KR900017200A - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

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Publication number
KR900017200A
KR900017200A KR1019900005484A KR900005484A KR900017200A KR 900017200 A KR900017200 A KR 900017200A KR 1019900005484 A KR1019900005484 A KR 1019900005484A KR 900005484 A KR900005484 A KR 900005484A KR 900017200 A KR900017200 A KR 900017200A
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KR
South Korea
Prior art keywords
insulating layer
silicon
layer
diffusion regions
silicon oxide
Prior art date
Application number
KR1019900005484A
Other languages
Korean (ko)
Other versions
KR930005081B1 (en
Inventor
슈이치 사마타
유우이치 미카다
도시로 우사미
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR900017200A publication Critical patent/KR900017200A/en
Application granted granted Critical
Publication of KR930005081B1 publication Critical patent/KR930005081B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음.No content.

Description

반도체장치Semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 1실시예를 나타낸 반도체장치에 포함되는 MOSFET의 단면도.1 is a cross-sectional view of a MOSFET included in a semiconductor device of one embodiment according to the present invention.

제2도는 제1도에 나타낸 MOSFET의 제조방법을 나타낸 단면도.2 is a cross-sectional view showing a method of manufacturing a MOSFET shown in FIG.

제3도는 접촉저항치의 본 발명에 따른 예와 종래예와의 비교를 나타낸 단면도.3 is a cross-sectional view showing a comparison between an example according to the present invention and a conventional example of contact resistance values.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : P형 실리콘기판 2 : N형 확산영역1: P type silicon substrate 2: N type diffusion region

3 : 산화실리콘절연층 4 : 관통구멍3: silicon oxide insulating layer 4: through hole

5 : 배선층 6 : 공동(空洞)5: wiring layer 6: cavity

7 : 단결정실리콘층 41 : 반도체기판7: single crystal silicon layer 41: semiconductor substrate

42 : 소자분리영역(SiO2층) 43 : 열산화막(게이트산화막)42: device isolation region (SiO 2 layer) 43: thermal oxide film (gate oxide film)

45 : 게이트전극 46 : 확산영역(소스영역)45 gate electrode 46 diffusion region (source region)

47 : 확산영역(드레인영역) 48 : 산화실리콘절연층(PSG)47 diffusion region (drain region) 48 silicon oxide insulating layer (PSG)

49 : 산화실리콘절연층(BPSG) 50 : 질화실리콘절연층49 silicon oxide insulating layer (BPSG) 50 silicon nitride insulating layer

51S,51D : 소스 및 드레인 실리콘반도체층51S, 51D: Source and Drain Silicon Semiconductor Layer

52S,52D : 소스 및 드레인 배선층52S, 52D: Source and Drain Wiring Layer

Claims (1)

반도체기판(41)의 주면(主面)에 노출되어 선택적으로 형성되는 확산영역(46, 47)과, 이 확산영역(46, 47)위에 형성되는 산화실리콘절연층(49), 이 산화실리콘절연층(49)위에 적층되는 질화실리콘절연층(50), 이 질화실리콘절연층(50)의 주면에서 상기 산화실리콘절연층(49)를 통해 상기 확산영역(46, 47)에 도달하는 관통구멍을 선택적으로 매립하는 낮은 비저항의 실리콘반도체층(51S, 51D), 이 실리콘반도체층(51S, 51D)에 접속되어 상기 질화실리콘절연층(50)위에 형성되는 배선층(51S, 51D)을 구비하여 구성된 것을 특징으로 하는 반도체장치.Diffusion regions 46 and 47 selectively exposed on the main surface of the semiconductor substrate 41, silicon oxide insulating layer 49 formed on the diffusion regions 46 and 47, and silicon oxide insulation The silicon nitride insulating layer 50 stacked on the layer 49 and through holes reaching the diffusion regions 46 and 47 through the silicon oxide insulating layer 49 on the main surface of the silicon nitride insulating layer 50 are formed. A low resistivity silicon semiconductor layer 51S, 51D which is selectively embedded, and wiring layers 51S, 51D connected to the silicon semiconductor layers 51S, 51D and formed on the silicon nitride insulating layer 50. A semiconductor device characterized by the above-mentioned. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900005484A 1989-04-19 1990-04-19 Semiconductor device KR930005081B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1099265A JP2659798B2 (en) 1989-04-19 1989-04-19 Semiconductor device
JP1-99265 1989-04-19

Publications (2)

Publication Number Publication Date
KR900017200A true KR900017200A (en) 1990-11-15
KR930005081B1 KR930005081B1 (en) 1993-06-15

Family

ID=14242866

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900005484A KR930005081B1 (en) 1989-04-19 1990-04-19 Semiconductor device

Country Status (2)

Country Link
JP (1) JP2659798B2 (en)
KR (1) KR930005081B1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57136366A (en) * 1982-01-11 1982-08-23 Fujitsu Ltd Manufacture of semiconductor device
JPS604258A (en) * 1983-06-23 1985-01-10 Nec Corp Structure of semiconductor device
JPS60123061A (en) * 1983-12-07 1985-07-01 Matsushita Electronics Corp Semiconductor device

Also Published As

Publication number Publication date
JP2659798B2 (en) 1997-09-30
KR930005081B1 (en) 1993-06-15
JPH02278769A (en) 1990-11-15

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