KR900007203A - 고속 직렬 데이타 링크 - Google Patents
고속 직렬 데이타 링크Info
- Publication number
- KR900007203A KR900007203A KR1019890014549A KR890014549A KR900007203A KR 900007203 A KR900007203 A KR 900007203A KR 1019890014549 A KR1019890014549 A KR 1019890014549A KR 890014549 A KR890014549 A KR 890014549A KR 900007203 A KR900007203 A KR 900007203A
- Authority
- KR
- South Korea
- Prior art keywords
- high speed
- serial data
- data link
- speed serial
- link
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
- H03M5/145—Conversion to or from block codes or representations thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US256,954 | 1981-04-23 | ||
US25695488A | 1988-10-12 | 1988-10-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900007203A true KR900007203A (ko) | 1990-05-09 |
KR0141918B1 KR0141918B1 (ko) | 1998-07-01 |
Family
ID=22974285
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890014549A KR0141918B1 (ko) | 1988-10-12 | 1989-10-11 | 고속 직렬 데이타 링크 |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0364170B1 (ko) |
JP (1) | JP2851076B2 (ko) |
KR (1) | KR0141918B1 (ko) |
DE (1) | DE68927217T2 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4020719A1 (de) * | 1990-06-29 | 1992-01-02 | Broadcast Television Syst | Verfahren zur uebertragung eines digitalen datensignals |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51136223A (en) * | 1975-05-21 | 1976-11-25 | Hitachi Ltd | Bit insertion circuit |
JPS60152155A (ja) * | 1984-01-20 | 1985-08-10 | Hitachi Ltd | 符号化方式 |
JPS61292434A (ja) * | 1985-05-17 | 1986-12-23 | Fujitsu Ltd | バツフアメモリ |
-
1989
- 1989-10-06 EP EP89310250A patent/EP0364170B1/en not_active Expired - Lifetime
- 1989-10-06 DE DE68927217T patent/DE68927217T2/de not_active Expired - Fee Related
- 1989-10-11 JP JP1264828A patent/JP2851076B2/ja not_active Expired - Fee Related
- 1989-10-11 KR KR1019890014549A patent/KR0141918B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0364170A3 (en) | 1991-12-11 |
DE68927217T2 (de) | 1997-01-30 |
KR0141918B1 (ko) | 1998-07-01 |
EP0364170A2 (en) | 1990-04-18 |
DE68927217D1 (de) | 1996-10-24 |
JPH02211744A (ja) | 1990-08-23 |
EP0364170B1 (en) | 1996-09-18 |
JP2851076B2 (ja) | 1999-01-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20070112 Year of fee payment: 10 |
|
LAPS | Lapse due to unpaid annual fee |