KR900005600B1 - Bright signal amplifing circuit - Google Patents

Bright signal amplifing circuit Download PDF

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Publication number
KR900005600B1
KR900005600B1 KR1019870012747A KR870012747A KR900005600B1 KR 900005600 B1 KR900005600 B1 KR 900005600B1 KR 1019870012747 A KR1019870012747 A KR 1019870012747A KR 870012747 A KR870012747 A KR 870012747A KR 900005600 B1 KR900005600 B1 KR 900005600B1
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South Korea
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transistor
resistor
luminance signal
adder
base
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KR1019870012747A
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Korean (ko)
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KR890009192A (en
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김헌욱
현윤종
박영서
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삼성반도체통신 주식회사
강진구
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Priority to KR1019870012747A priority Critical patent/KR900005600B1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/57—Control of contrast or brightness
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/148—Video amplifiers

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

The circuit comprises an amplification section (1), a buffer section (2), resistor elements (3,4), a band pass filter (5), a limitter (6), and an adder (7). The luminance signal input terminal (a) is connected with the bases of TR1, TR2. The output of the amplification section is coupled to the band pass filter and the bases of TR6, TR5, through R3, R4. The limitter is connected with the bases of TR7, TR9 in the adder, and The emitter of TR4 is linked to the connecting terminal of R10, R12 in the adder.

Description

휘도신호 증폭회로Luminance signal amplification circuit

제1도는 본 고안 휘도신호 증폭회로의 불럭도.1 is a block diagram of the luminance signal amplifying circuit of the present invention.

제2도는 본 고안 휘도신호 증폭회로도.2 is a luminance signal amplification circuit diagram of the present invention.

제3a~c도는 본 고안 휘도신호 증폭회로의 각부 파형도.3A to 3C are waveform diagrams of respective parts of the luminance signal amplifying circuit of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 증폭단 2 : 완충단1: amplification stage 2: buffer stage

3,4 : 저항소자 5 : 저역통과 필터3,4 resistance element 5: low pass filter

6 : 제한기 7 : 가산기6: limiter 7: adder

TR1~TR11: 트랜지스터 R1~R15: 저항TR 1 to TR 11 : Transistors R 1 to R 15 : Resistance

C1: 콘덴서 D1,D2: 다이오드C 1 : condenser D 1 , D 2 : diode

본 발명은 영상신호 처리장치의 휘도신호 처리에 관한 것으로, 재생시 뚜렷한 명암의 대비를 갖는 고화질의 화면을 얻을 수 있도록 하기 위한 휘도신호 증폭회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to luminance signal processing of an image signal processing apparatus, and relates to a luminance signal amplifying circuit for obtaining a high quality screen having a distinct contrast in reproduction.

종래의 영상신호 처리장치는 영상신호 기록시 고주파 대역의 휘도신호 성분을 충분히 증폭하지 않고 기록하였으므로, 이를 재생시 고주파 대역의 휘도신호가 신호처리 과정을 거치면서 감소되어 화면의 선명도가 떨어지는 문제점이 발생되었다.In the conventional video signal processing apparatus, since the luminance signal component of the high frequency band is not sufficiently amplified when the image signal is recorded, the luminance signal of the high frequency band is reduced during the signal processing to reduce the sharpness of the screen. It became.

본 발명은 이와 같은 문제점을 감안하여 영상신호의 기록시 휘도신호를 증폭하여 기록함으로써, 영상신호의 재생시 고주파 대역신호의 감소현상에 대응하여 선명한 화면을 얻을 수 있도록 안출한 것으로 이를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.In view of the above problems, the present invention amplifies and records a luminance signal during recording of a video signal, thereby providing a clear screen in response to the reduction of a high frequency band signal when the video signal is reproduced. When described in detail as follows.

제1도는 본 발명 휘도신호 증폭회로의 블록도로써, 휘도신호 입력단자(a)가 증폭단(1) 및 완충단(2)에 접속되어 있고, 증폭단(1)은 저항소자(3)를 통해 저역통과 필터(5)를 거쳐 제한기(6)에 접속됨과 아울러 저항소자(4)를 통해 제한기(6)에 접속되며, 제한기(6)는 가산기(7)를 거쳐 출력단자(b)에 접속되는 한편, 완충단(2)은 가산기(7)에 접속되어 구성되어 있고, 제2도는 본 발명 휘도신호 증폭회로의 상세 회로도로써, 휘도신호 입력단자(a)가 트랜지스터(TR1)(TR2) 및 저항(R1)(R2)이 접속되어 구성되어 있는 증폭단(1)의 트랜지스터(TR1)의 베이스 및 트랜지스터(TR3)(TR4)로 구성되어 있는 완충단(2)의 트랜지스터(TR3)의 베이스에 접속되고, 증폭단(1)은 저항(R3)으로 구성된 저항소자(3)를 통하여 저항(R9), 콘덴서(C1)로 구성된 저역통과 필터(5)의 저항(R9)의 일측단자와 트랜지스터(TR5)(TR6), 저항(R5)~(TR8), 다이오드(D1)(D2)로 접속되어 구성된 제한기(6)의 트랜지스터(TR6)의 베이스에 공통접속되는 한편, 상기 증폭단(1)은 저항(R4)을 통하여 제한기(6)의 트랜지스터(TR5)의 베이스에 접속되며, 제한기(6)는 트랜지스터(TR7)~(TR11) 및 저항(R10)~(R)15)으로 구성된 가산기(7)의 트랜지스터(TR7)(TR9)의 베이스에 각각 접속되어 있고 가산기(7)의 저항(R10)(R12)의 접속단자에 완충단(2)의 트랜지스터(TR4)의 에미터가 접속되어 구성되어 있다.1 is a block diagram of the luminance signal amplifying circuit of the present invention, in which a luminance signal input terminal (a) is connected to an amplifier stage (1) and a buffer stage (2), and the amplifier stage (1) is connected to a low pass through a resistance element (3). It is connected to the limiter 6 via the pass filter 5 and is connected to the limiter 6 through the resistance element 4, and the limiter 6 is connected to the output terminal b via the adder 7. On the other hand, the buffer stage 2 is connected to the adder 7, and FIG. 2 is a detailed circuit diagram of the luminance signal amplifying circuit of the present invention, in which the luminance signal input terminal a is a transistor TR 1 (TR). 2 ) of the buffer stage 2 composed of the base of the transistor TR 1 and the transistor TR 3 and TR 4 of the amplifier stage 1 connected to each other and the resistors R 1 and R 2 . The amplifying stage 1 is connected to the base of the transistor TR 3 , and the amplifying stage 1 is connected to the low pass filter 5 composed of the resistor R 9 and the capacitor C 1 through the resistor element 3 composed of the resistor R 3 . resistance (R 9) The base of one terminal and the transistor (TR 5) (TR 6), a resistance (R 5) ~ (TR 8 ), the diode (D 1), the transistor (TR 6) of the restrictor (6) is configured is connected to the (D 2) The amplifier stage 1 is connected to the base of the transistor TR 5 of the limiter 6 via a resistor R 4 , while the limiter 6 is connected to transistors TR 7 to TR. 11 ) and the resistors R 10 (R 12 ) of the adder 7 connected to the bases of the transistors TR 7 (TR 9 ) of the adder 7 respectively composed of the resistors R 10 to R 15. The emitter of the transistor TR 4 of the buffer terminal 2 is connected to the connection terminal of ().

이상에서와 같이 구성된 본 발명 휘도신호 증폭회로의 작용효과를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.If described in detail by the accompanying drawings the effect of the present invention the luminance signal amplifying circuit configured as described above are as follows.

제2도에 도시된 바와 같이 본 발명 휘도신호 증폭회로에 있어서, 전원단자(Vcc)에 전원을 인가하고 휘도신호 입력단자(a)에 제3a도에 도시한 바와 같이 휘도신호가 입력되면, 상기 휘도신호는 저항(R2)이 트랜지스터(TR1)의 에미터에 접속되고 트랜지스터(TR1)의 콜렉터에 저항(R1) 및 트랜지스터(TR2)의 베이스가 공통 접속된 증폭단(1)을 통하여 2단 증폭되어 트랜지스터(TR2)의 에미터에 출력되며, 증폭된 휘도신호는 저항소자(3)인 저항(R3)을 통하여 저항(R9), 콘덴서(C1)로 구성된 저역통과필터(5)에 입력되어 필터링되고, 이는 다시 저항(R5)~(R8) 및 트랜지스터(TR5)(TR6), 다이오드(D1)(D2)로 접속되어 차동증폭형으로 구성된 제한기(6)의 트랜지스터(TR6)의 베이스에 입력됨과 아울러, 저항소자(4)인 저항(R4)을 통하여 트랜지스터(TR5)의 베이스에 입력되며, 제한기(6)에 입력된 양 신호는 차동 증폭되어 고주파 부분이 증폭된 신호가 출력되는 한편 다이오드(D1)(D2)에 의하여 제한되어 제3b도에 도시한 바와 같이 레벨이 제한된 신호를 출력한다. 이와 같이 레벨이 제한된 신호는 완충기(2)에서 출력된 원신호가 입력되고 저항(R10)~(R15) 및 다알링톤 접속된 트랜지스터(TR7)(TR8)와 트랜지스터(TR9)(TR10)가 차동 증폭형으로 구성되어 트랜지스터(TR11)를 통하여 출력되는 가산기(7)에 입력되어, 상기 가산기(7)에서 원신호에 일정 주파수 이상의 고주파 대역이 입력신호 레벨에 따라 증폭도가 다른 신호가 더해짐으로써 제3c도에 도시한 바와 같이 원신호에 비하여 고주파 대역이 강조된 신호가 출력하게 된다.In the luminance signal amplifying circuit of the present invention as shown in FIG. 2, when the power is applied to the power supply terminal Vcc and the luminance signal is input to the luminance signal input terminal a as shown in FIG. the luminance signal is the resistance (R 2) and the transistor resistance to the collector of (TR 1) is connected to the emitter of the transistor (TR 1) (R 1) and the amplifier stage (1) the base is the common connection of the transistor (TR 2) It is amplified in two stages and output to the emitter of the transistor TR 2 , and the amplified luminance signal is a low pass composed of a resistor R 9 and a capacitor C 1 through a resistor R 3 , which is a resistor element 3. Filtered by input to the filter (5), which is connected to the resistors (R 5 ) to (R 8 ) and the transistors (TR 5 ) (TR 6 ), diode (D 1 ) (D 2 ) and configured in a differential amplification type limiter soon as the input to the base of the transistor (TR 6) (6) in addition, the base of the transistor (TR 5) through a resistance (R 4) resistance elements 4 Input is, the positive signal input to the limiter 6 is the differential amplifying limited by the other hand the diode (D 1) (D 2) in which the high frequency portion of the amplified signal output level as shown in the 3b FIG. Output a limited signal. The signal whose level is limited is inputted from the original signal output from the shock absorber 2, and the resistors R 10 to R 15 and the multi-arling tone connected transistors TR 7 (TR 8 ) and transistor TR 9 ( TR 10 ) is configured as a differential amplification type and is input to an adder 7 outputted through the transistor TR 11 , so that a high frequency band of a predetermined frequency or more differs depending on the input signal level from the adder 7 to the original signal. As the signal is added, a signal in which a high frequency band is emphasized as compared to the original signal is output as shown in FIG. 3C.

이상에서와 같이 본 발명 휘도신호 증폭회로에 의하여 고주파 대역이 강조된 신호를 출력함으로써, 영상신호 재생시 발생되는 휘도신호 감소현상에 대비하여 재생후 뚜렷한 명암대비를 갖는 고화질의 화면을 얻을 수 있는 장점이 있는 것이다.As described above, by outputting a signal in which a high frequency band is emphasized by the luminance signal amplifying circuit of the present invention, a high quality screen having a distinct contrast after reproduction is obtained in preparation for the reduction of the luminance signal generated during image signal reproduction. It is.

Claims (1)

휘도신호 입력단자(a)가 트랜지스터(TR1)(TR2) 및 저항(R1)(R2)이 접속되어 구성되어 있는 증폭단(1)의 트랜지스터(TR1)의 베이스 및 트랜지스터(TR3)(TR4)로 구성되어 있는 완충단(2)의 트랜지스터(TR3)의 베이스에 접속되고, 증폭단(1)은 저항(R3)으로 구성된 저항소자(3)를 통하여 저항(R9), 콘덴서(C1)로 구성된 저역통과 필터(5)의 저항(R9)의 일측단자와 트랜지스터(TR5)(TR6), 저항(R5)~(R8), 다이오드(D1)(D2)로 접속되어 구성된 제한기(6)의 트랜지스터(TR)의 베이스에 공통 접속되는 한편, 상기 증폭단(1)은 저항(R4)을 통하여 제한기(6)의 트랜지스터(TR5)의 베이스에 접속되며, 제한기(6)는 트랜지스터(TR7)~(TR11) 및 저항(R10)~(TR15)으로 구성된 가산기(7)의 트랜지스터(TR7)(TR9)의 베이스에 각각 접속되어 있고 가산기(7)의 저항(R10)(R12)의 접속단자에 완충단(2)의 트랜지스터(TR4)의 에미터가 접속되어 구성됨을 특징으로 한 휘도신호 증폭회로.The base and transistor TR 3 of the transistor TR 1 of the amplifier stage 1 in which the luminance signal input terminal a is connected to a transistor TR 1 (TR 2 ) and a resistor R 1 (R 2 ). Is connected to the base of the transistor TR 3 of the buffer stage 2 constituted by TR 4 , and the amplification stage 1 is connected to the resistor R 9 via a resistor element 3 composed of the resistor R 3 . , One side of the resistor R 9 of the low pass filter 5 composed of the capacitor C 1 , the transistors TR 5 , TR 6 , resistors R 5 , R 8 , and diode D 1 The amplifier stage 1 is connected to the base of the transistor TR of the limiter 6, which is connected to (D 2 ), while the amplifier stage 1 is connected to the transistor TR 5 of the limiter 6 via a resistor R 4 . of being connected to the base, limiter 6 has a transistor (TR 7) ~ (TR 11) and a resistor (R 10) ~ transistor (TR 7) (TR 9) of the adder (7) consisting of (TR 15) It is connected to the base and the resistance of the adder (7) (R 10) ( R 12) Welding of A luminance characterized by the emitter is connected consists of a transistor (TR 4) of a stage (2) buffering the terminal signal amplifier circuit.
KR1019870012747A 1987-11-12 1987-11-12 Bright signal amplifing circuit KR900005600B1 (en)

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Application Number Priority Date Filing Date Title
KR1019870012747A KR900005600B1 (en) 1987-11-12 1987-11-12 Bright signal amplifing circuit

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Application Number Priority Date Filing Date Title
KR1019870012747A KR900005600B1 (en) 1987-11-12 1987-11-12 Bright signal amplifing circuit

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KR890009192A KR890009192A (en) 1989-07-13
KR900005600B1 true KR900005600B1 (en) 1990-07-31

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