KR900004026A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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Publication number
KR900004026A
KR900004026A KR1019890011867A KR890011867A KR900004026A KR 900004026 A KR900004026 A KR 900004026A KR 1019890011867 A KR1019890011867 A KR 1019890011867A KR 890011867 A KR890011867 A KR 890011867A KR 900004026 A KR900004026 A KR 900004026A
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KR
South Korea
Prior art keywords
electrode
semiconductor device
insulating film
forming
silicon
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KR1019890011867A
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Korean (ko)
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KR940008564B1 (en
Inventor
야스노리 나까자끼
가즈끼 히라까와
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야마무라 가쯔미
세이꼬 엡슨 가부시끼가이샤
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Publication of KR900004026A publication Critical patent/KR900004026A/en
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Publication of KR940008564B1 publication Critical patent/KR940008564B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8615—Hi-lo semiconductor devices, e.g. memory devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Read Only Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음.No content.

Description

반도체 소자 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 반도체 소자의 한 실시예의 부분적 횡단면도.1 is a partial cross-sectional view of one embodiment of a semiconductor device according to the present invention.

제3도는 본 발명에 따른 반도체 소자의 다른 실시예의 부분적 횡단면도.3 is a partial cross-sectional view of another embodiment of a semiconductor device according to the present invention.

제4도는 본 발명에 따른 반도체 소자의 다른 실시예의 부분적 횡단면도.4 is a partial cross-sectional view of another embodiment of a semiconductor device according to the present invention.

Claims (6)

반도체 기판의 표면상에 형성된 전극을 갖고 있되, 그 전극에 전압을 부과함으로써 공급되는 전류에 의해 그 전극 중 한 전극과 다른 전극 사이에서 고저항 상태로부터 저저항 상태로의 변이를 야기하는 그런 전극을 갖고 있는 반도체 소자에 있어서, 상기 반도체 전극이 상부 전극과 비결정성 실리콘 및 실리콘 산화물 절연막과 하부 전극의 4층 구조로 구성되어 있는 것을 특징으로 하는 반도체 소자.And having an electrode formed on the surface of the semiconductor substrate, which causes a transition from a high resistance state to a low resistance state between one of the electrodes and the other by a current supplied by applying a voltage to the electrode. A semiconductor device having a semiconductor device, wherein the semiconductor electrode has a four-layer structure of an upper electrode, amorphous silicon, a silicon oxide insulating film, and a lower electrode. 제1항에 있어서, 상기 한 전극이 반도체 기판의 표면상에 형성된 불순물 확산층으로 구성되어 있는 것을 특징으로 하는 반도체 소자.The semiconductor device according to claim 1, wherein said one electrode is composed of an impurity diffusion layer formed on a surface of a semiconductor substrate. 제1항에 있어서, 상기 한 전극이 다결정 실리콘으로 구성되어 있는 것을 특징으로 하는 반도체 소자.The semiconductor device according to claim 1, wherein said one electrode is made of polycrystalline silicon. 제1항 내지 제3항중 어느 한 항에 있어서, 비결정성 실리콘이 Ⅲ그룹 또는 V그룹의 불순물 요소를 포함하고 있는 것을 특징으로 하는 반도체 소자.The semiconductor device according to any one of claims 1 to 3, wherein the amorphous silicon contains an impurity element of group III or group V. 전극에 전압을 부과함으로써 공급되는 전류에 의해 전극중 한 전극과 다른 전극 사이에서 고저항 상태로부터 저저항 상태로의 변이를 야기하는, 반도체 기판의 표면상에 형성된 전극을 가진 반도체 소자를 제조하는 방법에 있어서, 하부 전국이 형성된 반도체 기판상에 층간 절연막을 형성하는 단계와, 상기 층간 절연막에 콘택트 홀을 한정하는 단계와, CVD방법이나 열적 산화방법 또는 H2SO4+ H2O2처리에 의해 상기 콘택트 홀의 바닥에 실리콘 절연막을 형성하고, 전체 표면에 비결정성 실리콘을 침착시키고, 포토 에칭에 의해 상기 실리콘 산화막상에 비결정성 실리콘층을 패턴닝하는 단계와, 층간 절연막을 더 형성하고, 상기 전극중 다른 전극의 도선을 위해 상기 비결정성 실리콘에 콘택트 홀을 한정하는 단계와, 전체 표면에 전극 물질을 증기 침착시키고, 패턴닝에 의해 상기 비결정성 실리콘상에 상부 전극 및 상기 전극의 도선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.A method of manufacturing a semiconductor device having an electrode formed on a surface of a semiconductor substrate which causes a transition from a high resistance state to a low resistance state between one of the electrodes and the other by a current supplied by applying a voltage to the electrode. Forming an interlayer insulating film on a semiconductor substrate having a lower whole area, defining a contact hole in the interlayer insulating film, and performing a CVD method, a thermal oxidation method, or a H 2 SO 4 + H 2 O 2 process. Forming a silicon insulating film on the bottom of the contact hole, depositing amorphous silicon on the entire surface, patterning an amorphous silicon layer on the silicon oxide film by photo etching, further forming an interlayer insulating film, and forming the electrode Defining a contact hole in the amorphous silicon for conducting the other electrode, and vaporizing the electrode material over the entire surface And, by patterning a semiconductor device comprising the steps of forming a top electrode and a lead of the electrode on the amorphous silicon production method. 전극에 전압을 부과함으로써 공급되는 전류에 의해 전극중 한 전극과 다른 전극 사이에서 고저항 상태로부터 저저항 상태로의 변이를 야기하는, 반도체 기판의 표면상에 형성된 전극을 가진 반도체 소자를 제조하는 방법에 있어서, 불순물 확산층이 형성된 반도체 기판상에 층간 절연막을 형성하는 단계와, 상기 층간 절연막에 콘택트 홀을 한정하는 단계와, 상기 콘택트 홀의 바닥 부분까지 비결정성 실리콘을 침착시키고 포토 에칭에 의해 상기 비결정성 실리콘층을 패턴닝하는 단계와, CVD방법에 의해 실리콘 절연막을 형성하고 상기 비결정성 실리콘층에만 실리콘 절연막을 형성하는 단계와, 층간막을 한정하고, 상기 전극의 도선을 위해 2개의 콘택트 홀을 한정하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.A method of manufacturing a semiconductor device having an electrode formed on a surface of a semiconductor substrate which causes a transition from a high resistance state to a low resistance state between one of the electrodes and the other by a current supplied by applying a voltage to the electrode. Forming an interlayer insulating film on a semiconductor substrate having an impurity diffusion layer, defining a contact hole in the interlayer insulating film, depositing amorphous silicon to the bottom portion of the contact hole and depositing the amorphous by photoetching. Patterning a silicon layer, forming a silicon insulating film by a CVD method, forming a silicon insulating film only on the amorphous silicon layer, defining an interlayer film, and defining two contact holes for the lead of the electrode A semiconductor device manufacturing method comprising the step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890011867A 1988-08-23 1989-08-21 Semiconductor device and manufacturing method thereof KR940008564B1 (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP63-185387 1988-07-27
JP63-209034 1988-08-23
JP20903488 1988-08-23
JP1-124486 1989-05-19
JP1124486A JPH02153552A (en) 1988-08-23 1989-05-19 Semiconductor element and its manufacture
JP63-124486 1989-05-19
JP1-185387 1989-07-18
JP18538789A JPH0756884B2 (en) 1988-08-23 1989-07-18 Method for manufacturing semiconductor device

Publications (2)

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KR900004026A true KR900004026A (en) 1990-03-27
KR940008564B1 KR940008564B1 (en) 1994-09-24

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KR (1) KR940008564B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5595352A (en) * 1994-03-23 1997-01-21 Shin A Sports Co., Ltd. Bail arm inverting apparatus for a fishing reel

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714024B2 (en) * 1990-11-29 1995-02-15 川崎製鉄株式会社 Multi-chip module
US5625220A (en) * 1991-02-19 1997-04-29 Texas Instruments Incorporated Sublithographic antifuse
US5100827A (en) * 1991-02-27 1992-03-31 At&T Bell Laboratories Buried antifuse
JP2864774B2 (en) * 1991-03-26 1999-03-08 三菱電機株式会社 Adjustment method for semiconductor device
US5701027A (en) * 1991-04-26 1997-12-23 Quicklogic Corporation Programmable interconnect structures and programmable integrated circuits
US5557136A (en) * 1991-04-26 1996-09-17 Quicklogic Corporation Programmable interconnect structures and programmable integrated circuits
US5196724A (en) * 1991-04-26 1993-03-23 Quicklogic Corporation Programmable interconnect structures and programmable integrated circuits
US5314840A (en) * 1992-12-18 1994-05-24 International Business Machines Corporation Method for forming an antifuse element with electrical or optical programming
US6156588A (en) * 1998-06-23 2000-12-05 Vlsi Technology, Inc. Method of forming anti-fuse structure
JP5525694B2 (en) 2007-03-14 2014-06-18 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method of semiconductor device
JP5641840B2 (en) * 2009-10-01 2014-12-17 株式会社半導体エネルギー研究所 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5595352A (en) * 1994-03-23 1997-01-21 Shin A Sports Co., Ltd. Bail arm inverting apparatus for a fishing reel

Also Published As

Publication number Publication date
KR940008564B1 (en) 1994-09-24
JPH0756884B2 (en) 1995-06-14
JPH02146745A (en) 1990-06-05
JPH02153552A (en) 1990-06-13

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