KR900002422A - A method for forming a high concentration source region and a capacitor surface region of a semiconductor device using sidewall doping technology (SSWDT) and its semiconductor integrated device - Google Patents

A method for forming a high concentration source region and a capacitor surface region of a semiconductor device using sidewall doping technology (SSWDT) and its semiconductor integrated device Download PDF

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Publication number
KR900002422A
KR900002422A KR1019880009184A KR880009184A KR900002422A KR 900002422 A KR900002422 A KR 900002422A KR 1019880009184 A KR1019880009184 A KR 1019880009184A KR 880009184 A KR880009184 A KR 880009184A KR 900002422 A KR900002422 A KR 900002422A
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KR
South Korea
Prior art keywords
forming
source region
semiconductor integrated
layer
silicon wafer
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Application number
KR1019880009184A
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Korean (ko)
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KR920000707B1 (en
Inventor
오상묵
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정몽헌
현대전자산업 주식회사
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Priority to KR1019880009184A priority Critical patent/KR920000707B1/en
Publication of KR900002422A publication Critical patent/KR900002422A/en
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Publication of KR920000707B1 publication Critical patent/KR920000707B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

측면벽 도핑기술(SSWDT)을 이용한 반도체 소자의 고농도 소스영역 및 캐패시터 표면영역 형성방법과 그 반도체 집적소자A method for forming a high concentration source region and a capacitor surface region of a semiconductor device using sidewall doping technology (SSWDT) and its semiconductor integrated device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제2C도는 본 발명의 소스영역 및 캐패시터 표면영역 형성방법을 설명하기 위한 도시도로서, 제1A도는 본 발명을 설명하기 위해 웨이퍼상에 마스크층을 형성한 후 포토레지스터층을 코팅한 상태의 단면도.1A to 2C are diagrams for explaining a method for forming a source region and a capacitor surface region of the present invention. FIG. 1A is a view illustrating a method of forming a mask layer on a wafer and then coating a photoresist layer to explain the present invention. Section of status.

제1B도는 제1A도에서 포토레지스터층의 일부분을 제거한 상태의 단면도.FIG. 1B is a cross-sectional view of a portion of the photoresist layer removed from FIG. 1A. FIG.

제1C도는 제1B도에서 마스크 패턴을 형성하고 잔여 포토레지스터층을 제거한 상태의 단면도.FIG. 1C is a cross-sectional view of a mask pattern formed in FIG. 1B and a residual photoresist layer removed.

Claims (2)

메가 D RAM급 이상의 반도체 고집적 소자의 소스영역 형성방법에 있어서, 실리콘 웨이퍼 위에 산화물층을 침착하고 그위에 질화물층을 도핑하여 마스크층을 형성한 다음, 포토레지스터를 코팅하는 공정과, 상기 포토레지스터층의 일정부분을 제거시켜 노출된 마스크층을 실리콘 표면까지 에칭하여 마스크 패턴을 형성하고 포토레지스터층을 제거하는 공정과, 상기 마스크 패턴형성에 의해 노출된 실리콘 웨이퍼상에 트랜치를 형성하고 도프산화물을 일정한 두께로 침착한 후, 이 침착물을 부분에칭하여 질화물층 및 트랜치 구조저부의 침착물을 제거한 다음 고열처리하여 실리콘 웨이퍼 내부벽 양측에 상기 물질이 주입되는 도핑영역을 형성하고, 상기 침착물질을 에칭처리로 제거하는 공정으로 이루어지는 것을 특징으로 측면벽 도핑기술을 이용한 반도체 소자의 소스영역 형성방법.A method for forming a source region of a semiconductor high-density device of mega D RAM or more, comprising: depositing an oxide layer on a silicon wafer, doping a nitride layer thereon, forming a mask layer, and then coating a photoresist layer; Etching a portion of the exposed mask layer to a silicon surface to form a mask pattern and removing a photoresist layer; forming a trench on the exposed silicon wafer by forming the mask pattern and forming a dope oxide After depositing to a thickness, the deposit is partially etched to remove deposits from the nitride layer and the bottom of the trench structure, followed by high heat treatment to form doped regions into which the material is implanted on both sides of the silicon wafer inner wall, and the deposited material is etched. Half using side wall doping technology, characterized in that the process consisting of removing the Source region formation method of a conductor element. 반도체 집적소자에 있어서, 실리콘 웨이퍼상에 마스크 패턴을 형성시키고 트랜치 구조를 형성하여 도프산화물을 침착처리에 의해 상기 트랜치 구조의 좌, 우 측면벽 전체에 도핑영역인 소스영역을 가진 트랜치 캐패시터를 포함하는 것을 특징으로 하는 반도체 집적소자.A semiconductor integrated device comprising a trench capacitor having a source region serving as a doping region on the left and right sidewalls of the trench structure by forming a mask pattern on a silicon wafer and forming a trench structure by depositing dope oxide. Semiconductor integrated device, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880009184A 1988-07-22 1988-07-22 Manufacturing method of trench with high-density diffusion region KR920000707B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880009184A KR920000707B1 (en) 1988-07-22 1988-07-22 Manufacturing method of trench with high-density diffusion region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880009184A KR920000707B1 (en) 1988-07-22 1988-07-22 Manufacturing method of trench with high-density diffusion region

Publications (2)

Publication Number Publication Date
KR900002422A true KR900002422A (en) 1990-02-28
KR920000707B1 KR920000707B1 (en) 1992-01-20

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KR1019880009184A KR920000707B1 (en) 1988-07-22 1988-07-22 Manufacturing method of trench with high-density diffusion region

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KR920000707B1 (en) 1992-01-20

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