KR900002422A - A method for forming a high concentration source region and a capacitor surface region of a semiconductor device using sidewall doping technology (SSWDT) and its semiconductor integrated device - Google Patents
A method for forming a high concentration source region and a capacitor surface region of a semiconductor device using sidewall doping technology (SSWDT) and its semiconductor integrated device Download PDFInfo
- Publication number
- KR900002422A KR900002422A KR1019880009184A KR880009184A KR900002422A KR 900002422 A KR900002422 A KR 900002422A KR 1019880009184 A KR1019880009184 A KR 1019880009184A KR 880009184 A KR880009184 A KR 880009184A KR 900002422 A KR900002422 A KR 900002422A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- source region
- semiconductor integrated
- layer
- silicon wafer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 6
- 239000003990 capacitor Substances 0.000 title claims description 3
- 239000004065 semiconductor Substances 0.000 title claims 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 5
- 229910052710 silicon Inorganic materials 0.000 claims 5
- 239000010703 silicon Substances 0.000 claims 5
- 238000000151 deposition Methods 0.000 claims 3
- 239000000463 material Substances 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1A도 내지 제2C도는 본 발명의 소스영역 및 캐패시터 표면영역 형성방법을 설명하기 위한 도시도로서, 제1A도는 본 발명을 설명하기 위해 웨이퍼상에 마스크층을 형성한 후 포토레지스터층을 코팅한 상태의 단면도.1A to 2C are diagrams for explaining a method for forming a source region and a capacitor surface region of the present invention. FIG. 1A is a view illustrating a method of forming a mask layer on a wafer and then coating a photoresist layer to explain the present invention. Section of status.
제1B도는 제1A도에서 포토레지스터층의 일부분을 제거한 상태의 단면도.FIG. 1B is a cross-sectional view of a portion of the photoresist layer removed from FIG. 1A. FIG.
제1C도는 제1B도에서 마스크 패턴을 형성하고 잔여 포토레지스터층을 제거한 상태의 단면도.FIG. 1C is a cross-sectional view of a mask pattern formed in FIG. 1B and a residual photoresist layer removed.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019880009184A KR920000707B1 (en) | 1988-07-22 | 1988-07-22 | Manufacturing method of trench with high-density diffusion region |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019880009184A KR920000707B1 (en) | 1988-07-22 | 1988-07-22 | Manufacturing method of trench with high-density diffusion region |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900002422A true KR900002422A (en) | 1990-02-28 |
KR920000707B1 KR920000707B1 (en) | 1992-01-20 |
Family
ID=19276308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880009184A KR920000707B1 (en) | 1988-07-22 | 1988-07-22 | Manufacturing method of trench with high-density diffusion region |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR920000707B1 (en) |
-
1988
- 1988-07-22 KR KR1019880009184A patent/KR920000707B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR920000707B1 (en) | 1992-01-20 |
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G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
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Payment date: 20021223 Year of fee payment: 12 |
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