KR890015139A - Pseudo-scramble system of computer - Google Patents
Pseudo-scramble system of computer Download PDFInfo
- Publication number
- KR890015139A KR890015139A KR1019880002715A KR880002715A KR890015139A KR 890015139 A KR890015139 A KR 890015139A KR 1019880002715 A KR1019880002715 A KR 1019880002715A KR 880002715 A KR880002715 A KR 880002715A KR 890015139 A KR890015139 A KR 890015139A
- Authority
- KR
- South Korea
- Prior art keywords
- pseudo
- computer
- disk
- memory
- contents
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Storage Device Security (AREA)
Abstract
내용 없음.No content.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 개략 블록도.1 is a schematic block diagram of the present invention.
제2도는 제1도의 좀더 구체화된 요부블럭도.2 is a more detailed recessed block diagram of FIG.
제3도는 제1도의 논리제어회로부분을 좀더 구체화한 회로의 일예도,3 is an example of a circuit in which the logic control circuit portion of FIG. 1 is further embodied.
제4도의(가)는 본 발명의 마이크로컴퓨터에서 처리되는 메인프로그램의 플로우챠트,4A is a flowchart of a main program processed in a microcomputer of the present invention,
(나)는 본 발명의 마이크로컴퓨터에서 처리되는 인터럽트프로그램의 플로우챠트.(B) is a flowchart of an interrupt program processed by the microcomputer of the present invention.
Claims (2)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019880002715A KR910000590B1 (en) | 1988-03-14 | 1988-03-14 | Mirror disk ram system of computer |
JP1502352A JPH02501602A (en) | 1988-03-14 | 1989-02-14 | Mirror disk RAM system |
PCT/KR1989/000002 WO1989008885A1 (en) | 1988-03-14 | 1989-02-14 | Mirror disk ram system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019880002715A KR910000590B1 (en) | 1988-03-14 | 1988-03-14 | Mirror disk ram system of computer |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890015139A true KR890015139A (en) | 1989-10-28 |
KR910000590B1 KR910000590B1 (en) | 1991-01-26 |
Family
ID=19272840
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880002715A KR910000590B1 (en) | 1988-03-14 | 1988-03-14 | Mirror disk ram system of computer |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPH02501602A (en) |
KR (1) | KR910000590B1 (en) |
WO (1) | WO1989008885A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6850314B2 (en) * | 2019-03-05 | 2021-03-31 | 株式会社東海理化電機製作所 | User authentication device and user authentication method |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4500954A (en) * | 1981-10-15 | 1985-02-19 | International Business Machines Corporation | Cache bypass system with post-block transfer directory examinations for updating cache and/or maintaining bypass |
JPS60132256A (en) * | 1983-12-21 | 1985-07-15 | Hitachi Ltd | Data securing system of nonvolatile memory |
JPH0644245B2 (en) * | 1983-12-29 | 1994-06-08 | 富士通株式会社 | Store buffer device |
EP0203601B1 (en) * | 1985-05-29 | 1992-08-05 | Kabushiki Kaisha Toshiba | Cache system adopting an lru system, and magnetic disk controller incorporating it |
JPH087662B2 (en) * | 1985-10-18 | 1996-01-29 | 株式会社日立製作所 | Data transfer control method |
EP0232518A3 (en) * | 1986-01-13 | 1989-12-13 | Siemens Aktiengesellschaft | Address mapping method and system for controlling a working memory |
JPS6349924A (en) * | 1986-08-20 | 1988-03-02 | Matsushita Electric Ind Co Ltd | Rapid disk access device |
-
1988
- 1988-03-14 KR KR1019880002715A patent/KR910000590B1/en not_active IP Right Cessation
-
1989
- 1989-02-14 WO PCT/KR1989/000002 patent/WO1989008885A1/en unknown
- 1989-02-14 JP JP1502352A patent/JPH02501602A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
KR910000590B1 (en) | 1991-01-26 |
WO1989008885A1 (en) | 1989-09-21 |
JPH02501602A (en) | 1990-05-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19940110 Year of fee payment: 4 |
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LAPS | Lapse due to unpaid annual fee |