KR890009000A - 디지탈 집적 회로 - Google Patents

디지탈 집적 회로 Download PDF

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Publication number
KR890009000A
KR890009000A KR1019880014314A KR880014314A KR890009000A KR 890009000 A KR890009000 A KR 890009000A KR 1019880014314 A KR1019880014314 A KR 1019880014314A KR 880014314 A KR880014314 A KR 880014314A KR 890009000 A KR890009000 A KR 890009000A
Authority
KR
South Korea
Prior art keywords
transistor
digital integrated
power supply
integrated circuit
channel length
Prior art date
Application number
KR1019880014314A
Other languages
English (en)
Inventor
디트빈 하르트그링 코르넬리스
딕켄 얀
푸르테르 티멘
Original Assignee
이반 밀러 레르너
엔.브이.필립스 글로아이람펜파브리켄
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이반 밀러 레르너, 엔.브이.필립스 글로아이람펜파브리켄 filed Critical 이반 밀러 레르너
Publication of KR890009000A publication Critical patent/KR890009000A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

내용 없음

Description

디지탈 집적 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 디지탈 집적 회로의 실시도.
제2도는 본 발명에 따른 디지탈 집적 회로의 또다른 실시도.

Claims (5)

  1. 드레인이 출력 단자에 결합되며, 제1보조 회로를 통하여 제1전력 공급 단자에 접속되는 제1도전형의 MOS 트랜지스터를 구비하는데, 상기 트랜지스터의 게이트는 제1입력 단자에 접속되는 반면, 상기 트랜지스터의 소스는 제1도전형의 적어도 하나의 제2 MOS 트랜지스터를 가진 제2보조 회로를 통하여 제2전력 공급 단자에 접속되며, 제1 및 제2보조 회로는 제2입력 단자를 통하여 구동되는 디지탈 집적 회로에 있어서, 핫 캐리어 스트레스를 억압하기 위하여, 아래 단계중 적어도 한 단계가 취해지는데, 즉 한 단계에 따르면, 제1트렌지스터는 제2트랜지스터 보다 큰 임계 전압을 갖는 반면, 다른 단계에 따르면, 제1트랜지스터의 채널 길이는 제2트랜지스터 보다 큰 것을 특징으로 하는 디지탈 집적 회로.
  2. 제1항에 있어서, 제1입력 단자는 제1 및 제2전력 공급 전압치 사이의 전압을 운반하는 것을 특징으로 하는 디지탈 집적 회로.
  3. 제1항에 있어서, 제1도전형은 NMOS형인 것을 특징으로 하는 디지탈 집적 회로.
  4. 제3항에 있어서, 제1트랜지스터의 게이트는 NMOS 트랜지스터를 통하여 제1전력 공급 단자에 접속되는 것을 특징으로 하는 디지탈 집적 회로.
  5. 제1, 2 또는 3항에 있어서, 제1트랜지스터의 채널 길이는 1㎛보다 크고, 제2트랜지스터의 채널 길이는 1㎛보다 적은 것을 특징으로 하는 디지탈 집적 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880014314A 1987-11-04 1988-11-01 디지탈 집적 회로 KR890009000A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8702630 1987-11-04
NL8702630A NL8702630A (nl) 1987-11-04 1987-11-04 Geintegreerde digitale schakeling.

Publications (1)

Publication Number Publication Date
KR890009000A true KR890009000A (ko) 1989-07-13

Family

ID=19850862

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880014314A KR890009000A (ko) 1987-11-04 1988-11-01 디지탈 집적 회로

Country Status (5)

Country Link
US (1) US4920287A (ko)
EP (1) EP0316033A1 (ko)
JP (1) JPH01149448A (ko)
KR (1) KR890009000A (ko)
NL (1) NL8702630A (ko)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07109859B2 (ja) * 1988-09-03 1995-11-22 日本電気株式会社 Ｍｏｓ型半導体集積回路装置
US4996450A (en) * 1990-02-28 1991-02-26 Motorola, Inc. Data processor circuit and method for controlling voltage variation of a dynamic node
US5029283A (en) * 1990-03-28 1991-07-02 Ncr Corporation Low current driver for gate array
US5030854A (en) * 1990-04-05 1991-07-09 Gazelle Microcircuits, Inc. Translator circuit for converting ECL type signals to TTL type signals
US5117125A (en) * 1990-11-19 1992-05-26 National Semiconductor Corp. Logic level control for impact ionization sensitive processes
EP0571512A1 (en) * 1991-02-12 1993-12-01 Analog Devices, Inc. Gain linearity correction circuit for mos circuits
US5300832A (en) * 1992-11-10 1994-04-05 Sun Microsystems, Inc. Voltage interfacing buffer with isolation transistors used for overvoltage protection
US5359240A (en) * 1993-01-25 1994-10-25 National Semiconductor Corporation Low power digital signal buffer circuit
JP3379601B2 (ja) * 1993-05-12 2003-02-24 セイコーインスツルメンツ株式会社 半導体集積回路装置
DE4334513C1 (de) * 1993-10-09 1994-10-20 Itt Ind Gmbh Deutsche CMOS-Schaltung mit erhöhter Spannungsfestigkeit
US5587665A (en) * 1995-07-18 1996-12-24 Vlsi Technology, Inc. Testing hot carrier induced degradation to fall and rise time of CMOS inverter circuits
US5541528A (en) * 1995-08-25 1996-07-30 Hal Computer Systems, Inc. CMOS buffer circuit having increased speed
US5874836A (en) * 1996-09-06 1999-02-23 International Business Machines Corporation High reliability I/O stacked fets
US20070063758A1 (en) * 2005-09-22 2007-03-22 Honeywell International Inc. Voltage divider and method for minimizing higher than rated voltages

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4100438A (en) * 1974-08-21 1978-07-11 Nippon Gakki Seizo Kabushiki Kaisha Compound transistor circuitry
US4521698A (en) * 1982-12-02 1985-06-04 Mostek Corporation Mos output driver circuit avoiding hot-electron effects
US4704547A (en) * 1984-12-10 1987-11-03 American Telephone And Telegraph Company, At&T Bell Laboratories IGFET gating circuit having reduced electric field degradation
EP0204762B1 (en) * 1984-12-10 1991-02-27 AT&T Corp. Integrated logic circuit
JPH0738583B2 (ja) * 1985-01-26 1995-04-26 株式会社東芝 半導体集積回路

Also Published As

Publication number Publication date
US4920287A (en) 1990-04-24
NL8702630A (nl) 1989-06-01
JPH01149448A (ja) 1989-06-12
EP0316033A1 (en) 1989-05-17

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