KR890001294A - Digital PLL State Detection Circuit - Google Patents

Digital PLL State Detection Circuit Download PDF

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Publication number
KR890001294A
KR890001294A KR1019870006583A KR870006583A KR890001294A KR 890001294 A KR890001294 A KR 890001294A KR 1019870006583 A KR1019870006583 A KR 1019870006583A KR 870006583 A KR870006583 A KR 870006583A KR 890001294 A KR890001294 A KR 890001294A
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KR
South Korea
Prior art keywords
output
digital pll
inputting
oscillation output
detection circuit
Prior art date
Application number
KR1019870006583A
Other languages
Korean (ko)
Other versions
KR890004120B1 (en
Inventor
함명식
Original Assignee
강진구
삼성반도체통신 주식회사
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Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR8706583A priority Critical patent/KR890004120B1/en
Publication of KR890001294A publication Critical patent/KR890001294A/en
Application granted granted Critical
Publication of KR890004120B1 publication Critical patent/KR890004120B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

내용 없음No content

Description

디지탈 PLL 상태 검출회로Digital PLL State Detection Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래 기술의 PLL 상태 검출회로.1 is a prior art PLL state detection circuit.

제2도는 본 발명에 따른 PLL 상태 검출회로.2 is a PLL state detection circuit according to the present invention.

제3도는 제2도의 각부 동작 타이밍도.3 is an operation timing diagram of each part of FIG.

Claims (1)

기준 입력신호와 비교신호를 입력하여 위상검출하는 위상검출기(11)와, 상기 위상검출기(11)의 각 출력을 입력하여 비교하는 로우패스필터(100)와, 상기 로우패스필터(100)의 출력을 입력하여 소정의 발진출력을 제공하는 전압제어발진기(13)와, 상기 전압제어발진기(13)의 발진출력을 소정 분주하는 분주회로(14)를구비한 디지탈 PLL 상태 검출회로에 있어서, 상기 전압제어발진기(13)의 발진출력을 상기 분주회로(14)를 통해 소정분주한 비교신호를 플립플롭(21)의 데이타 입력단(D)으로 입력함과 동시에 상기 기준입력 신호를 그의 클록입력단(CK)에 입력하고, 상기 D형 플립플롭(21)의 출력단(Q)으로 부터는 리트리거러블 원-샷 멀티바이브레이터(22)의 입력단(B)에 접속하여 그 출력단(Q)의 출력상태로써 PLL의 "고정"상태에 따른 논리"하이" 또는 "로우"신호를 출력하도록 구성함을 특징으로 하는 디지탈 PLL 상태 검출회로.A phase detector 11 for detecting phase by inputting a reference input signal and a comparison signal, a low pass filter 100 for inputting and comparing each output of the phase detector 11, and an output of the low pass filter 100 A digital PLL state detection circuit comprising a voltage controlled oscillator 13 for inputting a predetermined oscillation output to provide a predetermined oscillation output and a frequency divider circuit 14 for dividing an oscillation output of the voltage controlled oscillator 13 in a predetermined manner. A comparison signal obtained by dividing the oscillation output of the control oscillator 13 through the frequency division circuit 14 is input to the data input terminal D of the flip-flop 21, and the reference input signal is supplied to its clock input terminal CK. Input from the output terminal Q of the D flip-flop 21 to the input terminal B of the retriggerable one-shot multivibrator 22, and the " PLL " Outputs logic "high" or "low" signals according to the fixed "state" Digital PLL state detecting circuit, characterized in that the configured. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR8706583A 1987-06-27 1987-06-27 Detecting circuit of digital pll stade KR890004120B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR8706583A KR890004120B1 (en) 1987-06-27 1987-06-27 Detecting circuit of digital pll stade

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR8706583A KR890004120B1 (en) 1987-06-27 1987-06-27 Detecting circuit of digital pll stade

Publications (2)

Publication Number Publication Date
KR890001294A true KR890001294A (en) 1989-03-20
KR890004120B1 KR890004120B1 (en) 1989-10-20

Family

ID=19262410

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8706583A KR890004120B1 (en) 1987-06-27 1987-06-27 Detecting circuit of digital pll stade

Country Status (1)

Country Link
KR (1) KR890004120B1 (en)

Also Published As

Publication number Publication date
KR890004120B1 (en) 1989-10-20

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