KR870011531U - Contour correction control circuit - Google Patents

Contour correction control circuit

Info

Publication number
KR870011531U
KR870011531U KR2019850016364U KR850016364U KR870011531U KR 870011531 U KR870011531 U KR 870011531U KR 2019850016364 U KR2019850016364 U KR 2019850016364U KR 850016364 U KR850016364 U KR 850016364U KR 870011531 U KR870011531 U KR 870011531U
Authority
KR
South Korea
Prior art keywords
control circuit
correction control
contour correction
contour
circuit
Prior art date
Application number
KR2019850016364U
Other languages
Korean (ko)
Other versions
KR910003664Y1 (en
Inventor
지영배
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019850016364U priority Critical patent/KR910003664Y1/en
Publication of KR870011531U publication Critical patent/KR870011531U/en
Application granted granted Critical
Publication of KR910003664Y1 publication Critical patent/KR910003664Y1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/20—Circuitry for controlling amplitude response
    • H04N5/205—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic
    • H04N5/208—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic for compensating for attenuation of high frequency components, e.g. crispening, aperture distortion correction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/142—Edging; Contouring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/148—Video amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Picture Signal Circuits (AREA)
KR2019850016364U 1985-12-05 1985-12-05 Out line compensating control circuit KR910003664Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019850016364U KR910003664Y1 (en) 1985-12-05 1985-12-05 Out line compensating control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019850016364U KR910003664Y1 (en) 1985-12-05 1985-12-05 Out line compensating control circuit

Publications (2)

Publication Number Publication Date
KR870011531U true KR870011531U (en) 1987-07-18
KR910003664Y1 KR910003664Y1 (en) 1991-05-31

Family

ID=19247039

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019850016364U KR910003664Y1 (en) 1985-12-05 1985-12-05 Out line compensating control circuit

Country Status (1)

Country Link
KR (1) KR910003664Y1 (en)

Also Published As

Publication number Publication date
KR910003664Y1 (en) 1991-05-31

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Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19961231

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee