KR860009379A - Block Synchronization Signal Generation Circuit of Digital Audio Equipment - Google Patents

Block Synchronization Signal Generation Circuit of Digital Audio Equipment Download PDF

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Publication number
KR860009379A
KR860009379A KR1019850004180A KR850004180A KR860009379A KR 860009379 A KR860009379 A KR 860009379A KR 1019850004180 A KR1019850004180 A KR 1019850004180A KR 850004180 A KR850004180 A KR 850004180A KR 860009379 A KR860009379 A KR 860009379A
Authority
KR
South Korea
Prior art keywords
digital audio
generation circuit
signal generation
synchronization signal
audio equipment
Prior art date
Application number
KR1019850004180A
Other languages
Korean (ko)
Other versions
KR880001974B1 (en
Inventor
김용석
Original Assignee
정재은
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정재은, 삼성전자 주식회사 filed Critical 정재은
Priority to KR1019850004180A priority Critical patent/KR880001974B1/en
Publication of KR860009379A publication Critical patent/KR860009379A/en
Application granted granted Critical
Publication of KR880001974B1 publication Critical patent/KR880001974B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음No content

Description

디지탈 오디오기기의 블럭동기신호 발생회로Block Synchronization Signal Generation Circuit of Digital Audio Equipment

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 디지털 오디오기기의 복조시 인터페이스회로,1 is an interface circuit for demodulation of a digital audio device;

제2도는 메모리 버퍼의 회로도,2 is a circuit diagram of a memory buffer,

제3도는 본 발명의 회로도.3 is a circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

I1: 인버터 FF1, FF2: 플립플롭I 1 : Inverter FF 1 , FF 2 : Flip-flop

A1: 앤드게이트 1 : 펄스검출부A 1 : AND gate 1: pulse detection unit

2, 5 : 레지스터 3 : 메모리버퍼2, 5: Register 3: Memory Buffer

4 : 버퍼 BP1: 복조회로4: Buffer BP 1 : Demodulation Circuit

12 : 램 1 13 : 램 212: RAM 1 13: RAM 2

15, 17, 18 : 멀리플렉서 14 : 14진 카운터15, 17, 18: far multiplexer 14: 14-degree counter

16 : 16진 카운터16: hexadecimal counter

Claims (1)

디스에이블 신호(a)가 인버터(I1)를 통하여 플립플롭(FF1)의 입력단자(D)에 인가되게 구성시키고 그 출력이 앤드게이트(A1)의 일측 및 플립플롭(FF2)의 입력단자(D)에 인가되게 구성시킨후 플립플롭(FF2)의 출력단자(Q)가 앤드 게이트(A1)의 타측에 인가되게 구성한 디지털 오디오기기의 블럭 동기신호 발생회로.The disable signal a is configured to be applied to the input terminal D of the flip-flop FF 1 through the inverter I 1 , and its output is connected to one side of the AND gate A 1 and the flip-flop FF 2 . A block synchronizing signal generation circuit of a digital audio device, configured to be applied to an input terminal (D), and configured such that an output terminal (Q) of the flip-flop (FF 2 ) is applied to the other side of the AND gate (A 1 ). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850004180A 1985-06-11 1985-06-11 Synchronizing signal generating circuit KR880001974B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850004180A KR880001974B1 (en) 1985-06-11 1985-06-11 Synchronizing signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850004180A KR880001974B1 (en) 1985-06-11 1985-06-11 Synchronizing signal generating circuit

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
KR2019850005966 Division 1985-05-20
KR2019850005967 Division 1985-05-20

Publications (2)

Publication Number Publication Date
KR860009379A true KR860009379A (en) 1986-12-22
KR880001974B1 KR880001974B1 (en) 1988-10-08

Family

ID=19241373

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850004180A KR880001974B1 (en) 1985-06-11 1985-06-11 Synchronizing signal generating circuit

Country Status (1)

Country Link
KR (1) KR880001974B1 (en)

Also Published As

Publication number Publication date
KR880001974B1 (en) 1988-10-08

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