KR860009379A - Block Synchronization Signal Generation Circuit of Digital Audio Equipment - Google Patents
Block Synchronization Signal Generation Circuit of Digital Audio Equipment Download PDFInfo
- Publication number
- KR860009379A KR860009379A KR1019850004180A KR850004180A KR860009379A KR 860009379 A KR860009379 A KR 860009379A KR 1019850004180 A KR1019850004180 A KR 1019850004180A KR 850004180 A KR850004180 A KR 850004180A KR 860009379 A KR860009379 A KR 860009379A
- Authority
- KR
- South Korea
- Prior art keywords
- digital audio
- generation circuit
- signal generation
- synchronization signal
- audio equipment
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 디지털 오디오기기의 복조시 인터페이스회로,1 is an interface circuit for demodulation of a digital audio device;
제2도는 메모리 버퍼의 회로도,2 is a circuit diagram of a memory buffer,
제3도는 본 발명의 회로도.3 is a circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
I1: 인버터 FF1, FF2: 플립플롭I 1 : Inverter FF 1 , FF 2 : Flip-flop
A1: 앤드게이트 1 : 펄스검출부A 1 : AND gate 1: pulse detection unit
2, 5 : 레지스터 3 : 메모리버퍼2, 5: Register 3: Memory Buffer
4 : 버퍼 BP1: 복조회로4: Buffer BP 1 : Demodulation Circuit
12 : 램 1 13 : 램 212: RAM 1 13: RAM 2
15, 17, 18 : 멀리플렉서 14 : 14진 카운터15, 17, 18: far multiplexer 14: 14-degree counter
16 : 16진 카운터16: hexadecimal counter
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019850004180A KR880001974B1 (en) | 1985-06-11 | 1985-06-11 | Synchronizing signal generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019850004180A KR880001974B1 (en) | 1985-06-11 | 1985-06-11 | Synchronizing signal generating circuit |
Related Parent Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019850005966 Division | 1985-05-20 | ||
KR2019850005967 Division | 1985-05-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR860009379A true KR860009379A (en) | 1986-12-22 |
KR880001974B1 KR880001974B1 (en) | 1988-10-08 |
Family
ID=19241373
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019850004180A KR880001974B1 (en) | 1985-06-11 | 1985-06-11 | Synchronizing signal generating circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR880001974B1 (en) |
-
1985
- 1985-06-11 KR KR1019850004180A patent/KR880001974B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR880001974B1 (en) | 1988-10-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19970829 Year of fee payment: 12 |
|
LAPS | Lapse due to unpaid annual fee |