KR850008764A - Noise attenuation circuit - Google Patents

Noise attenuation circuit Download PDF

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Publication number
KR850008764A
KR850008764A KR1019840002617A KR840002617A KR850008764A KR 850008764 A KR850008764 A KR 850008764A KR 1019840002617 A KR1019840002617 A KR 1019840002617A KR 840002617 A KR840002617 A KR 840002617A KR 850008764 A KR850008764 A KR 850008764A
Authority
KR
South Korea
Prior art keywords
noise attenuation
attenuation circuit
adder
output
pass filter
Prior art date
Application number
KR1019840002617A
Other languages
Korean (ko)
Inventor
겡죠우 아까기리
Original Assignee
이와마 가즈오
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이와마 가즈오, 소니 가부시끼 가이샤 filed Critical 이와마 가즈오
Priority to KR1019840002617A priority Critical patent/KR850008764A/en
Publication of KR850008764A publication Critical patent/KR850008764A/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G7/00—Volume compression or expansion in amplifiers

Landscapes

  • Noise Elimination (AREA)

Abstract

내용 없음No content

Description

잡음 감쇠회로Noise attenuation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 각기 다른 종래의 잡음 감쇠회로의 입출력특성을 보인 그래프.2 is a graph showing the input and output characteristics of different conventional noise reduction circuits.

제3도는 본 발명의 기본적 구성을 나타낸 블럭회로도.3 is a block circuit diagram showing the basic configuration of the present invention.

제4도는 본 발명의 실시예를 도시하는 블럭 회로도.4 is a block circuit diagram showing an embodiment of the present invention.

Claims (1)

입력신호가 입력되는 가산기와, 이 가산기로 부터의 출력을 제어신호에 응하는 이득으로 증폭하는 이득제어형 증폭기와, 이 이득제어형 증폭기로부터의 출력을 고역감쇠시키는 제1의 로우패스필터와, 이 제1의 오루 패스필터의 출력의 일부를 통과시켜서 상기 가산기에 감산신호로서 공급하는 제2의 로우패스 필터를 가지고, 상기 입력신호의 일부를 상기 제어신호로서 상기 이득제어용 증폭기에 보내도록 구성시킨 것을 특징으로 하는 잡음 감쇠회로.An adder to which the input signal is input, a gain control amplifier for amplifying the output from the adder with a gain corresponding to the control signal, a first low pass filter for high-pass attenuating the output from the gain control amplifier, and And a second low pass filter which passes a part of the output of the first through pass filter of 1 and supplies it to the adder as a subtracted signal, and is configured to send a part of the input signal as the control signal to the gain control amplifier. Noise attenuation circuit. ※참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: This is to be disclosed based on the first application.
KR1019840002617A 1984-05-14 1984-05-14 Noise attenuation circuit KR850008764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019840002617A KR850008764A (en) 1984-05-14 1984-05-14 Noise attenuation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019840002617A KR850008764A (en) 1984-05-14 1984-05-14 Noise attenuation circuit

Publications (1)

Publication Number Publication Date
KR850008764A true KR850008764A (en) 1985-12-21

Family

ID=55316202

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840002617A KR850008764A (en) 1984-05-14 1984-05-14 Noise attenuation circuit

Country Status (1)

Country Link
KR (1) KR850008764A (en)

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