KR20210098659A - 댐 구조물을 갖는 반도체 패키지 - Google Patents
댐 구조물을 갖는 반도체 패키지 Download PDFInfo
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- KR20210098659A KR20210098659A KR1020200012460A KR20200012460A KR20210098659A KR 20210098659 A KR20210098659 A KR 20210098659A KR 1020200012460 A KR1020200012460 A KR 1020200012460A KR 20200012460 A KR20200012460 A KR 20200012460A KR 20210098659 A KR20210098659 A KR 20210098659A
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- semiconductor chip
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- lower semiconductor
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Abstract
반도체 패키지는 상면에 본딩 패드들을 갖는 기판, 하부 반도체 칩 및 상기 하부 반도체 칩 상의 적어도 하나의 상부 반도체 칩, 상기 하부 반도체 칩을 둘러싸는 닫힌 루프 형상을 갖는 댐 구조물을 포함한다. 상기 댐 구조물은 상기 하부 반도체 칩과 상기 본딩 패드들 사이의 협폭 댐 및 상기 협폭 댐보다 큰 내부 폭을 갖는 광폭 댐을 포함한다. 반도체 패키지는 상기 댐 구조물의 내측에 배치되며 상기 기판과 상기 하부 반도체 칩 사이를 채우는 언더필을 포함한다.
Description
본 개시의 기술적 사상은 댐 구조물을 갖는 반도체 패키지에 관한 것이다.
반도체 소자의 소형화 추세에 따라, 하나의 반도체 패키지 내부에 각각의 기능을 갖는 반도체 칩들을 실장하는 기술이 요구된다. 반도체 패키지는 기판과 하부 반도체 칩 사이를 채우는 언더필, 및 본딩 패드가 언더필에 덮이지 않도록 하는 댐 구조물을 포함한다. 반도체 패키지의 크기가 작아짐에 따라, 언더필의 디스펜싱 면적이 좁아지는 문제가 있다.
본 개시의 기술적 사상의 실시예들에 따른 과제는 협폭 댐 및 광폭 댐을 갖는 댐 구조물을 포함하는 반도체 패키지를 제공하는데 있다.
본 개시의 실시예들에 따른 반도체 패키지는 상면에 본딩 패드들을 갖는 기판; 상기 기판 상에 배치되는 하부 반도체 칩 및 상기 하부 반도체 칩 상의 적어도 하나의 상부 반도체 칩; 상기 기판 상에 배치되며 상기 하부 반도체 칩을 둘러싸는 닫힌 루프 형상을 갖는 댐 구조물, 상기 댐 구조물은 상기 하부 반도체 칩과 상기 본딩 패드들 사이의 협폭 댐 및 상기 협폭 댐보다 큰 내부 폭을 갖는 광폭 댐을 포함하며, 및 상기 댐 구조물의 내측에 배치되며 상기 기판과 상기 하부 반도체 칩 사이를 채우는 언더필을 포함할 수 있다.
본 개시의 실시예들에 따른 반도체 패키지는 상면에 본딩 패드들을 갖는 기판; 상기 기판 상에 배치되는 하부 반도체 칩 및 상기 하부 반도체 칩 상의 적어도 하나의 상부 반도체 칩; 상기 기판과 상기 하부 반도체 칩 사이를 채우는 언더필을 포함하되, 상기 언더필은 상기 하부 반도체 칩과 상기 본딩 패드들 사이의 비확장 영역 및 상기 비확장 영역보다 내부 폭이 큰 확장 영역을 포함하며, 및; 상기 기판 상에 배치되고 상기 언더필을 둘러싸며 닫힌 루프 형상을 갖는 댐 구조물을 포함할 수 있다.
본 개시의 실시예들에 따른 반도체 패키지는 상면에 본딩 패드들을 갖는 기판; 상기 기판 상에 플립칩 방식으로 실장된 하부 반도체 칩 및 상기 하부 반도체 칩 상에 와이어 본딩 방식으로 실장된 상부 반도체 칩; 상기 기판 상에 배치되며 상기 하부 반도체 칩을 둘러싸는 닫힌 루프 형상을 갖는 댐 구조물, 상기 댐 구조물은 상기 하부 반도체 칩과 상기 본딩 패드들 사이의 협폭 댐 및 상기 협폭 댐보다 내부 폭이 확장된 광폭 댐을 가지며, 상기 댐 구조물의 내측에 배치되며 상기 기판과 상기 하부 반도체 칩 사이를 채우는 언더필; 및 상기 기판, 상기 하부 반도체 칩 및 상기 상부 반도체 칩을 덮는 봉지재를 포함할 수 있다.
본 개시의 실시예들에 따르면 댐 구조물을 협폭 댐 및 광폭 댐을 포함하여, 언더필의 디스펜싱 면적을 넓게 확보할 수 있다.
도 1은 본 개시의 일 실시예에 따른 반도체 패키지의 평면도이다.
도 2a 내지 도 2c는 도 1에 도시된 반도체 패키지의 선 I-I', 선 II-II' 및 선 III-III'을 따른 수직 단면도들이다.
도 3은 본 개시의 다른 실시예에 따른 반도체 패키지의 평면도이다.
도 4는 본 개시의 다른 실시예에 따른 반도체 패키지의 평면도이다.
도 5는 도 4에 도시된 반도체 패키지의 선 IV-IV'을 따른 수직 단면도이다.
도 6은 본 개시의 다른 실시예에 따른 반도체 패키지의 평면도이다.
도 7 내지 도 12는 본 개시의 일 실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위해 공정 순서에 따라 도시된 평면도들 및 수직 단면도들이다.
도 2a 내지 도 2c는 도 1에 도시된 반도체 패키지의 선 I-I', 선 II-II' 및 선 III-III'을 따른 수직 단면도들이다.
도 3은 본 개시의 다른 실시예에 따른 반도체 패키지의 평면도이다.
도 4는 본 개시의 다른 실시예에 따른 반도체 패키지의 평면도이다.
도 5는 도 4에 도시된 반도체 패키지의 선 IV-IV'을 따른 수직 단면도이다.
도 6은 본 개시의 다른 실시예에 따른 반도체 패키지의 평면도이다.
도 7 내지 도 12는 본 개시의 일 실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위해 공정 순서에 따라 도시된 평면도들 및 수직 단면도들이다.
도 1은 본 개시의 일 실시예에 따른 반도체 패키지의 평면도이다.
도 2a 내지 도 2c는 도 1에 도시된 반도체 패키지의 선 I-I', 선 II-II' 및 선 III-III'을 따른 수직 단면도들이다.
도 1, 도 2a 내지 도 2c를 참조하면, 반도체 패키지(100)는 기판(102), 댐 구조물(D), 하부 반도체 칩(110), 언더필(120), 상부 반도체 칩(130), 봉지재(140) 및 외부 연결 단자(150)를 포함할 수 있다.
기판(102)은 상면에 상부 패드들(104) 포함할 수 있으며, 하면에 하부 패드들(106)을 포함할 수 있다. 상부 패드들(104)은 각각 대응하는 하부 패드들(106)과 전기적으로 연결될 수 있다. 또한, 기판(102)은 상면에 본딩 패드들(108)을 포함할 수 있다. 본딩 패드들(108)은 대응하는 하부 패드들(106)과 전기적으로 연결될 수 있다. 본딩 패드들(108)은 기판(102)의 3면에 배치될 수 있다. 예를 들어, 본딩 패드들(108)은 평면도에서 기판(102)의 제1 수평 방향(x)의 일측면의 가장자리 및 제2 수평 방향(y)의 양측 가장자리에 배치될 수 있다. 그러나, 이에 제한되지 않는다. 본딩 패드들(108)은 직사각 형상을 갖는 것이 도시되어 있으나, 다른 실시예에서, 원, 타원 등의 형상을 가질 수 있다.
하부 반도체 칩(110)은 기판(102) 상에 배치될 수 있다. 하부 반도체 칩(110)은 직사각 형상을 가지며 제1 측면(111), 제2 측면(112), 제3 측면(113) 및 제4 측면(114)을 포함할 수 있다. 하부 반도체 칩(110)은 하면에 범프들(116)을 포함할 수 있다. 범프들(116)은 상부 패드들(104)을 통해 기판(102)과 전기적으로 연결될 수 있다.
댐 구조물(D)은 기판(102)의 상면에 배치될 수 있으며, 하부 반도체 칩(110)을 둘러쌀 수 있다. 댐 구조물(D)은 협폭 댐(Da), 광폭 댐(Db), 제1 연결부(Dc1) 및 제2 연결부(Dc2)를 포함할 수 있다. 협폭 댐(Da)은 본딩 패드(108)와 하부 반도체 칩(110) 사이에 배치될 수 있으며, 상대적으로 작은 내부 폭을 가질 수 있다. 광폭 댐(Db)은 협폭 댐(Da)에 연결되며, 상대적으로 큰 내부 폭을 가질 수 있다. 일 실시예에서, 하부 반도체 칩(110)과 광폭 댐(Db) 사이의 거리는 하부 반도체 칩(110)과 협폭 댐(Da) 사이의 거리보다 클 수 있다. 예를 들어, 하부 반도체 칩(110)과 협폭 댐(Da) 사이의 거리(W1)는 200㎛ ~ 400㎛일 수 있으며, 하부 반도체 칩(110)과 광폭 댐(Db) 사이의 거리(W2)는 500㎛ ~ 1000㎛일 수 있다. 협폭 댐(Da)과 본딩 패드들(108) 사이의 제2 수평 방향(y) 거리(W3)는 50㎛ ~ 150㎛일 수 있다. 광폭 댐(Db)과 기판(102)의 측면 사이의 거리(W4)는 100㎛ ~ 300㎛일 수 있다. 제1 연결부(Dc1) 및 제2 연결부(Dc2)와 본딩 패드들(108) 사이의 제1 수평 방향(x) 거리(W5)는 50㎛ ~ 150㎛일 수 있다.
댐 구조물(D)은 본딩 패드들(108)과 언더필(120)을 공간적으로 분리시킬 수 있다. 예를 들어, 댐 구조물(D)의 협폭 댐(Da)은 본딩 패드들(108)과 언더필(120) 사이에서 하부 반도체 칩(110)의 제1 내지 제3 측면들(111, 112, 113)을 따라 연장될 수 있다.
일 실시예에서, 협폭 댐(Da) 및 광폭 댐(Db)은 ㄷ자 형상 또는 각진 C자 형상(angular C-shape)일 수 있다. 예를 들어, 협폭 댐(Da)은 하부 반도체 칩(110)의 제1 내지 제3 측면들(111, 112, 113)을 둘러싸고, 광폭 댐(Db)은 제1, 제3 및 제4 측면들(111, 113, 114)을 둘러쌀 수 있다. 평면도에서, 협폭 댐(Da) 및 광폭 댐(Db)은 각각 하부 반도체 칩(110)의 제1 측면(111)과 인접한 제1 단부(Da1) 및 제1 단부(Db1)를 포함할 수 있으며, 제3 측면(113)과 인접한 제2 단부(Da2) 및 제2 단부(Db2)를 포함할 수 있다. 제1 연결부(Dc1)는 제1 단부(Da1) 및 제1 단부(Db1)를 연결할 수 있으며, 제2 연결부(Dc2)는 제2 단부(Da2)와 제2 단부(Db2)를 연결할 수 있다. 다른 실시예에서, 협폭 댐(Da) 및 광폭 댐(Db)은 둥근 C자 형상 또는 원호 형상을 가질 수 있다. 제1 연결부(Dc1) 및 제2 연결부(Dc2)와 본딩 패드들(108) 사이의 제1 수평 방향(x) 거리는 50㎛ ~ 150㎛일 수 있다. 본딩 패드들(108)은 하부 반도체 칩(110)의 제1 내지 제3 측면들(111, 112, 113)과 대향하도록 배치될 수 있다.
언더필(120)은 기판(102)과 하부 반도체 칩(110) 사이를 채울 수 있다. 언더필(120)은 에폭시 수지를 포함할 수 있으며, 범프들(116)을 보호할 수 있다. 언더필(120)은 기판(102)의 상면을 부분적으로 덮을 수 있으며, 본딩 패드(108)를 덮지 않을 수 있다. 언더필(120)은 댐 구조물(D)의 내측에 배치될 수 있으며, 댐 구조물(D)의 내측면에 접할 수 있다.
평면도에서, 언더필(120)은 협폭 댐(Da)의 내측을 채우는 비확장 영역(120a) 및 광폭 댐(Db)의 내측을 채우는 확장 영역(120b)을 포함할 수 있다. 비확장 영역(120a)은 본딩 패드(108)와 하부 반도체 칩(110) 사이에 배치될 수 있다. 확장 영역(120b)은 비확장 영역(120a)과 연결될 수 있으며, 확장 영역(120b)은 비확장 영역(120a)보다 큰 내부 폭을 가질 수 있다. 예를 들어, 하부 반도체 칩(110)과 확장 영역(120b)의 측면 사이의 거리는 하부 반도체 칩(110)과 비확장 영역(120a)의 측면 사이의 거리보다 클 수 있다. 비확장 영역(120a) 및 확장 영역(120b)은 직사각 형상을 갖는 것이 도시되어 있으나, 이에 제한되지 않으며 원 또는 타원 형상을 가질 수 있다.
기판(102)과 하부 반도체 칩(110) 사이에 채워지는 언더필(120)의 양은 범프들(116)의 높이에 따라 결정될 수 있다. 그러나, 반도체 패키지(100)의 사이즈가 작아지면 언더필(120)의 디스펜싱 면적이 충분하지 않을 수 있다. 본 발명의 일 실시예에 따른 반도체 패키지(100)는 협폭 댐(Da) 및 광폭 댐(Db)을 갖는 댐 구조물(D)을 포함하므로, 주어진 반도체 패키지(100) 사이즈에 대해 언더필(120)의 디스펜싱 면적을 상대적으로 넓게 확보할 수 있다.
상부 반도체 칩(130)은 하부 반도체 칩(110) 상에 배치될 수 있다. 일 실시예에서, 상부 반도체 칩(130)은 기판(102)에 와이어 본딩 방식으로 실장될 수 있다. 예를 들어, 상부 반도체 칩(130)은 상면에 칩 패드들(132)을 포함할 수 있으며, 기판(102)의 본딩 패드들(108)과 상부 반도체 칩(130)의 칩 패드들(132)은 본딩 와이어(134)를 통해 전기적으로 연결될 수 있다. 상부 반도체 칩(130)은 접착제(136)에 의해 하부 반도체 칩(110) 상에 고정될 수 있다.
하부 반도체 칩(110)은 마이크로 프로세서, 마이크로 컨트롤러 등의 어플리케이션 프로세서(application processor; AP) 칩, CPU, GPU, 모뎀, ASIC(application-specific IC) 및 FPGA(Field Programmable Gate Array) 등의 로직 칩을 포함할 수 있다. 상부 반도체 칩(130)은 DRAM과 같은 휘발성 메모리 칩 또는 플래시 메모리 같은 비휘발성 메모리 칩을 포함할 수 있다. 일 실시예에서, 하부 반도체 칩(110)은 모뎀 칩을 포함할 수 있고, 상부 반도체 칩(130)은 DRAM 칩을 포함할 수 있다.
봉지재(140)는 기판(102), 하부 반도체 칩(110), 상부 반도체 칩(130) 및 댐 구조물(D)을 덮을 수 있다. 일 실시예에서, 봉지재(140)는 에폭시 몰딩 컴파운드(EMC)를 포함할 수 있다.
외부 연결 단자(150)는 기판(102)의 하면에 형성될 수 있다. 외부 연결 단자(150)는 기판(102)의 하부 패드(106)와 연결될 수 있으며, 하부 패드(106)를 통해 상부 패드(104)와 전기적으로 연결될 수 있다.
도 3은 본 개시의 다른 실시예에 따른 반도체 패키지의 평면도이다.
도 3을 참조하면, 반도체 패키지(200)는 기판(102)상에 배치되며 하부 반도체 칩(110)을 둘러싸는 댐 구조물(D)을 포함할 수 있다. 반도체 패키지(200)는 기판(102) 상에 얼라인 마크(208)를 포함할 수 있다. 얼라인 마크(208)는 상부 반도체 칩(130)의 형성 시 상부 반도체 칩(130)을 기판(102)상에 정렬하고 본딩 패드들(108)과 연결하기 위한 기준이 될 수 있다. 얼라인 마크(208)는 기판(102)의 가장자리에 배치될 수 있으며, 예를 들어 두 개의 얼라인 마크(208)가 기판(102)의 대각선 방향의 양 모서리에 배치될 수 있다.
댐 구조물(D)은 얼라인 마크(208)와 중첩되지 않을 수 있다. 예를 들어, 댐 구조물(D)은 얼라인 마크(208)에 대응하여 수직으로 구부러진 컷-아웃(C)을 포함할 수 있다. 컷-아웃(C)은 얼라인 마크(208)로부터 이격되어 배치될 수 있으며, 얼라인 마크(208)는 댐 구조물(D)의 외측에 위치할 수 있다.
도 4는 본 개시의 다른 실시예에 따른 반도체 패키지의 평면도이다.
도 5는 도 4에 도시된 반도체 패키지의 선 IV-IV'을 따른 수직 단면도이다.
도 4 및 도 5를 참조하면, 반도체 패키지(300)는 하부 반도체 칩(110)을 둘러싸는 댐 구조물(D) 및 댐 구조물(D) 내부의 언더필(320)을 포함할 수 있다. 하부 반도체 칩(110) 상에 제1 상부 반도체 칩(330a) 및 제2 상부 반도체 칩(330b)이 배치될 수 있다. 제1 상부 반도체 칩(330a)과 제2 상부 반도체 칩(330b)은 제1 수평 방향(x)을 따라 서로 이격되어 배치될 수 있다. 일 실시예에서, 제1 상부 반도체 칩(330a) 및 제2 상부 반도체 칩(330b)은 기판(102)에 와이어 본딩 방식으로 실장될 수 있다. 제1 상부 반도체 칩(330a)은 상면에 제1 칩 패드들(332a)을 포함할 수 있으며, 제2 상부 반도체 칩(330b)은 상면에 제2 칩 패드들(332b)을 포함할 수 있다. 제1 칩 패드들(332a)은 ㄷ자 형상으로 배치될 수 있다. 예를 들어, 제1 칩 패드들(332a)은 제1 상부 반도체 칩(330a)의 우측을 제외한 상측, 하측 및 좌측에 배치될 수 있다. 제2 칩 패드들(332b)은 ㄷ자 형상으로 배치될 수 있다. 예를 들어, 제2 칩 패드들(332b)은 제2 상부 반도체 칩(330b)의 좌측을 제외한 상측, 하측 및 우측에 배치될 수 있다. 본딩 패드들(108)은 제1 칩 패드들(332a) 및 제2 칩 패드들(332b)에 대응하여 하부 반도체 칩(110)을 둘러싸도록 배치될 수 있다.
댐 구조물(D)은 협폭 댐(Da) 및 광폭 댐(Db)을 포함할 수 있다. 예를 들어, 댐 구조물(D)은 제1 수평 방향(x)으로 이격된 두 개의 협폭 댐들(Da) 및 협폭 댐들(Da) 사이에 배치되며 제2 수평 방향(y)으로 확장된 광폭 댐(Db)을 포함할 수 있다. 협폭 댐들(Da)은 본딩 패드들(108)과 하부 반도체 칩(110) 사이에서 연장될 수 있다. 댐 구조물(D) 하부 반도체 칩(110)을 둘러쌀 수 있으며, 닫힌 루프 형상을 가질 수 있다.
언더필(320)은 댐 구조물(D)의 내측에 배치될 수 있으며, 댐 구조물(D)의 내측면에 접할 수 있다. 평면도에서, 언더필(320)은 협폭 댐(Da)의 내측을 채우는 비확장 영역(320a) 및 광폭 댐(Db)의 내측을 채우는 확장 영역(320b)을 포함할 수 있다. 확장 영역(320b)은 비확장 영역(320a)보다 큰 내부 폭을 가질 수 있다. 예를 들어, 확장 영역(320b)의 제2 수평 방향(y)의 폭은 비확장 영역(320a)의 제2 수평 방향(y)의 내부 폭 보다 클 수 있다.
도 6은 본 개시의 다른 실시예에 따른 반도체 패키지의 평면도이다.
도 6을 참조하면, 반도체 패키지(400)는 하부 반도체 칩(110)을 둘러싸는 댐 구조물(D) 및 댐 구조물(D) 내부의 언더필(420)을 포함할 수 있다. 상부 반도체 칩(130)은 상면에 칩 패드들(432)을 포함할 수 있으며, 칩 패드들(432)은 상부 반도체 칩(130)의 좌측 및 우측 가장자리에 배치될 수 있다. 본딩 패드들(108)은 칩 패드들(432)에 대응하여 기판(102)의 좌측 및 우측 가장자리에 배치될 수 있다.
댐 구조물(D)은 협폭 댐(Da) 및 광폭 댐(Db)을 포함할 수 있다. 예를 들어, 평면도에서 댐 구조물(D)은 협폭 댐(Da) 및 협폭 댐(Da) 아래에 광폭 댐(Db)을 포함할 수 있다. 협폭 댐(Da)은 본딩 패드들(108)과 하부 반도체 칩(110) 사이에서 연장될 수 있다. 댐 구조물(D) 하부 반도체 칩(110)을 둘러쌀 수 있으며, 닫힌 루프 형상을 가질 수 있다.
평면도에서, 언더필(420)은 협폭 댐(Da)의 내측을 채우는 비확장 영역(420a) 및 광폭 댐(Db)의 내측을 채우는 확장 영역(420b)을 포함할 수 있다.
도 7 내지 도 12는 본 개시의 일 실시예에 따른 반도체 패키지(100)의 제조 방법을 설명하기 위해 공정 순서에 따라 도시된 평면도들 및 수직 단면도들이다. 도 7, 도 9 및 도 11은 따른 반도체 패키지(100)의 제조 방법을 설명하기 위한 평면도들이며, 도 8, 도 10 및 도 12는 각각 도 7, 도 9 및 도 11의 선 I-I'를 따른 수직 단면도들이다.
도 7 및 도 8을 참조하면, 기판(102)이 제공될 수 있다. 기판(102)은 상면에 상부 패드들(104)을 포함할 수 있으며, 하면에 하부 패드들(106)을 포함할 수 있다. 상부 패드들(104)은 각각 대응하는 하부 패드들(106)과 전기적으로 연결될 수 있다. 또한, 기판(102)은 상면에 본딩 패드들(108)을 포함할 수 있다. 상부 패드들(104), 하부 패드들(106) 및 본딩 패드들(108)은 Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au 및 Ag와 같은 금속을 포함할 수 있다.
도 9 및 도 10을 참조하면, 기판(102)의 상면에 댐 구조물(D)이 형성될 수 있다. 댐 구조물(D)은 포토레지스트 수지 또는 Al, Cu 등의 금속을 포함할 수 있다. 일 실시예에서, 댐 구조물(D)은 포토 레지스트 수지를 포함할 수 있다. 포토 레지스트는 예를 들어, 에폭시 수지, 아크릴계 단량체(acrylic monomer), 포스핀 옥사이드 화합물(phosphine oxide compound), 아민 화합물(amine compound), 실리카, 황산 바륨 등을 포함할 수 있다.
댐 구조물(D)은 기판(102)의 상면에 포토 레지스트 수지를 형성하고, 상기 포토레지스트 수지를 식각하여 형성될 수 있다. 일 실시예에서, 댐 구조물(D)의 높이는 18㎛ 이하 일 수 있다. 댐 구조물(D)은 상부 패드들(104)을 둘러싸도록 배치될 수 있으며, 닫힌 루프 형상을 가질 수 있다. 상부 패드들(104)은 댐 구조물(D)의 내측에 위치할 수 있으며, 본딩 패드들(108)은 댐 구조물(D)의 외측에 위치할 수 있다. 댐 구조물(D)은 협폭 댐(Da), 광폭 댐(Db) 및 협폭 댐(Da)과 광폭 댐(Db)을 연결하는 제1 연결부(Dc1) 및 제2 연결부(Dc2)를 포함할 수 있다. 예를 들어, 협폭 댐(Da) 및 광폭 댐(Db)은 ㄷ자 형상 또는 각진 C자 형상(angular C-shape)일 수 있다. 협폭 댐(Da)의 제1 단부(Da1)는 광폭 댐(Db)의 제1 단부(Db1)와 제1 연결부(Dc1)에 의해 연결될 수 있으며, 협폭 댐(Da)의 제2 단부(Da2)는 광폭 댐(Db)의 제2 단부(Db2)와 제2 연결부(Dc2)에 의해 연결될 수 있다. 일 실시예에서, 기판(102)의 측면과 협폭 댐(Da) 사이의 거리는 기판(102)의 측면과 광폭 댐(Db) 사이의 거리보다 클 수 있다.
도 11 및 도 12를 참조하면, 기판(102) 상에 하부 반도체 칩(110)이 실장될 수 있으며, 언더필(120)이 형성될 수 있다. 하부 반도체 칩(110)은 기판(102) 상에 플립칩 본딩 방식으로 실장될 수 있다. 하부 반도체 칩(110)은 직사각 형상을 가지며 제1 측면(111), 제2 측면(112), 제3 측면(113) 및 제4 측면(114)을 포함할 수 있다. 하부 반도체 칩(110)은 하면에 상부 패드들(104)과 연결되는 범프들(116)을 포함할 수 있다.
하부 반도체 칩(110)이 실장된 후, 기판(102)과 하부 반도체 칩(110) 사이를 채우는 언더필(120)이 형성될 수 있다. 일 실시예에서, 언더필(120)은 에폭시 수지를 포함할 수 있다. 언더필(120)은 댐 구조물(D)의 내측에 형성될 수 있으며, 본딩 패드들(108)을 덮지 않을 수 있다. 언더필(120)은 디스펜싱 방법을 이용하여 형성될 수 있다. 예를 들어, 언더필(120)은 디스펜서(122)로부터 하부 반도체 칩(110)의 제4 측면(114)과 댐 구조물(D) 사이에 공급될 수 있으며, 제4 측면(114)으로부터 제1 측면(111) 방향으로 기판(102)과 하부 반도체 칩(110) 사이에 채워질 수 있다.
다시 도 1, 도 2a 내지 도 2c를 참조하면, 상부 반도체 칩(130)은 하부 반도체 칩(110) 상에 배치될 수 있다. 상부 반도체 칩(130)은 기판(102)에 와이어 본딩 방식으로 실장될 수 있다. 예를 들어, 상부 반도체 칩(130)의 칩 패드(132)는 본딩 와이어(134)를 통해 본딩 패드들(108)과 연결될 수 있다. 상부 반도체 칩(130)은 접착제(136)에 의해 하부 반도체 칩(110) 상에 고정될 수 있다. 접착제(136)는 DAF(die attach film) 또는 에폭시 수지를 포함할 수 있다.
기판(102), 하부 반도체 칩(110), 상부 반도체 칩(130) 및 댐 구조물(D)을 덮도록 봉지재(140)가 형성될 수 있다. 봉지재(140)는 에폭시 또는 폴리이미드 등을 포함하는 수지일 수 있다. 예를 들면, 봉지재(140)는 비스페놀계 에폭시 수지(Bisphenol-group Epoxy Resin), 다방향족 에폭시 수지(Polycyclic Aromatic Epoxy Resin), 올소크레졸 노블락계 에폭시 수지(o-Cresol Novolac Epoxy Resin), 바이페닐계 에폭시 수지(Biphenyl-group Epoxy Resin) 또는 나프탈렌계 에폭시 수지(Naphthalene-group Epoxy Resin) 등을 포함할 수 있다.
이상, 첨부된 도면을 참조하여 본 개시에 따른 실시예들을 설명하였지만, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자는 본 발명이 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 이상에서 기술한 실시예는 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해하여야 한다.
100 : 반도체 패키지
102 : 기판
104 : 상부 패드 106 : 하부 패드
110 : 하부 반도체 칩 116 : 범프
120 : 언더필 120a : 비확장 영역
120b : 확장 영역 130 : 상부 반도체 칩
140 : 봉지재 150 : 외부 연결 단자 D : 댐 구조물 Da : 협폭 댐
Db : 광폭 댐 Dc1 : 제1 연결부
Dc2 : 제2 연결부 208 : 얼라인 마크
C : 컷-아웃
104 : 상부 패드 106 : 하부 패드
110 : 하부 반도체 칩 116 : 범프
120 : 언더필 120a : 비확장 영역
120b : 확장 영역 130 : 상부 반도체 칩
140 : 봉지재 150 : 외부 연결 단자 D : 댐 구조물 Da : 협폭 댐
Db : 광폭 댐 Dc1 : 제1 연결부
Dc2 : 제2 연결부 208 : 얼라인 마크
C : 컷-아웃
Claims (10)
- 상면에 본딩 패드들을 갖는 기판;
상기 기판 상에 배치되는 하부 반도체 칩 및 상기 하부 반도체 칩 상의 적어도 하나의 상부 반도체 칩;
상기 기판 상에 배치되며 상기 하부 반도체 칩을 둘러싸는 닫힌 루프 형상을 갖는 댐 구조물, 상기 댐 구조물은 상기 하부 반도체 칩과 상기 본딩 패드들 사이의 협폭 댐 및 상기 협폭 댐보다 큰 내부 폭을 갖는 광폭 댐을 포함하며, 및
상기 댐 구조물의 내측에 배치되며 상기 기판과 상기 하부 반도체 칩 사이를 채우는 언더필을 포함하는 반도체 패키지. - 제1항에 있어서,
상기 하부 반도체 칩과 상기 기판은 범프들을 이용하여 전기적으로 연결되고,
상기 상부 반도체 칩과 상기 기판은 본딩 와이어를 이용하여 전기적으로 연결되는 반도체 패키지. - 제1항에 있어서,
상면도에서, 상기 협폭 댐은 상기 하부 반도체 칩의 제1 내지 제3 측면들을 둘러싸고,
상기 광폭 댐은 상기 하부 반도체 칩의 상기 제1, 제3 측면 및 제4 측면을 둘러싸고,
상기 협폭 댐의 제1 단부와 상기 광폭 댐의 제1 단부를 연결하는 제1 연결부, 및
상기 협폭 댐의 제2 단부와 상기 광폭 댐의 제2 단부를 연결하는 제2 연결부를 포함하는 반도체 패키지. - 제3항에 있어서,
상기 제1 및 제2 연결부들와 상기 본딩 패드들 사이의 거리는 50㎛ ~ 150㎛인 반도체 패키지. - 제1항에 있어서,
상기 하부 반도체 칩과 상기 협폭 댐 사이의 거리는 200㎛ ~ 400㎛인 반도체 패키지. - 제1항에 있어서,
상기 하부 반도체 칩과 상기 광폭 댐 사이의 거리는 500㎛ ~ 1000㎛인 반도체 패키지. - 제1항에 있어서,
상기 기판 상의 얼라인 마크를 더 포함하며,
상기 댐 구조물은 상기 얼라인 마크에 대응하여 직각으로 구부러진 컷-아웃을 포함하는 반도체 패키지. - 제1항에 있어서,
상기 적어도 하나의 상부 반도체 칩은 제1 상부 반도체 칩 및 제2 상부 반도체 칩을 포함하며,
상기 광폭 댐은 상기 제1 상부 반도체 칩과 상기 본딩 패드들 사이의 제1 협폭 댐, 제2 상부 반도체 칩과 상기 본딩 패드들 사이의 제2 협폭 댐을 포함하며, 상기 광폭 댐은 상기 제1 협폭 댐과 상기 제2 협폭 댐 사이에 배치되는 반도체 패키지. - 상면에 본딩 패드들을 갖는 기판;
상기 기판 상에 배치되는 하부 반도체 칩 및 상기 하부 반도체 칩 상의 적어도 하나의 상부 반도체 칩;
상기 기판과 상기 하부 반도체 칩 사이를 채우는 언더필을 포함하되, 상기 언더필은 상기 하부 반도체 칩과 상기 본딩 패드들 사이의 비확장 영역 및 상기 비확장 영역보다 내부 폭이 큰 확장 영역을 포함하며, 및;
상기 기판 상에 배치되고 상기 언더필을 둘러싸며 닫힌 루프 형상을 갖는 댐 구조물을 포함하는 반도체 패키지 - 제9항에 있어서,
상기 확장 영역 및 비확장 영역은 상기 댐 구조물의 내측면에 접하는 반도체 패키지.
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