KR20210002976A - Fod adhesive film and semiconductor package comprising thereof - Google Patents

Fod adhesive film and semiconductor package comprising thereof Download PDF

Info

Publication number
KR20210002976A
KR20210002976A KR1020190078925A KR20190078925A KR20210002976A KR 20210002976 A KR20210002976 A KR 20210002976A KR 1020190078925 A KR1020190078925 A KR 1020190078925A KR 20190078925 A KR20190078925 A KR 20190078925A KR 20210002976 A KR20210002976 A KR 20210002976A
Authority
KR
South Korea
Prior art keywords
adhesive film
fod
epoxy resin
film
adhesive layer
Prior art date
Application number
KR1020190078925A
Other languages
Korean (ko)
Other versions
KR102240906B1 (en
Inventor
최재원
김영건
윤근영
조형준
박종현
신범석
조영석
Original Assignee
(주)이녹스첨단소재
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by (주)이녹스첨단소재 filed Critical (주)이녹스첨단소재
Priority to KR1020190078925A priority Critical patent/KR102240906B1/en
Priority to SG10202006305VA priority patent/SG10202006305VA/en
Priority to JP2020114245A priority patent/JP7153690B2/en
Priority to CN202010625963.6A priority patent/CN112185905B/en
Priority to TW109122308A priority patent/TWI825329B/en
Publication of KR20210002976A publication Critical patent/KR20210002976A/en
Application granted granted Critical
Publication of KR102240906B1 publication Critical patent/KR102240906B1/en

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/20—Adhesives in the form of films or foils characterised by their carriers
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/02—Non-macromolecular additives
    • C09J11/04—Non-macromolecular additives inorganic
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J133/00—Adhesives based on homopolymers or copolymers of compounds having one or more unsaturated aliphatic radicals, each having only one carbon-to-carbon double bond, and at least one being terminated by only one carboxyl radical, or of salts, anhydrides, esters, amides, imides, or nitriles thereof; Adhesives based on derivatives of such polymers
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J163/00—Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/20—Adhesives in the form of films or foils characterised by their carriers
    • C09J7/22—Plastics; Metallised plastics
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/40—Adhesives in the form of films or foils characterised by release liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4825—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2203/00—Applications of adhesives in processes or use of adhesives in the form of films or foils
    • C09J2203/326—Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • Die Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Adhesive Tapes (AREA)

Abstract

The present invention relates to a film over die (FOD) adhesive film and to a semiconductor package comprising the same. The FOD adhesive film according to the present invention comprises a laminate structure in which an adhesive layer and a support layer are laminated on one surface of the adhesive layer. Therefore, the occurrence of defects during a cutting process is significantly reduced due to the support layer, and the manufacturing yield of the semiconductor package to which the FOD adhesive film according to the present invention is applied is dramatically increased.

Description

FOD 접착필름 및 이를 포함하는 반도체 패키지{FOD ADHESIVE FILM AND SEMICONDUCTOR PACKAGE COMPRISING THEREOF}FOD adhesive film and semiconductor package including the same {FOD ADHESIVE FILM AND SEMICONDUCTOR PACKAGE COMPRISING THEREOF}

본 발명은 FOD(Film on die) 적용 방식의 반도체 패키지에 적용되는 컨트롤러 다이 매립형 접착필름 및 이를 이용한 반도체 패키지에 관한 것이다.The present invention relates to a controller die-embedded adhesive film applied to a semiconductor package using a film on die (FOD) method, and a semiconductor package using the same.

종래의 반도체 패키지 제조과정에서는 리드 프레임이나 회로기판 부재에 반도체 칩을 부착함에 있어서 우선 다이 고정용 패드 부위에 액상 접착제를 주입, 도포하고 여기에 반도체 칩을 탑재한 후, 액상의 접착제 층을 일정 시간 고온 경화시킨 후, 반도체 칩의 본딩패드와 기판의 본딩 영역간을 전기적 신호 교환이 가능하게 와이어로 본딩하는 공정과 반도체 칩과 와이어 등을 감싸는 몰딩 공정을 행하는 다단계 과정의 공정법이 채택되어 왔다. 종래에 많이 사용되었던 액상 접착제는 돌출 또는 반도체 소자의 경사에 기인하는 와이어 본딩(wire bonding)시의 이상발생, 기포발생, 두께의 제어가 어려운 점 등의 단점이 있었다. 따라서, 최근에는 액상 접착제를 대신하여 접착 필름이 주로 사용되고 있는 추세이다.In the conventional semiconductor package manufacturing process, when attaching a semiconductor chip to a lead frame or a circuit board member, a liquid adhesive is first injected and applied to the die fixing pad, and the semiconductor chip is mounted thereon, and then a liquid adhesive layer is applied for a certain period of time. After curing at a high temperature, a multi-step process has been adopted in which a bonding pad of a semiconductor chip and a bonding region of a substrate are bonded with a wire so that electrical signals can be exchanged, and a molding process that wraps a semiconductor chip and a wire is performed. Liquid adhesives, which have been widely used in the past, have disadvantages such as occurrence of abnormalities during wire bonding due to protrusion or inclination of semiconductor devices, generation of bubbles, and difficulty in controlling thickness. Therefore, in recent years, instead of liquid adhesives, adhesive films are mainly used.

최근 전자기기의 소형화, 고기능화, 대용량화 추세가 확대되고 이에 따른 반도체 패키지의 고밀도화, 고집적화에 대한 필요성이 급격히 커짐에 따라 반도체 칩 크기가 점점 커지고 있으며 집적도 측면에서도 개선하기 위하여 칩을 다단으로 적층하는 스택 패키지 방법이 점차로 증가하고 있다.In recent years, as the trend of miniaturization, high functionality, and large capacity of electronic devices is expanding, and the need for high density and high integration of semiconductor packages accordingly increases, the size of semiconductor chips is gradually increasing, and a stack package in which chips are stacked in multiple stages to improve the degree of integration. The methods are gradually increasing.

이러한 반도체 패키지에서는 반도체 소자 간의 신호나 동작을 제어하기 위한 컨트롤러 다이(Controller die)가 사용되며, 컨트롤러 다이는 통상적으로 구조적 특성으로 인하여 반도체 외곽부 또는 반도체 상부측에 위치하고 있다.In such a semiconductor package, a controller die is used to control signals or operations between semiconductor devices, and the controller die is typically located on the outer side of the semiconductor or on the upper side of the semiconductor due to structural characteristics.

하지만, 컨트롤러 다이가 반도체 외곽부에 위치하게 될 경우, 반도체 패키지의 면적이 증가하여 패키지 축소에 한계를 가지고 있으며, 반도체 상부측에 위치할 경우, 컨트롤러 접속에 필요한 와이어 길이가 길어짐에 따라, 저항이 증가하게 되어 고속 전송에 어려움을 지니고 있다.However, when the controller die is located on the outer side of the semiconductor, the area of the semiconductor package increases, which limits the package reduction. When located on the upper side of the semiconductor, the resistance increases as the wire length required for connection to the controller increases. As it increases, it has difficulty in high-speed transmission.

따라서, 이 컨트롤러 다이를 반도체 적층부 하단에 매립함으로써 패키지 면적의 효율적 활용 및 신호의 고속 전송에 뛰어난 구조를 확보 할 수 있다. 컨트롤러 다이를 반도체 적층부 하단에 매립하기 위해서, 상기 컨트롤러 다이 보다 두꺼운 두께를 갖는 FOD(film over die) 접착필름이 사용되었다.Therefore, by embedding this controller die at the bottom of the semiconductor laminate, it is possible to secure a structure excellent for efficient use of the package area and high-speed signal transmission. In order to bury the controller die at the bottom of the semiconductor stack, a film over die (FOD) adhesive film having a thickness thicker than that of the controller die was used.

그러나, FOD 접착필름이 적용된 반도체 패키지는 FOD 접착필름의 위에 적층되는 반도체 다이(웨이퍼 칩)와 다이 어태치 필름 위에 적층되는 반도체 다이를 각각 별도로 관리해야 한다. 이에 따라, FOD 접착필름이 적용된 반도체 패키지는 일반 반도체 패키지 대비 총 수율이 감소하는 문제가 있다.However, in the semiconductor package to which the FOD adhesive film is applied, the semiconductor die (wafer chip) stacked on the FOD adhesive film and the semiconductor die stacked on the die attach film must be separately managed. Accordingly, the semiconductor package to which the FOD adhesive film is applied has a problem in that the total yield is reduced compared to a general semiconductor package.

또한, FOD 접착필름을 반도체 패키지에 적용하는 가운데 FOD 접착필름이 일정 사이즈로 컷팅되는 절단 공정이 진행될 때 접착층의 융착 과다로 픽업 불량률이 증가하는 문제가 발생되어 왔다.In addition, while the FOD adhesive film is applied to a semiconductor package, when a cutting process in which the FOD adhesive film is cut to a predetermined size is in progress, a problem of an increase in pickup defect rate due to excessive fusion of the adhesive layer has occurred.

위와 같은 문제점 때문에 해당 업계에서는 FOD 접착필름이 적용된 반도체 패키지를 기피하는 현상이 발생하고 있다. Due to the above problems, there is a phenomenon in the industry that avoids semiconductor packages to which FOD adhesive films are applied.

이에 따라, 위와 같은 문제점을 해결할 수 있는 신규의 FOD 접착필름이 요구된다. Accordingly, a new FOD adhesive film capable of solving the above problems is required.

본 발명은 상술한 기술적 문제점을 해결하기 위해 새로운 구조를 갖는 FOD 접착필름을 제공하는 것을 목적으로 한다.An object of the present invention is to provide an FOD adhesive film having a new structure in order to solve the above technical problem.

또한 본 발명은 제조 공정이 간단하고 제조 수율이 높은 FOD 접착필름이 적용된 반도체 패키지를 제공하는 것을 목적으로 한다.In addition, an object of the present invention is to provide a semiconductor package to which an FOD adhesive film having a simple manufacturing process and a high manufacturing yield is applied.

상기 과제를 해결하기 위한 본 발명의 일실시예에 따른 FOD 접착필름은 접착층의 일면에 서포트층이 적층된 신규의 적층구조를 포함한다. The FOD adhesive film according to an embodiment of the present invention for solving the above problem includes a novel laminate structure in which a support layer is laminated on one side of the adhesive layer.

또한, 상기 과제를 해결하기 위한 본 발명의 다른 일실시예에 따른 반도체패키지는 접착층의 일면에 서포트층이 적층된 신규의 적층구조를 갖는 FOD 접착필름을 포함하고, 컨트롤러 다이의 적어도 일부가 상기 접착층의 내부에 매립되어 있는 구조를 갖는다.In addition, a semiconductor package according to another embodiment of the present invention for solving the above problem includes a FOD adhesive film having a novel laminate structure in which a support layer is stacked on one side of an adhesive layer, and at least a part of the controller die is the adhesive layer It has a structure that is buried inside of

본 발명에 따른 FOD 접착필름은 접착층의 일면에 서포트층이 적층된 신규의 적층구조를 포함하여, 상기 서포트층으로 인해 컷팅 공정 시 불량률 발생이 현저히 감소하는 우수한 효과를 갖는다.The FOD adhesive film according to the present invention includes a novel laminate structure in which a support layer is laminated on one side of the adhesive layer, and has an excellent effect of remarkably reducing the occurrence of defect rates during the cutting process due to the support layer.

또한, 본 발명에 따른 FOD 접착필름이 적용된 반도체 패키지는 FOD 접착필름 위에 적층되는 반도체 다이와 다이 어태치 필름에 의해서 적층되는 반도체 다이를 별도로 관리할 필요가 없기 때문에, 종래의 FOD 접착필름이 적용된 반도체 패키지 대비 수율이 비약적으로 상승하는 효과를 갖는다.In addition, since the semiconductor package to which the FOD adhesive film according to the present invention is applied does not require separate management of the semiconductor die stacked on the FOD adhesive film and the semiconductor die stacked by the die attach film, the conventional semiconductor package to which the FOD adhesive film is applied. It has the effect of dramatically increasing the contrast yield.

도 1은 본 발명의 일실시예에 따른 FOD 접착필름을 도시한 단면도이다.
도 2는 본 발명의 다른 일실시예에 따른 FOD 접착필름을 도시한 단면도이다.
도 3은 본 발명에 따른 FOD 접착필름이 반도체 패키지에 적용되는 공정을 개략적으로 도시한 공정도이다.
도 4는 본 발명에 따른 반도체 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a FOD adhesive film according to an embodiment of the present invention.
2 is a cross-sectional view showing an FOD adhesive film according to another embodiment of the present invention.
3 is a process diagram schematically showing a process in which the FOD adhesive film according to the present invention is applied to a semiconductor package.
4 is a cross-sectional view showing a semiconductor package according to the present invention.

전술한 목적, 특징 및 장점은 상세하게 후술되며, 이에 따라 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 것이다. 본 발명을 설명함에 있어서 본 발명과 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 상세한 설명을 생략한다. 이하, 본 발명에 따른 바람직한 실시예를 상세히 설명하기로 한다.The above-described objects, features, and advantages will be described later in detail, and accordingly, a person of ordinary skill in the art to which the present invention pertains will be able to easily implement the technical idea of the present invention. In describing the present invention, if it is determined that a detailed description of known technologies related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description will be omitted. Hereinafter, a preferred embodiment according to the present invention will be described in detail.

본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위하여 제공되는 것이다.The present invention is not limited to the embodiments disclosed below, but may be implemented in a variety of different forms, only the present embodiment is intended to complete the disclosure of the present invention, and the scope of the invention to those of ordinary skill in the art. It is provided to inform you.

이하, 본 발명에 따른 FOD 접착필름 및 이를 포함하는 반도체 패키지에 대해 상세히 설명하기로 한다.Hereinafter, the FOD adhesive film according to the present invention and a semiconductor package including the same will be described in detail.

<FOD(film over die) 접착필름><FOD(film over die) adhesive film>

도 1을 참조하면, 본 발명에 따른 FDO 접착필름(100)은 접착층(10) 및 상기 접착층(10)의 일면에 서포트층(20)이 적층된 적층구조;를 포함한다. 아울러, 본 발명의 FOD 접착필름에 포함된 상기 적층구조가 반도체 패키지에 그대로 적용된다. Referring to FIG. 1, the FDO adhesive film 100 according to the present invention includes an adhesive layer 10 and a laminate structure in which a support layer 20 is stacked on one surface of the adhesive layer 10. In addition, the laminated structure included in the FOD adhesive film of the present invention is applied to the semiconductor package as it is.

종래의 FOD 접착필름은 오직 접착층 만이 반도체 패키지에 적용되었다. 이와 달리 본 발명에 따른 FOD 접착필름(100)은 접착층(10) 및 상기 접착층(10)의 일면에 서포트층(20)이 적층된 적층구조를 포함하고, 상기 적층구조가 반도체 패키지에 적용된다. 이처럼, 본 발명에 따른 FOD 접착필름(100)은 적어도 2층의 적층구조를 갖는 점에서, 종래의 FOD 접착필름과 구성상 차이가 있다.In the conventional FOD adhesive film, only the adhesive layer was applied to the semiconductor package. In contrast, the FOD adhesive film 100 according to the present invention includes an adhesive layer 10 and a stacked structure in which a support layer 20 is stacked on one surface of the adhesive layer 10, and the stacked structure is applied to a semiconductor package. As such, the FOD adhesive film 100 according to the present invention is different in configuration from the conventional FOD adhesive film in that it has a laminated structure of at least two layers.

본 발명의 FOD 접착필름에 포함된 서포트층(20)은 상기 접착층(10)의 일면에 적층되어 상기 접착층(10)의 일면을 보호하면서 다이 어태치 필름이 접착되어 있는 반도체 다이가 로딩될 수 있는 중간층 기능을 한다. The support layer 20 included in the FOD adhesive film of the present invention is laminated on one surface of the adhesive layer 10 to protect one surface of the adhesive layer 10 while the semiconductor die to which the die attach film is adhered can be loaded. It functions as an intermediate layer.

상기 서포트층(20)은 상기 접착층(10)의 일면에 적층되면서 상기 접착층(10)을 보호하고 또한 다이 어태치 필름이 접착되어 있는 반도체 다이가 로딩될 수 있는 폴리머 소재라면 제한 없이 적용이 가능하다. 바람직하게는, 상기 서포트층(20)은 폴리이미드(polyimide, PI), 폴리이미드아미드(polyimideamide), 폴리에테르이미드(polyetherimide, PEI), 폴리에틸렌테레프탈레이트(polyethyleneterephtalate, PET), 폴리에틸렌나프탈레이트(polyethylenenaphthalate, PEN) 및 폴리에테르에테르케톤(polyetheretherketon, PEEK) 가운데 1종 이상의 재료를 포함할 수 있다.The support layer 20 can be applied without limitation as long as it is a polymer material that protects the adhesive layer 10 while being laminated on one surface of the adhesive layer 10 and can load the semiconductor die to which the die attach film is adhered. . Preferably, the support layer 20 is a polyimide (PI), polyimideamide (polyimideamide), polyetherimide (polyetherimide, PEI), polyethylene terephtalate (polyethyleneterephtalate, PET), polyethylene naphthalate (polyethylenenaphthalate, PEN) and polyetheretherketon (PEEK) may contain one or more materials.

바람직하게는 상기 서포트층(20)은 5~50㎛의 두께를 가질 수 있다. 상기 서포트층(20)의 두께가 5㎛ 미만이면 상기 접착층(10)의 일면을 보호하기 위한 충분한 두께를 가지지 못하기 때문에 FOD 접착필름을 절단하는 과정에서 불량이 발생할 가능성이 높아진다. 또한 상기 서포트층(20)의 두께가 50㎛를 초과하면 불필요하게 두꺼운 두께로 인해 단가가 상승하는 등의 문제가 있다.Preferably, the support layer 20 may have a thickness of 5 to 50 μm. If the thickness of the support layer 20 is less than 5 μm, it does not have a sufficient thickness to protect one surface of the adhesive layer 10, and thus, there is a high possibility that defects may occur in the process of cutting the FOD adhesive film. In addition, when the thickness of the support layer 20 exceeds 50 μm, there is a problem such as an increase in unit cost due to an unnecessarily thick thickness.

다음으로, 본 발명의 FOD 접착필름(100)에 포함된 접착층(10)은 반도체 패키지에 포함된 컨트롤러 다이의 적어도 일부를 매립하는 기능을 갖는다. Next, the adhesive layer 10 included in the FOD adhesive film 100 of the present invention has a function of filling at least a part of the controller die included in the semiconductor package.

상기 접착층(10)은 우수한 컨트롤러 다이 매립성과 더불어, 적정 필릿(fillet), 와이어 눌림성 방지, 적정 경화성, 내습성 및 내열성을 확보하기 위해 공지된 최적의 조성비로 제조될 수 있다.The adhesive layer 10 may be manufactured in a known optimal composition ratio in order to secure an appropriate fillet, wire pressurization prevention, appropriate curability, moisture resistance, and heat resistance in addition to excellent controller die embedding.

바람직하게는, 상기 접착층(10)은 아크릴 공중합체, 에폭시 수지 및 무기 필러를 포함할 수 있다. Preferably, the adhesive layer 10 may include an acrylic copolymer, an epoxy resin, and an inorganic filler.

상기 접착층(10)에 포함된 아크릴 공중합체는 유리전이온도 0℃ ~ 20℃ 및 중량평균분자량 100,000 ~ 500,000인 아크릴 공중합체를 포함할 수 있다. 이때, 아크릴 공중합체의 중량평균분자량이 100,000 미만인 경우, 상기 접착층의 필름형성이 어렵고 또한 상기 접착층의 유동성이 과다해져서 와이어 본딩 패드 오염을 야기시킬 수 있다. 아울러, 아크릴 공중합체의 중량평균분자량이 500,000을 초과하면 고분자 중합이 어려워 실제적으로 적용은 어려울 뿐만 아니라, 코팅성이 불량 우려가 있다. 무엇보다 후술할 서포트층과의 적층이 되는 점을 고려하여 아크릴 공중합체의 중량평균분자량은 100,000 ~ 500,000인 것이 바람직하다. 또한, 아크릴 공중합체의 유리전이온도가 0℃ 미만인 경우, 접착층 자체의 tack(끈적임) 특성이 강하게 발현하여 픽업(pick up) 공정에서 수율이 저하될 우려가 있으며, 유리전이온도가 20℃을 초과하면 부착 특성이 저하되어, 마운트(mount) 공정에서 보이드를 유발할 수 있다. The acrylic copolymer included in the adhesive layer 10 may include an acrylic copolymer having a glass transition temperature of 0°C to 20°C and a weight average molecular weight of 100,000 to 500,000. At this time, when the weight average molecular weight of the acrylic copolymer is less than 100,000, film formation of the adhesive layer is difficult, and fluidity of the adhesive layer becomes excessive, which may cause contamination of the wire bonding pad. In addition, when the weight average molecular weight of the acrylic copolymer exceeds 500,000, polymer polymerization is difficult and practical application is difficult, and there is a fear of poor coatability. Above all, it is preferable that the weight average molecular weight of the acrylic copolymer is 100,000 to 500,000 in consideration of the point of being laminated with a support layer to be described later. In addition, when the glass transition temperature of the acrylic copolymer is less than 0℃, the tack (sticky) characteristic of the adhesive layer itself is strongly expressed, and there is a possibility that the yield may decrease in the pick-up process, and the glass transition temperature exceeds 20℃. If the adhesive property is lowered, it may cause voids in the mounting process.

아울러, 상기 아크릴 공중합체는 에폭시기 함유 아크릴 공중합체로서, 글리시딜아크릴레이트 또는 글리시딜메타크릴레이트 3 ~ 15 중량%를 포함할 수 있다. 아크릴 공중합체 내 에폭시기 함량이 3 중량% 미만이면 에폭시 수지와 상용성이 충분하지 않고, 에폭시기 함량이 15 중량%를 초과하면 경화에 의한 점도 상승 속도가 너무 빨라 경화 공정에서 열압에 의한 컨트롤러 다이의 매립이 충분히 이루어 지지 않을 수가 있다. In addition, the acrylic copolymer is an epoxy group-containing acrylic copolymer, and may include 3 to 15% by weight of glycidyl acrylate or glycidyl methacrylate. If the content of the epoxy group in the acrylic copolymer is less than 3% by weight, compatibility with the epoxy resin is not sufficient, and if the content of the epoxy group exceeds 15% by weight, the rate of increase in viscosity due to curing is too fast, and the controller die is buried by heat pressure in the curing process. This may not be enough.

또한, 상기 접착층(10)은 에폭시 수지를 포함할 수 있다. 보다 구체적으로 상기 에폭시 수지는 비스페놀계 에폭시 수지, 바이페닐계 에폭시 수지, 나프탈렌계 에폭시 수지, 플로렌계 에폭시 수지, 페놀노볼락계 에폭시 수지, 크레졸노볼락계 에폭시 수지, 트리스하이드록 실페닐메탄계 에폭시 수지 및 테트라페닐메탄계 에폭시 수지 중에서 선택된 1종 이상을 포함할 수 있으며, 바람직하게는 비스페놀계 에폭시 수지, 페놀노볼락계 에폭시 수지 및 크레졸노볼락계 에폭시 수지 중에서 선택된 1종 이상을 혼합하여 사용할 수 있다. 이때, 상기 비스페놀계 에폭시 수지로는 비스페놀 A형 에폭시 수지, 비스페놀 F형 에폭시 수지, 비스페놀 S형 에폭시 수지, 수소첨가 비스페놀 A형 에폭시 수지, 비스페놀 AF형 에폭시 수지 등이 있다. In addition, the adhesive layer 10 may include an epoxy resin. More specifically, the epoxy resin is a bisphenol-based epoxy resin, a biphenyl-based epoxy resin, a naphthalene-based epoxy resin, a florene-based epoxy resin, a phenol novolak-based epoxy resin, a cresol novolac-based epoxy resin, and trishydroxylphenylmethane-based It may include at least one selected from an epoxy resin and a tetraphenylmethane-based epoxy resin, and preferably, at least one selected from a bisphenol-based epoxy resin, a phenol novolak-based epoxy resin, and a cresol novolak-based epoxy resin is used by mixing. I can. At this time, the bisphenol type epoxy resin includes a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol S type epoxy resin, a hydrogenated bisphenol A type epoxy resin, and a bisphenol AF type epoxy resin.

또한, 상기 에폭시 수지는 10℃ ~ 35℃에서 액상인 에폭시 수지; 및 10℃ ~ 35℃에서 고상인 에폭시 수지;를 포함할 수 있고, 이들이 적정비로 접착층에 포함될 수 있다. 상기 액상 에폭시 수지는 에폭시 당량 150 ~ 210 g/eq 및 점도 10,000 ~ 15,000 cps(25℃)일 수 있으며, 바람직하게는 에폭시 당량 170 ~ 200 g/eq 및 점도 10,500 ~ 14,500 cps(25℃)일 수 있다. 그리고, 상기 고상 에폭시 수지는 에폭시 당량 180 ~ 240 g/eq 및 연화점 50℃ ~ 70℃일 수 있으며, 바람직하게는 에폭시 당량 195 ~ 225 g/eq 및 연화점 50℃ ~ 65℃일 수 있다.In addition, the epoxy resin is a liquid epoxy resin at 10 ℃ ~ 35 ℃; And a solid epoxy resin at 10° C. to 35° C., and these may be included in the adhesive layer at an appropriate ratio. The liquid epoxy resin may have an epoxy equivalent of 150 to 210 g/eq and a viscosity of 10,000 to 15,000 cps (25°C), and preferably, an epoxy equivalent of 170 to 200 g/eq and a viscosity of 10,500 to 14,500 cps (25°C). have. In addition, the solid epoxy resin may have an epoxy equivalent of 180 to 240 g/eq and a softening point of 50°C to 70°C, and preferably, an epoxy equivalent of 195 to 225 g/eq and a softening point of 50°C to 65°C.

또한, 본 발명에 따른 접착층(10)은 무기 필러를 포함할 수 있다. 상기 무기 필러는 바람직하게는 평균입경 약 0.1㎛ ~ 2㎛의 구상 분말을 포함할 수 있다. 이때, 무기 필러의 평균입경이 0.1㎛ 미만이면 접착층 내에서 뭉쳐서 존재하는 문제가 있을 수 있고, 2㎛를 초과하면 컨트롤러 다이 및/또는 반도체 다이가 무기 필러에 의한 패턴 손상이나 크랙이 발생할 수 있고, 접착층의 접착성 저하가 발생할 수 있다.In addition, the adhesive layer 10 according to the present invention may include an inorganic filler. The inorganic filler may preferably include spherical powder having an average particle diameter of about 0.1 μm to 2 μm. At this time, if the average particle diameter of the inorganic filler is less than 0.1 μm, there may be a problem that it is aggregated in the adhesive layer, and if it exceeds 2 μm, pattern damage or cracks may occur in the controller die and/or the semiconductor die due to the inorganic filler, Deterioration of adhesion of the adhesive layer may occur.

상기 구상 분말은 알루미나, 실리카, 수산화마그네슘 및 탄산칼슘 중에서 선택된 1종 이상을 포함할 수 있으며, 바람직하게는 알루미나 및 실리카 중에서 선택된 1종 이상을 포함할 수 있다.The spherical powder may include at least one selected from alumina, silica, magnesium hydroxide, and calcium carbonate, and preferably at least one selected from alumina and silica.

바람직하게는 상기 접착층(10)은 60~150㎛의 두께를 가질 수 있다. 상기 접착층(20)의 두께가 60㎛ 미만이면 컨트롤러 다이를 매립하기 위한 충분한 충분한 두께를 가지지 못하기 때문에 반도체 패키지의 불량이 발생할 가능성이 높아진다. 또한 상기 접착층(10)의 두께가 150㎛를 초과하면 불필요하게 두꺼운 두께로 인해 단가가 상승하는 등의 문제가 있다.Preferably, the adhesive layer 10 may have a thickness of 60 to 150 μm. If the thickness of the adhesive layer 20 is less than 60 μm, it does not have a sufficient thickness to fill the controller die, and thus the possibility of occurrence of a defect in the semiconductor package increases. In addition, when the thickness of the adhesive layer 10 exceeds 150 μm, there is a problem such as an increase in unit cost due to an unnecessarily thick thickness.

아울러 도 2를 참조하면, 본 발명에 따른 FOD 접착필름(101)은 접착층(10)의 다른 일면(서포트층(20)이 적층된 면의 반대면)에 이형필름(30)을 더 포함할 수 있다. 또한, 서포트층(20)의 일면에 이형필름(30)이 더 포함될 수도 있다.In addition, referring to FIG. 2, the FOD adhesive film 101 according to the present invention may further include a release film 30 on the other side of the adhesive layer 10 (the opposite side to the side on which the support layer 20 is laminated). have. In addition, a release film 30 may be further included on one surface of the support layer 20.

상기 이형필름(30)의 소재는 FOD 접착필름(101)을 보호할 수 있는 폴리머 필름 소재라면 제한되지 않는다. 바람직하게는 폴리에틸렌테레프탈레이트(polyethyleneterephtalate, PET)를 포함하는 소재가 상기 이형필름(30)에 사용될 수 있다.The material of the release film 30 is not limited as long as it is a polymer film material capable of protecting the FOD adhesive film 101. Preferably, a material including polyethylene terephtalate (PET) may be used for the release film 30.

도 3을 참조하면, 도 3에는 본 발명에 따른 FOD 접착필름(100)이 이송, 절단 및 픽업되어 후술할 반도체 패키지에 적용되기 위한 공정이 개략적으로 도시되어 있다.3, FIG. 3 schematically illustrates a process for transferring, cutting, and picking up the FOD adhesive film 100 according to the present invention to be applied to a semiconductor package to be described later.

본 발명에 따른 FOD 접착필름(100)이 이형필름(30)을 포함하는 경우 먼저 이형필름이 제거되는 공정이 진행될 수 있다. 물론, FOD 접착필름(100)이 이형필름(30)을 포함하지 않는다면 이형필름 제거 공정은 생략된다.When the FOD adhesive film 100 according to the present invention includes the release film 30, a process in which the release film is first removed may be performed. Of course, if the FOD adhesive film 100 does not include the release film 30, the release film removal process is omitted.

다음으로, FOD 접착필름(100)은 이송 공정을 거쳐서 블레이드에 의해 일정 사이즈로 컷팅되는 절단 공정을 거친다. 이후 컷팅된 FOD 접착필름(100)은 픽업(pick up)되어 반도체 패키지에 적용된다.Next, the FOD adhesive film 100 undergoes a cutting process that is cut to a predetermined size by a blade through a transfer process. Then, the cut FOD adhesive film 100 is picked up and applied to a semiconductor package.

상술한 바와 같이, FOD 접착필름을 반도체 패키지에 적용하는 가운데 FOD 접착필름이 일정 사이즈로 컷팅되는 절단 공정이 진행될 때, 접착층의 융착 과다로 픽업 불량률이 증가하는 문제가 발생되어 왔다.As described above, when a cutting process in which the FOD adhesive film is cut to a predetermined size while the FOD adhesive film is applied to a semiconductor package is performed, a problem of an increase in pickup defect rate due to excessive fusion of the adhesive layer has occurred.

그러나, 본 발명에 따른 FOD 접착필름(100)은 종래의 FOD 접착필름과 달리 접착층(10) 및 상기 접착층(10)에 적층된 서포트층(20)을 포함한 적층구조를 가짐으로써, 컷팅 공정 시 상기 서포트층(20)에 의해 상기 접착층(10)의 융착 과다 현상을 억제하여 픽업 불량률 발생이 현저히 감소하는 효과가 있다. However, unlike the conventional FOD adhesive film, the FOD adhesive film 100 according to the present invention has a laminated structure including an adhesive layer 10 and a support layer 20 laminated on the adhesive layer 10. The support layer 20 suppresses excessive fusion of the adhesive layer 10, thereby remarkably reducing the occurrence of a pickup defect rate.

<반도체 패키지><semiconductor package>

이하에서는 본 발명에 따른 반도체 패키지에 대해 상세히 설명한다.Hereinafter, a semiconductor package according to the present invention will be described in detail.

도 4를 참조하면, 본 발명에 따른 반도체 패키지는 기판(200); 상기 기판(200) 상부에 실장된 컨트롤러 다이(51); 상기 기판(200) 상부에 형성된 FOD 접착필름(100); 및 상기 FOD 접착필름(100) 상에 적층된 반도체 다이(60);를 포함하고, 상기 FOD 접착필름(100)은 접착층(10) 및 상기 접착층(10)의 일면에 서포트층(20)이 적층된 적층구조를 포함하고, 상기 컨트롤러 다이(51)의 적어도 일부가 상기 접착층(10)의 내부에 매립되어 있는 구조를 갖는다. Referring to FIG. 4, a semiconductor package according to the present invention includes a substrate 200; A controller die 51 mounted on the substrate 200; FOD adhesive film 100 formed on the substrate 200; And a semiconductor die 60 laminated on the FOD adhesive film 100, wherein the FOD adhesive film 100 includes an adhesive layer 10 and a support layer 20 on one surface of the adhesive layer 10 It includes a laminated structure, and has a structure in which at least a part of the controller die 51 is buried in the adhesive layer 10.

또한 도 3을 참조하면 본 발명에 따른 반도체 패키지는 상기 기판(200) 상에 본딩패드(70)가 형성될 수 있고, 상기 본딩패드는 반도체 다이(칩)(60) 상에 형성된 본딩패드(70)와 와이어로 연결될 수 있다. Also, referring to FIG. 3, in the semiconductor package according to the present invention, a bonding pad 70 may be formed on the substrate 200, and the bonding pad is a bonding pad 70 formed on a semiconductor die (chip) 60. ) And can be connected by wire.

상기 반도체 다이(60)는 일면에 다이 어태치 필름(52)이 접착된 형태로 반도체 패키지에 적용될 수 있다.The semiconductor die 60 may be applied to a semiconductor package in a form in which a die attach film 52 is adhered to one surface.

또한 본 발명에 따른 반도체 패키지는 반도체 다이(60)를 포함하는 적층체가 EMC(Epoxy molding compound)(80)에 매립된 구조를 가질 수 있다.In addition, the semiconductor package according to the present invention may have a structure in which a laminate including a semiconductor die 60 is embedded in an epoxy molding compound (EMC) 80.

아울러, 본 발명에 따른 반도체 패키지는 상기 접착층(10) 내 단수 또는 복수개의 수동소자; 단수 또는 복수개의 본딩패드(70); 및 단수 또는 복수개의 와이어;를 더 포함할 수 있다.In addition, the semiconductor package according to the present invention includes a single or a plurality of passive elements in the adhesive layer 10; A single or a plurality of bonding pads 70; And a single or a plurality of wires; may further include.

또한 본 발명에 따른 반도체 패키지는 상기 기판(200) 및 실장된 컨트롤러 다이(51) 상에 다이 어태치 필름(51)을 포함할 수 있고, 상기 FOD 접착필름의 서포트층(20)과 반도체 다이(60) 사이에 다이 어태치 필름(52)을 포함할 수 있다.In addition, the semiconductor package according to the present invention may include a die attach film 51 on the substrate 200 and the mounted controller die 51, and the support layer 20 and the semiconductor die of the FOD adhesive film ( A die attach film 52 may be included between 60).

상술한 바와 같이, FOD 접착필름이 적용된 반도체 패키지는 FOD 접착필름의 위에 적층되는 반도체 다이(웨이퍼 칩)와 다이 어태치 필름 위에 적층되는 반도체 다이를 각각 별도로 관리해야 한다. 이에 따라, FOD 접착필름이 적용된 반도체 패키지는 일반 반도체 패키지 대비 총 수율이 감소하는 문제가 있다.As described above, in the semiconductor package to which the FOD adhesive film is applied, the semiconductor die (wafer chip) stacked on the FOD adhesive film and the semiconductor die stacked on the die attach film must be separately managed. Accordingly, the semiconductor package to which the FOD adhesive film is applied has a problem in that the total yield is reduced compared to a general semiconductor package.

그러나, 본 발명에 따른 FOD 접착필름(100)이 적용된 반도체 패키지는 FOD 접착필름(100) 위에 적층되는 반도체 다이와 다이 어태치 필름에 의해서 적층되는 반도체 다이를 별도로 관리할 필요가 없다. 다시 말해, 본 발명에 따른 FOD 접착필름(100)이 적용된 반도체 패키지는 FOD 접착필름(100) 위에 적층되는 반도체 다이도 다이 어태치 필름을 구비한 반도체 다이를 사용할 수 있다. 이에 따라, 종래의 FOD 접착필름이 적용된 반도체 패키지 대비 수율이 비약적으로 상승하는 효과를 갖는다.However, the semiconductor package to which the FOD adhesive film 100 according to the present invention is applied does not require separate management of the semiconductor die stacked on the FOD adhesive film 100 and the semiconductor die stacked by the die attach film. In other words, in the semiconductor package to which the FOD adhesive film 100 according to the present invention is applied, a semiconductor die stacked on the FOD adhesive film 100 may also use a semiconductor die having a die attach film. Accordingly, it has the effect of dramatically increasing the yield compared to a semiconductor package to which a conventional FOD adhesive film is applied.

<실시예><Example>

1. FOD 접착필름의 제조1. Preparation of FOD adhesive film

먼저 아래와 같은 조성을 이용하여 접착층을 형성하는 코팅액을 제조하였다.First, a coating solution for forming an adhesive layer was prepared using the following composition.

아크릴 공중합체(나가세켐텍 SG-P307S, 수평균분자량 250,000, 유리전이온도 10℃)를 준비하였다.An acrylic copolymer (Nagase Chemtech SG-P307S, number average molecular weight 250,000, glass transition temperature 10°C) was prepared.

상온(15 ~ 35℃)에서 액상인 에폭시 수지인 비스페놀A 에폭시 수지(국도화학 YD-128, 에폭시당량:187g/eq) 및 상온(15 ~ 35℃)에서 고상인 에폭시 수지인 크레졸노볼락 에폭시 수지(국도화학 YDCN-500-5P, 에폭시당량:206g/eq)를 열경화성 수지로서 준비하였다.Bisphenol A epoxy resin (Kukdo Chemical YD-128, epoxy equivalent: 187g/eq), a liquid epoxy resin at room temperature (15 ~ 35℃), and cresol novolac epoxy resin, a solid epoxy resin at room temperature (15 ~ 35℃) (Kukdo Chemical YDCN-500-5P, epoxy equivalent: 206 g/eq) was prepared as a thermosetting resin.

경화제로서, 페놀노볼락 수지(코오롱유화 KPH-F2004, OH당량:106g/eq, 연화점:120)를 준비하였으며, 무기충진제로서 구상 실리카(전기화학공업주식회사 SFP-30M, 평균 입경 0.7㎛)를 준비하였다.As a curing agent, a phenol novolak resin (KPH-F2004, OH equivalent: 106 g/eq, softening point: 120) was prepared as an inorganic filler, and spherical silica (electrochemical industry Co., Ltd. SFP-30M, average particle diameter 0.7 μm) was prepared as an inorganic filler. I did.

또한, 경화촉진제로서 이미다졸계 경화촉진제(큐아졸 2PH)를 준비하였다.In addition, an imidazole-based curing accelerator (cuazole 2PH) was prepared as a curing accelerator.

다음으로, 상기 열가소성 수지, 액상 에폭시, 고상 에폭시, 경화제, 무기충진제 및 경화촉진제를 24 : 12 : 12 : 11 : 40 : 1의 중량 배합비로 혼합하여 혼합액을 제조하였다.Next, the thermoplastic resin, liquid epoxy, solid epoxy, curing agent, inorganic filler and curing accelerator were mixed at a weight mixing ratio of 24: 12: 12: 11: 40: 1 to prepare a mixed solution.

다음으로, 코팅성 확보 차원에서 상기 혼합액을 메틸에틸케톤(MEK)과 1:0.9 중량비로 혼합하여 접착 코팅액을 제조하였다. Next, in order to secure coating properties, the mixture was mixed with methyl ethyl ketone (MEK) in a weight ratio of 1:0.9 to prepare an adhesive coating solution.

다음으로, 두께 30㎛의 폴리에테르에테르케톤(polyetheretherketon, PEEK)을 서포트층으로 준비하고 상기 PEEK 필름 상에 접착 코팅액을 도포하였다. 상기 접착 코팅액 상에 이형 처리한 폴리에스테르 필름을 적층하고 130℃에서 5분 동안 열풍 건조기 내에서 혼합용제를 건조, 제거시킴으로써 반도체 패키지용 FOD 접착시트를 제작하였다.Next, a polyetheretherketon (PEEK) having a thickness of 30 μm was prepared as a support layer, and an adhesive coating solution was applied on the PEEK film. A release-treated polyester film was laminated on the adhesive coating solution, and the mixed solvent was dried and removed in a hot air dryer at 130° C. for 5 minutes to prepare a FOD adhesive sheet for a semiconductor package.

2. 컨트롤러 다이가 매립된 기판 제작 2. Fabrication of board with embedded controller die

시판되는 10㎛ 다이어태치용 필름을 사용하여 두께 50㎛, 길이3mmХ5mm(가로Х세로) 사이즈의 컨트롤러 칩(다이)을 온도 120℃, 압력 1kg, 시간 1초의 조건으로 PCB 기판 위에 부착하여 컨트롤러가 포함된 기판을 제작하였다.Using a commercially available 10㎛ die attach film, attach a controller chip (die) with a thickness of 50㎛ and a length of 3mm to 5mm (horizontal to vertical) on the PCB under the conditions of temperature 120℃, pressure 1kg, time 1 second, and the controller is included. The prepared substrate was prepared.

3 FOD 접착필름을 이송, 컷팅, 픽업 및 기판에 부착하여 반도체 패키지 제작3 FOD adhesive film is transferred, cut, picked up and attached to the substrate to produce a semiconductor package

준비된 FOD 접착필름을 이송하면서 절단하여 총 150개의 FOD 접착필름 샘플을 제작하였다. 상기 FOD 접착필름 샘플을 다이본딩 장치 SPA-300S(상품명, 신카와)를 이용하여 니들(NEEDLE) 개수 21, 니들 높이 0.30mm으로 픽업을 진행하여 온도 120℃, 압력 1kgf, 시간 1초로 앞서 제작한 컨트롤러 칩이 부착된 기판에 접착하였다.A total of 150 FOD adhesive film samples were produced by cutting while transferring the prepared FOD adhesive film. The FOD adhesive film sample was picked up using a die-bonding device SPA-300S (brand name, Shinkawa) with a needle (NEEDLE) of 21 and a needle height of 0.30 mm, and was prepared in advance with a temperature of 120°C, a pressure of 1 kgf, and a time of 1 second. It adhered to the substrate to which the controller chip was attached.

4. 결과 평가4. Evaluation of results

본 발명에 따른 FOD 접착필름은 절단 등 공정이 진행될 때 불량이 없었다. The FOD adhesive film according to the present invention had no defects when processes such as cutting were in progress.

또한, 종래의 FOD 접착필름은 상기 FDO 접착필름에 다이싱 테이프를 합지하여 웨이퍼를 부착하고 함께 다이싱 하는 등 FOD 접착필름 상에 적층되는 반도체 다이를 별도로 관리할 필요가 있었다. 그러나, 본 발명에 따른 FOD 접착필름은 웨이퍼와 함께 다이싱할 필요가 없다. 이에 따라, 본 발명에 따른 반도체 패키지는 다이 어태치 필름이 부착된 웨이퍼만을 이용하여 제조할 수 있어 공정이 간단하고 수율이 향상되었다.In addition, in the conventional FOD adhesive film, it was necessary to separately manage a semiconductor die stacked on the FOD adhesive film, such as laminating a dicing tape on the FDO adhesive film, attaching a wafer and dicing together. However, the FOD adhesive film according to the present invention does not need to be diced together with the wafer. Accordingly, the semiconductor package according to the present invention can be manufactured using only a wafer to which a die attach film is attached, so that the process is simple and the yield is improved.

이상과 같이 본 발명에 대해 설명하였으나, 본 명세서에 개시된 실시예에 의해 본 발명이 한정되는 것은 아니며, 본 발명의 기술사상의 범위 내에서 통상의 기술자에 의해 다양한 변형이 이루어질 수 있음은 자명하다. 아울러 앞서 본 발명의 실시예를 설명하면서 본 발명의 구성에 따른 작용 효과를 명시적으로 기재하여 설명하지 않았을 지라도, 해당 구성에 의해 예측 가능한 효과 또한 인정되어야 함은 당연하다.Although the present invention has been described above, the present invention is not limited by the embodiments disclosed in the present specification, and it is apparent that various modifications may be made by a person skilled in the art within the scope of the technical idea of the present invention. In addition, even if not explicitly described and described the effects of the configuration of the present invention while describing the embodiments of the present invention, it is natural that the predictable effects of the configuration should also be recognized.

Claims (12)

접착층 및 상기 접착층의 일면에 서포트층이 적층된 적층구조;를 포함하는
FOD 접착필름.
Including; an adhesive layer and a laminated structure in which a support layer is stacked on one surface of the adhesive layer
FOD adhesive film.
 제1항에 있어서,
상기 접착층의 다른 일면에 적층된 이형필름;을 더 포함하는
FOD 접착필름.
The method of claim 1,
A release film laminated on the other side of the adhesive layer; further comprising
FOD adhesive film.
 제1항에 있어서,
상기 서포트층은
폴리이미드(polyimide, PI), 폴리이미드아미드(polyimideamide), 폴리에테르이미드(polyetherimide, PEI), 폴리에틸렌테레프탈레이트(polyethyleneterephtalate, PET), 폴리에틸렌나프탈레이트(polyethylenenaphthalate, PEN) 및 폴리에테르에테르케톤(polyetheretherketon, PEEK) 가운데 1종 이상의 재료를 포함하는
FOD 접착필름.
The method of claim 1,
The support layer is
Polyimide (PI), polyimideamide, polyetherimide (PEI), polyethyleneterephtalate (PET), polyethylenenaphthalate (PEN), and polyetheretherketon (PEEK) ) Containing at least one material
FOD adhesive film.
 제1항에 있어서,
상기 접착층은
아크릴 공중합체, 에폭시 수지 및 무기 필러를 포함하는
FOD 접착필름.
The method of claim 1,
The adhesive layer
Including acrylic copolymer, epoxy resin and inorganic filler
FOD adhesive film.
 제4항에 있어서,
상기 아크릴 공중합체는
유리전이온도 0℃ ~ 20℃ 및 중량평균분자량 100,000 ~ 500,000인 아크릴 공중합체를 포함하는
FOD 접착필름.
The method of claim 4,
The acrylic copolymer is
Including an acrylic copolymer having a glass transition temperature of 0℃ to 20℃ and a weight average molecular weight of 100,000 to 500,000
FOD adhesive film.
 제4항에 있어서,
상기 에폭시 수지는
비스페놀계 에폭시 수지, 바이페닐계 에폭시 수지, 나프탈렌계 에폭시 수지, 플로렌계 에폭시 수지, 페놀노볼락계 에폭시 수지, 크레졸노볼락계 에폭시 수지, 트리스하이드록 실페닐메탄계 에폭시 수지 및 테트라페닐메탄계 에폭시 수지 가운데 1종 이상을 포함하는
FOD 접착필름.
The method of claim 4,
The epoxy resin is
Bisphenol epoxy resin, biphenyl epoxy resin, naphthalene epoxy resin, florene epoxy resin, phenol novolak epoxy resin, cresol novolak epoxy resin, trishydroxylphenylmethane epoxy resin and tetraphenylmethane Containing at least one epoxy resin
FOD adhesive film.
 제4항에 있어서,
상기 에폭시 수지는
10℃ ~ 35℃에서 액상인 에폭시 수지; 및 10℃ ~ 35℃에서 고상인 에폭시 수지;를 포함하는 것을 특징으로 하는
FOD 접착필름.
The method of claim 4,
The epoxy resin is
Epoxy resin liquid at 10°C to 35°C; And an epoxy resin that is solid at 10° C. to 35° C.
FOD adhesive film.
 제1항에 있어서,
상기 접착층은 60~150㎛의 두께를 갖는
FOD 접착필름.
The method of claim 1,
The adhesive layer has a thickness of 60 ~ 150㎛
FOD adhesive film.
 제1항에 있어서,
상기 서포트층은 5~50㎛의 두께를 갖는
FOD 접착필름.
The method of claim 1,
The support layer has a thickness of 5-50㎛
FOD adhesive film.
 기판;
상기 기판 상부에 실장된 컨트롤러 다이;
상기 기판 상부에 형성된 FOD 접착필름; 및
상기 FOD 접착필름 상에 적층된 반도체 다이;를 포함하고,
상기 FOD 접착필름은 접착층 및 상기 접착층의 일면에 서포트층이 적층된 적층구조를 포함하고,
상기 컨트롤러 다이의 적어도 일부가 상기 접착층의 내부에 매립되어 있는
반도체 패키지.
Board;
A controller die mounted on the substrate;
An FOD adhesive film formed on the substrate; And
Including; a semiconductor die laminated on the FOD adhesive film,
The FOD adhesive film includes an adhesive layer and a laminated structure in which a support layer is laminated on one surface of the adhesive layer,
At least a portion of the controller die is embedded in the adhesive layer
Semiconductor package.
 제10항에 있어서,
상기 접착층 내 단수 또는 복수개의 수동소자; 단수 또는 복수개의 본딩패드; 및 단수 또는 복수개의 와이어;를 더 포함하는 것을 특징으로 하는 반도체 패키지.
The method of claim 10,
A single or a plurality of passive elements in the adhesive layer; Singular or plural bonding pads; And a single or a plurality of wires.
 제11항에 있어서,
상기 기판 및 실장된 컨트롤러 다이 상에 다이 어태치 필름을 포함하고,
상기 FOD 접착필름의 서포트층과 반도체 다이 사이에 다이 어태치 필름을 포함하는 것을 특징으로 하는 반도체 패키지.
The method of claim 11,
Including a die attach film on the substrate and the mounted controller die,
A semiconductor package comprising a die attach film between the support layer of the FOD adhesive film and the semiconductor die.
KR1020190078925A 2019-07-01 2019-07-01 Fod adhesive film and semiconductor package comprising thereof KR102240906B1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020190078925A KR102240906B1 (en) 2019-07-01 2019-07-01 Fod adhesive film and semiconductor package comprising thereof
SG10202006305VA SG10202006305VA (en) 2019-07-01 2020-06-30 FOD adhesive film and semiconductor package including the same
JP2020114245A JP7153690B2 (en) 2019-07-01 2020-07-01 FOD adhesive film and semiconductor package including the same
CN202010625963.6A CN112185905B (en) 2019-07-01 2020-07-01 Film-wrapped chip attach film and semiconductor package including the same
TW109122308A TWI825329B (en) 2019-07-01 2020-07-01 Fod adhesive film and semiconductor package comprising thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190078925A KR102240906B1 (en) 2019-07-01 2019-07-01 Fod adhesive film and semiconductor package comprising thereof

Publications (2)

Publication Number Publication Date
KR20210002976A true KR20210002976A (en) 2021-01-11
KR102240906B1 KR102240906B1 (en) 2021-04-15

Family

ID=74128946

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020190078925A KR102240906B1 (en) 2019-07-01 2019-07-01 Fod adhesive film and semiconductor package comprising thereof

Country Status (1)

Country Link
KR (1) KR102240906B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100860098B1 (en) * 2008-02-29 2008-09-26 주식회사 이녹스 Adhesive film for semiconductor package
KR100894173B1 (en) * 2008-03-31 2009-04-22 주식회사 이녹스 Mulitlayer adhesive film for semiconductor package
KR20180118777A (en) * 2016-03-31 2018-10-31 미쓰이 가가쿠 토세로 가부시키가이샤 Adhesive film for semiconductor device manufacturing and method of manufacturing semiconductor device
KR20180137128A (en) * 2017-06-16 2018-12-27 (주)이녹스첨단소재 FOD adhesive film of semiconductor controller embedding type and Semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100860098B1 (en) * 2008-02-29 2008-09-26 주식회사 이녹스 Adhesive film for semiconductor package
KR100894173B1 (en) * 2008-03-31 2009-04-22 주식회사 이녹스 Mulitlayer adhesive film for semiconductor package
KR20180118777A (en) * 2016-03-31 2018-10-31 미쓰이 가가쿠 토세로 가부시키가이샤 Adhesive film for semiconductor device manufacturing and method of manufacturing semiconductor device
KR20180137128A (en) * 2017-06-16 2018-12-27 (주)이녹스첨단소재 FOD adhesive film of semiconductor controller embedding type and Semiconductor package

Also Published As

Publication number Publication date
KR102240906B1 (en) 2021-04-15

Similar Documents

Publication Publication Date Title
KR101044584B1 (en) Laminated sheet
US8043698B2 (en) Method of producing a semiconductor device, and wafer-processing tape
KR101140512B1 (en) Thermosetting die bonding film
CN101848974B (en) Dicing die bonding film having excellent burr property and reliability and semiconductor device using same
JP5477144B2 (en) Adhesive sheet for connecting circuit members and method for manufacturing semiconductor device
KR101023844B1 (en) Adhesive resin composition, adhesive film, dicing die bonding film and semiconductor device using the same
KR101136599B1 (en) Adhesive composition, adhesive sheet for connecting circuit member, and method for manufacturing semiconductor device
KR101752992B1 (en) Adhesive agent composition, adhesive sheet, and method for manufacturing semiconductor device
KR101462845B1 (en) Composition for non-conductive film of having excellent flexibility and non-conductive film including the same
US11479699B2 (en) Adhesive film for semiconductor
KR102605475B1 (en) Composition for non-conductive film and non-conductive film including the same
KR102012788B1 (en) Adhesive film, preparation method of semiconductor device, and semiconductor device
TWI626292B (en) Composition for non-conductive adhesive film and non-conductive adhesive film including the same
KR101936593B1 (en) FOD adhesive film of semiconductor controller embedding type and Semiconductor package
US8802776B2 (en) Epoxy resin composition, method for producing composite unit using the epoxy resin composition, and composite unit
CN104726032A (en) Adhesive film, dicing/die-bonding film, method for manufacturing semiconductor device, and semiconductor device
JP5691244B2 (en) Film adhesive, adhesive sheet and semiconductor device
KR101435758B1 (en) Composition for non-conductive film and non-conductive film including the same
KR102305022B1 (en) Fod adhesive film and semiconductor package comprising thereof
KR102240906B1 (en) Fod adhesive film and semiconductor package comprising thereof
KR102240909B1 (en) Fod adhesive film and semiconductor package comprising thereof
KR101751972B1 (en) FOD adhesive film of semiconductor controller embedding type and Semiconductor package
KR101435613B1 (en) Composition for non-conductive film of having excellent light transmittance and non-conductive film including the same
KR102228539B1 (en) Adhesive composition for semiconductor circuit connection and adhesive film containing the same
JP7153690B2 (en) FOD adhesive film and semiconductor package including the same

Legal Events

Date Code Title Description
E701 Decision to grant or registration of patent right