KR20180008442A - Method of forming fence conductor using spacer etched trenches - Google Patents

Method of forming fence conductor using spacer etched trenches Download PDF

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KR20180008442A
KR20180008442A KR1020177031585A KR20177031585A KR20180008442A KR 20180008442 A KR20180008442 A KR 20180008442A KR 1020177031585 A KR1020177031585 A KR 1020177031585A KR 20177031585 A KR20177031585 A KR 20177031585A KR 20180008442 A KR20180008442 A KR 20180008442A
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dielectric
trench
depositing
sacrificial thin
conductive material
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KR1020177031585A
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Korean (ko)
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폴 페스트
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마이크로칩 테크놀로지 인코포레이티드
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Priority claimed from US14/714,475 external-priority patent/US9583435B2/en
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Publication of KR20180008442A publication Critical patent/KR20180008442A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The spacer etch process produces very narrow conductive lines of a plurality of semiconductor dies. Trenches are formed in the first dielectric and then the sacrificial film is deposited on the first dielectric and the trench surfaces formed therein. The flat sacrificial thin film is removed from the bottom of the first dielectric surface and trenches, leaving only the sacrificial thin film only on the trench walls. The gap between the sacrificial thin films on the trench walls is filled with the second dielectric. A portion of the second dielectric is removed to expose portions of the sacrificial thin film. The sacrificial thin film is removed leaving ultra-fine gaps filled with conductive material. The upper portions of the conductive material in the gaps are exposed to form "fence conductors ". Portions of the fence conductors and the insulating material surrounding them are removed at appropriate locations to form the desired conductor patterns including the insulated fence conductors.

Description

Method of forming fence conductor using spacer etched trenches

This application is a continuation-in-part of U.S. Patent Application No. 13 / 836,647, filed March 15, 2013, the entire content of which is incorporated herein by reference in its entirety.

The present disclosure relates to the manufacture of semiconductor integrated circuits (ICs), and more particularly to forming sub-lithographic patterns of conductive lines in a semiconductor die (e.g., an integrated circuit die) during fabrication of the semiconductor integrated circuit .

Reduction of the size of patterned conductive lines used to interconnect active elements, e.g., transistors, in a semiconductor die has been limited by available lithographic processes. Since the number of transistors has been increased in semiconductor dies resulting from improvements in lithographic masking processes that form these transistors, the conductive lines that must interconnect the transistors of these sizes are reduced in proportion to these smaller transistors The size could not be reduced.

Therefore, there is a need for a method for reducing the size of patterned conductive lines without being limited by the lithographic processes available for manufacturing semiconductor integrated circuits.

According to one embodiment, a method of forming fence conductors in a semiconductor integrated circuit die comprises depositing a first dielectric on a surface of a semiconductor substrate; Creating at least one trench in the first dielectric; Depositing a sacrificial film on a first dielectric comprising walls and bottoms of the at least one trench; Removing portions of the sacrificial thin film from a surface of the first dielectric and the bottom of the at least one trench wherein the sacrificial thin films remain only in the walls of the at least one trench; Depositing a second dielectric between the sacrificial thin films on the walls of the at least one trench; Removing the first dielectric and the second dielectric until the top portions of the sacrificial thin film can be exposed between the first dielectric and the second dielectric; Removing the sacrificial thin films between the first dielectric and the second dielectric by leaving at least two narrow channels between the first dielectric and the second dielectric; Depositing a conductive material on the first dielectric and second dielectric surfaces and into the at least two narrow channels; And removing portions of the conductive material on the surfaces of the first and second dielectrics until only the tops of the conductive material can be exposed in the at least two narrow channels. have.

According to a further embodiment of the method, after removing the portions of the conductive material on the faces of the first and second dielectrics, portions of the conductive material in the at least two narrow channels are separated into independent fence conductors And a step of dividing. According to a further embodiment of the method, after removing the portions of the sacrificial thin film from the surface of the first dielectric and the bottom of the at least one trench, the sacrificial thin film is removed from portions of the walls of the at least one trench, And removing the thin film.

According to a further embodiment of the method, the step of depositing the first dielectric may be performed on the surface of the semiconductor substrate at a thickness of from about 1 nanometer to about 2000 nanometers, for example, from about 1 nanometer to about 100 nanometers And depositing the first dielectric. According to a further embodiment of the method, the step of creating the at least one trench comprises implanting the first dielectric at a depth of from about 1 nanometer to about 2000 nanometers, for example, from about 1 nanometer to about 100 nanometers, And creating at least one trench. According to a further embodiment of the method, the step of creating the at least one trench comprises providing the first dielectric with a width of from about 1 nanometer to about 2000 nanometers, e.g., from about 1 nanometer to about 100 nanometers And creating the at least one trench. According to a further embodiment of the method, the step of depositing the sacrificial thin film comprises depositing the sacrificial thin film to a thickness of from about 1 nanometer to about 2000 nanometers, for example, from about 1 nanometer to about 100 nanometers . According to a further embodiment of the method, the step of depositing the second dielectric comprises depositing the second dielectric to a thickness of from about 1 nanometer to about 2000 nanometers, for example, from about 1 nanometer to about 100 nanometers .

According to a further embodiment of the method, the sacrificial thin film may be selected from the group consisting of SiN, SiO 2 and SiO x N y . According to a further embodiment of the method, the conductive material may be selected from the group consisting of Al, Ag, Au, Fe, Ta, TaN, Ti and TiN. According to a further embodiment of the method, the conductive material comprises copper (Cu).

According to a further embodiment of the method, depositing a barrier layer on the at least one narrow channel may be prior to depositing a conductive material in the channel. According to a further embodiment of the method, dividing the portions of the conductive material may include dividing portions of the conductive material by reactive-ion etching (RIE). According to a further embodiment of the method, the RIE may be aggressive. According to a further embodiment of the method, it may comprise filling the gaps produced by the RIE with a dielectric and chemically-mechanically planarizing (CMP) polishing it.

According to another embodiment, a semiconductor die comprises a semiconductor substrate; A first dielectric on the surface of the semiconductor substrate; At least one trench in the first dielectric; At least two narrow channels in the at least one trench formed by the walls of the at least one trench and the sacrificial thin films on the second dielectric wherein the second dielectric is between the sacrificial thin films on the walls of the at least one trench Wherein the sacrificial thin films are removed to form the at least two narrow channels; And a conductive material filling the at least two narrow channels, wherein the conductive material within the at least two narrow channels may be used as fence conductors that are divided to connect the active elements of the semiconductor die.

According to a further embodiment, a plurality of fence conductors can be made by dividing the conductive material in the at least two narrow channels into desired lengths. According to a further embodiment, the first dielectric may have a thickness of from about 1 nanometer to about 2000 nanometers, for example, from about 1 nanometer to about 100 nanometers. According to a further embodiment, the at least one trench may have a depth of from about 1 nanometer to about 2000 nanometers, for example, from about 1 nanometer to about 100 nanometers, from about 1 nanometer to about 2000 nanometers, For example, from about 1 nanometer to about 100 nanometers in width. According to a further embodiment, the sacrificial thin film has a thickness of from about 1 nanometer to about 2000 nanometers, for example, from about 1 nanometer to about 100 nanometers. According to a further embodiment, the second dielectric may have a thickness of from about 1 nanometer to about 2000 nanometers, for example, from about 1 nanometer to about 100 nanometers. According to a further embodiment, there may be a barrier layer between the walls of the at least one narrow channel and the conductive material. According to a further embodiment, the conductive material may be copper.

A more complete understanding of the present disclosure may be achieved by reference to the following description taken together with the accompanying drawings.
Figure 1 shows a schematic plan view of a semiconductor integrated circuit wafer comprising a plurality of semiconductor dies;
Figures 2, 3, 3a and 3b show schematic front views of semiconductor fabrication steps for forming sub-lithographic patterns of conductive lines in a semiconductor die, in accordance with certain exemplary embodiments of this disclosure;
Figure 4 shows a schematic plan view of a plurality of sub-lithographic patterns of conductive lines formed in a semiconductor die, in accordance with certain illustrative embodiments of this disclosure;
Figure 5 shows a schematic plan view of a plurality of sub-lithographic patterns of conductive lines formed in a semiconductor die, in accordance with certain illustrative embodiments of this disclosure;
Figure 6 shows a schematic plan view of a plurality of sub-lithographic patterns of the conductive lines shown in Figure 5, prepared for separating conductive lines from each other, according to a specific exemplary embodiment of this disclosure;
Figure 7 is a schematic representation of a plurality of sub-lithographic patterns of conductive lines shown in Figures 5 and 6, in which portions of the conductive lines are removed to separate the conductive lines from each other, according to a particular exemplary embodiment of this disclosure. FIG.
Figure 8 shows a schematic plan view of a plurality of sub-lithographic patterns of conductive lines having various routing paths formed in a semiconductor die, in accordance with another particular exemplary embodiment of this disclosure;
FIG. 9 is a schematic diagram of a plurality of sub-lithographic elements of conductive lines having various routing paths, as shown in FIG. 8, prepared for division into semiconductor conductors of a semiconductor die, according to another particular exemplary embodiment of this disclosure. ≪ / RTI > shows a schematic top view of the graphic patterns;
Figure 10 is a schematic diagram of a semiconductor die having a plurality of sub-lithographs of conductive lines having various routing paths as shown in Figures 8 and 9, after being divided into discrete conductors of a semiconductor die, according to another particular exemplary embodiment of this disclosure. ≪ / RTI > showing a schematic top view of the patterns;
Figure 11 shows a schematic process flow diagram for forming a plurality of sub-lithographic patterns of conductive lines of a semiconductor die, in accordance with certain exemplary embodiments of this disclosure;
Figure 12 shows a schematic process flow diagram for forming a plurality of sub-lithographic patterns of conductive lines of a semiconductor die, in accordance with certain other exemplary embodiments of this disclosure.
While the present disclosure may be susceptible to various modifications and alternative forms, specific illustrative embodiments thereof have been shown in the drawings and are described in detail herein. It should be understood, however, that the description herein of specific exemplary embodiments is not intended to be limited to the specific configurations disclosed herein, on the contrary, the intention is to cover all modifications and equivalents as defined by the appended claims, do.

According to the teachings of this disclosure, a spacer etching process can be used to fabricate at least one trench of a first dielectric deposited on a face of a semiconductor die. A sacrificial thin film is then deposited to a desired thickness on the side of the first dielectric including walls and bottoms of at least one trench. The sacrificial thin film is then removed from the surface of the first dielectric and the bottom of the at least one trench leaving the sacrificial thin film only on the walls of at least one trench. This can be obtained by etching the sacrificial thin film from the surface of the first dielectric and the bottom surface of the at least one trench, for example but not limited thereto. During the aforementioned steps in which a gap fill step can cause breaks in the conductors, selected portions of the sacrificial thin film may also optionally be "broken", for example, removed. Next, a second dielectric is deposited over the surface of the first dielectric and over the sacrificial thin film on the walls of the trenches, wherein a gap between the sacrificial thin films on the walls of the at least one trench, . The second dielectric is then removed by polishing until the tops of the sacrificial thin films on the walls of the at least one trench, for example, but not limited to, are again exposed.

Subsequently, the dielectric material is removed from the very narrow channels remaining between the first dielectric walls and the second dielectric walls formed from previous process steps, effectively removing the sacrificial thin film entirely, If the dip-out process has good selectivity, the sacrificial thin film may be removed by dip-out, for example, but not exclusively. However, the slight etch of the dielectric material can round the top corners of these ultra-narrow channels that can improve the filling of the dielectric material. Next, the conductive material fills these ultra-narrow channels to create extremely thin fence conductors. The surface of the dielectric and the top of the microfine conductors can then be planarized by a chemical-mechanical planarization (CMP) process, for example, but not limited thereto.

This sub-lithographic patterning of the conductive lines can be fabricated in a manufacturing process that is compatible with conventional aluminum and copper backend processing. Some of the fence conductors and the insulating material surrounding them may be removed (e.g., "broken") at locations suitable for producing the desired conductor patterns comprising the fence conductors. The trench depth helps to determine one dimension of the fence conductors, for example conductor height, and the thickness of the deposited sacrificial thin film determines the second dimension, for example conductor width. The length of the fence conductors is determined by where the continuous fence conductors are "broken", eg, separated from each other and disconnection between the fence conductors.

Referring now to the drawings, there is shown schematically the details of certain exemplary embodiments. In the drawings, the same elements are denoted by the same reference numerals, and the similar elements are denoted by the same reference numerals with different subscripts.

Referring to Figure 1, a schematic plan view of a semiconductor integrated circuit wafer including a plurality of semiconductor dies is shown. The silicon wafer 102 may be scribed into a plurality of semiconductor dice 104 for further processing to create planar transistors, diodes, and conductors on each of the plurality of semiconductor dice 104. [ After all of the circuits have been fabricated on the plurality of semiconductor dies 104, the dies 104 are singulated (partitioned) and packaged into integrated circuits (not shown).

Referring to Figures 2,3A and 3B, schematic front views of semiconductor fabrication steps for forming sub-lithographic patterns of conductive lines in a semiconductor die are shown, in accordance with certain exemplary embodiments of this disclosure . The first step (a) of forming the fence conductors is shown in Figure 2 wherein the first dielectric 212 can be deposited on the surface of the semiconductor substrate 210 for each of the plurality of semiconductor dies 104 have. In the next step (b). The first dielectric 212 may have at least one trench 214 etched therein to a depth that helps determine one dimension, e. G., Depth, of the desired fence conductors. At least one trench 214 includes walls 216 and a bottom. In step (c), the sacrificial thin film 222 may be deposited over the exposed surfaces of the first dielectric 212 and the at least one trench 214. In step (d), the sacrificial thin film 222 is formed by leaving the sacrificial thin films 222a only on the walls 216 of the at least one trench 214 and leaving the sacrificial thin films 222a on the top surface of the first dielectric 212, May be selectively etched from the bottom of one trench (214). Rounding of the tops of the sacrificial thin films 222a may be performed during the etching process.

In step (e), the gap between the sacrificial thin films 222a over the exposed surfaces of the first dielectric 212 and the sacrificial thin films 222a on the vertical walls 116 of the at least one trench 214 The second dielectric 212a can be deposited thick enough to be charged. In step (f), a portion of the second dielectric 212a may be removed deep enough to be able to remove, for example, go past past the rounded tops of the sacrificial thin films 222a, And if not, there may be a re-entrant shape which can be very difficult to charge. In step (g), the sacrificial film 222a is removed from the first dielectric 212 and the second dielectric 212a by, for example, but not limited to, dip-out etching. Thereby leaving ultra-thin channels therein, for example trenches, furrows or grooves therein. The deep-out etch can also round off the top edges of these ultra-narrow channels that can improve internal fill material. At step (h), the conductive material 218 may be deposited on the first dielectric 212 and the second dielectric 212a to a thickness sufficient to fill these microfine channels. In step (i), the deposited conductive material 218 is removed from the top surfaces of the first dielectric 212 and the second dielectric 212a to expose the tops of the microfine conductors 218a have. The depth of the trenches 214 can determine the height of the fence conductors 218a and the thickness of the deposited sacrificial thin film 222 can determine the thickness of the fence conductors 218a.

The conductive material 218 is a metal, a metal alloy, and a non-metallic material suitable for the conductive fences disclosed herein, as is well known to those of ordinary skill in the semiconductor integrated circuit fabrication arts and those of ordinary skill in the art having the benefit of this disclosure May be selected from many different types of conductive materials including conductive compounds.

When copper is used as the conductive material 218b (FIG. 3B), the barrier layer 220 may be used between the surfaces of the copper material 218b and the first dielectric 212 and the second dielectric 212a Because the copper atoms can diffuse into the materials surrounding them and thereby degrade their properties. Thus, the barrier layer 220 (FIG. 3B) of step h1 may be removed from the exposed surfaces of the first dielectric 212 and the second dielectric 212a before the copper conductive material 218a is deposited at step h2 Lt; / RTI >

A first dielectric layer 212 is, for example, SiN, SiO 2, SiO x N y Etc. However, the present invention is not limited thereto. A second dielectric layer (212a) is, for example, or the like can be SiN, SiO 2, SiO x N y, but it is not limited thereto. The sacrificial thin film 222 may be, for example, SiN, SiO 2 , SiO x N y or the like, but is not limited thereto. The conductive material 218 may be, for example, Al, Ag, Au, Fe, Ta, TaN, Ti, TiN, Cu, or the like, but is not limited thereto. The barrier layer 220 may be, for example, Ta, TaN, or the like, but is not limited thereto. The various layers or films of the structure may be formed by any suitable technique of growing, coating, or otherwise transferring the material onto a wafer or stack, particularly physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and atomic layer deposition (ALD) Or any other suitable technique (s), such as < / RTI >

The thickness of the first dielectric layer 212 may be from about 1 nanometer to about 2000 nanometers. In certain embodiments, when atomic layer deposition (ALD), for example, is used to form the related layers / films of the structure, the thickness of the first dielectric layer 212 may range from about 1 nanometer to about 100 nanometers Lt; / RTI >

The thickness of the second dielectric layer 212a may be from about 1 nanometer to about 2000 nanometers. In certain embodiments, for example, if the related layers / films of the structure are formed by ALD, the thickness of the second dielectric layer 212a may be from about 1 nanometer to about 100 nanometers.

The thickness of the sacrificial thin film 222 may be from about 1 nanometer to about 2000 nanometers. In certain embodiments, for example, when the related layers / thin films of the structure are formed by the ALD method, the thickness of the sacrificial thin film 222 may be from about 1 nanometer to about 100 nanometers.

The thickness of barrier layer 220 may be from about 1 nanometer to about 100 nanometers. In certain embodiments, for example, when the related layers / thin films of the structure are formed by ALD, the thickness of the barrier layer 220 may be from about 1 nanometer to about 5 nanometers.

The depth of the at least one trench 214 may be from about 1 nanometer to about 2000 nanometers. In certain embodiments, the depth of the at least one trench 214 may be from about 1 nanometer to about 100 nanometers, for example when the related layers / thin films of the structure are formed by the ALD method. The width of the at least one trench 214 may be from about 1 nanometer to about 2000 nanometers. In certain embodiments, the width of the at least one trench 214 may be from about 1 nanometer to about 100 nanometers, for example when the related layers / thin films of the structure are formed by the ALD method. In some embodiments, the at least one trench 214 has a depth of about 1 nanometer to about 100 nanometers and a width of about 1 nanometer to about 100 nanometers.

The width or thickness of the fence conductors 218a may be from about 1 nanometer to about 1000 nanometers. In certain embodiments, the width or thickness of the fence conductors 218a may be from about 1 nanometer to about 10 nanometers, for example, where the related layers / thin films of the structure are formed by the ALD process.

Referring to Figures 4 and 5, there are shown schematic top views of a plurality of sub-lithographic patterns of conductive lines formed in a semiconductor die, in accordance with certain exemplary embodiments of this disclosure. After the continuous conductive material 218 has been removed to the point where the top of the fence conductors 218a is exposed as shown in Figures 3a and 3b step (i), the fence conductors 218a are removed for further processing Ready. The fence conductors 218a may be divided to produce useful independent circuit conductors. The plurality of fence conductors 218a shown in Figure 5 may represent conductors used in a semiconductor transistor array.

Referring to FIG. 6, a schematic top view of a plurality of sub-lithographic patterns of conductive lines shown in FIG. 5 is shown, which is prepared for dividing the conductive lines from one another, according to a particular exemplary embodiment of this disclosure. The ends of the fence conductors 218a, designated 620, may be broken, e.g., split apart, and cut between the ends of the fence conductors. The ends 620 may be routed to the "safe" area on the die 104 and may be routed to a " secure " area by a removal process, such as, but not limited to, aggressive reactive ion etch (RIE) where the ends 620 are exposed and the remainder of the plurality of fence conductors 218a is protected from RIE, for example masked.

Referring to Figure 7, a schematic top view of a plurality of sub-lithographic patterns is shown in which portions of the conductive lines have been removed to separate the conductive lines from each other, in accordance with certain exemplary embodiments of this disclosure. After the ends 620 have been removed, a third dielectric fill (not shown) may be needed to fill the gaps created by the RIE process. Once this third dielectric filler is completed, a chemical-mechanical planarization (CMP) process may be performed on the face of the die 104. The RIE mask may also be performed to selectively break the fence conductor 218a at any location on the die 104. [

Referring to Figure 8, a schematic plan view of a plurality of sub-lithographic patterns of conductive lines having various routing paths formed in a semiconductor die, according to another particular exemplary embodiment of this disclosure, Respectively. The illustrated fence conductor 218a has been described in greater detail above. It can be noted that the fence conductors 820 can be routed to as many different paths as desired and can be configured as active elements, e. G., Conductors between the transistors, on the semiconductor die 104, Are within the scope of this disclosure. The steps for making the trenches of this pattern and creating the fence conductors 820 may be performed using appropriate masks (not shown) and the processes shown in Figures 2,3, and 3a and in the accompanying detailed description thereof, May be performed through the same or similar processes as the steps.

9, a plurality of sub-lines of conductive lines having various routing paths, as shown in FIG. 8, prepared for segmenting into discrete conductors of a semiconductor die, in accordance with another particular exemplary embodiment of this disclosure, A schematic top view of lithographic patterns is shown. The fence conductors 820 may be disconnected, for example, between fence conductors, at various locations on the semiconductor die 104, generally indicated at 822. These split locations 822 can be obtained using conventional Via type processes as is well known to those of ordinary skill in the semiconductor manufacturing arts and those of ordinary skill in the art having the benefit of this disclosure.

Referring to Figure 10, a plurality of conductive lines having various routing paths as shown in Figures 8 and 9, after being divided into discrete conductors of a semiconductor die, in accordance with another particular exemplary embodiment of this disclosure A schematic top view of the sub-lithographic patterns is shown. The via style fence separations can be filled with another dielectric process deposition and then the fully divided fence conductors 1020 can be filled in the semiconductor die 104 with the active element For example, transistors, and other connection nodes (not shown).

Referring to Figure 11, a schematic process flow diagram for forming conductive lines of a plurality of sub-lithographic patterns on a semiconductor die is disclosed, in accordance with certain exemplary embodiments of this disclosure. In step 1102, the first dielectric 212 may be deposited on the face of a semiconductor substrate (die) 210. At step 1104, at least one trench 214 may be etched into the dielectric 212. At step 1106, a sacrificial thin film 222 may be deposited to a desired thickness on the first dielectric 212 and the walls and on the bottom of at least one trench 214. At step 1108, the sacrificial thin film 222 may be selectively etched from the top of the first dielectric 212 and the bottom of the at least one trench 214.

In step 1110, a second dielectric 212a is deposited over the first dielectric 212 and the remaining sacrificial thin film 222 on the walls to fill the gaps between the walls of the at least one trench 214 . In step 1112, a portion of the second dielectric 212a may be removed, e.g., polished off, until the tops of the sacrificial films 222 are exposed. In step 1114, the sacrificial thin films 222 are removed, thereby leaving at least two narrow channels between the vertical portions of the first dielectric 212 and the second dielectric 212a. At step 1116, the conductive material 218 may be deposited on the faces of the first dielectric and second dielectric and in at least two narrow channels. In step 1118, the conductivity of the first dielectric 212 and the second dielectric 212a on the top surface of the first dielectric 212 and the second dielectric 212a, until only the tops of the remaining conductive material 218a are exposed in the at least two narrow channels. A portion of the material 218 may be removed. In step 1120, to make the independent fence conductors 1020 that can be used to interconnect the active devices (not shown) in the semiconductor die 104, portions of the conductive material 218a may be partitioned, Can be achieved.

Referring to Figure 12, a schematic process flow diagram for forming conductive lines of a plurality of sub-lithographic patterns on a semiconductor die is shown, in accordance with certain other exemplary embodiments of this disclosure. In step 1102, the first dielectric 212 may be deposited on the side of the semiconductor substrate (die) 210. At step 1104, at least one trench 214 may be etched into the dielectric 212. At step 1106, a sacrificial thin film 222 may be deposited to a desired thickness on the first dielectric 212 and the walls and on the bottom of at least one trench 214. In step 1108, the sacrificial thin film 222 may be selectively etched from the top of the first dielectric 212 and from the bottom of the at least one trench 214. In step 1209, the sacrificial thin film may be removed from portions of the walls of at least one trench. Step 1209 may effectively remove step 1120 of FIG. 11 to form an independent fence conductor 1020 that may be used to interconnect active devices (not shown) in the semiconductor die 104.

At step 1110 a second dielectric 212a may be deposited over the first dielectric 212 and the remaining sacrificial thin film 222 on the walls to fill the gaps between the walls of the at least one trench 214. [ In step 1112, a portion of the second dielectric 212a may be removed, e.g., polished, until the tops of the sacrificial films 222 are exposed. At step 1114, the sacrificial thin film 222 is removed, thereby leaving at least two narrow channels between the vertical portions of the first and second dielectrics 212 and 212a. At step 1116, the conductive material 218 may be deposited on the faces of the first dielectric and second dielectric and in at least two narrow channels. A portion of the conductive material 218 on the faces of the first dielectric 212 and the second dielectric 212a may be formed such that only the tops of the remaining conductive material 218a are at least two Can be removed until it is exposed in narrow channels.

While the embodiments of this disclosure are shown, described, and defined with reference to the exemplary embodiments of this disclosure, these descriptions are not meant to imply a limitation on this disclosure, nor will such limitations be implied. The disclosed subject matter is susceptible to many modifications, alterations, and equivalents in form and function, as would occur to those of ordinary skill in the art and to those of ordinary skill in the art to which this disclosure pertains. The illustrated and described embodiments of this disclosure are illustrative only and are not intended to be exhaustive of the scope of the disclosure.

Claims (20)

A method of forming femto conductors in a semiconductor integrated circuit die,
Depositing a first dielectric on the side of the semiconductor substrate;
Creating at least one trench in the first dielectric;
Depositing a sacrificial film on the first dielectric comprising walls and bottoms of the at least one trench;
Removing portions of the sacrificial thin film from a surface of the first dielectric and the bottom of the at least one trench, wherein the sacrificial thin films remain only on the walls of the at least one trench (on);
Depositing a second dielectric between the sacrificial thin films on the walls of the at least one trench;
Removing the first and second dielectrics until the top portions of the sacrificial film are exposed between the first dielectric and the second dielectric;
Removing the sacrificial thin films between the first dielectric and the second dielectric by leaving at least two narrow channels between the first dielectric and the second dielectric;
Depositing a conductive material on the first dielectric and second dielectric surfaces and into at least two narrow channels; And
Removing portions of the conductive material on the sides of the first and second dielectrics until only the tops of the conductive material can be exposed in the at least two narrow channels. The method according to claim 1,
Further comprising dividing portions of the conductive material within the at least two narrow channels into independent fence conductors after removing portions of the conductive material on the sides of the first and second dielectrics. A method of forming fence conductors in an integrated circuit die. 3. The method according to claim 1 or 2,
Further comprising removing the sacrificial thin film from portions of the walls of the at least one trench after removing the portions of the sacrificial thin film from the first dielectric surface and the bottom of the at least one trench A method of forming fence conductors in a semiconductor integrated circuit die. 4. The method according to any one of claims 1 to 3,
Wherein depositing the first dielectric comprises depositing the first dielectric to a thickness of about 1 nanometer to about 2000 nanometers on the side of the semiconductor substrate to form fence conductors on the semiconductor integrated circuit die Way. 5. The method according to any one of claims 1 to 4,
Wherein depositing the first dielectric comprises depositing the first dielectric to a thickness of from about 1 nanometer to about 100 nanometers on the side of the semiconductor substrate to form fence conductors on the semiconductor integrated circuit die Way. 6. The method according to any one of claims 1 to 5,
Wherein the step of creating the at least one trench comprises forming the at least one trench at a depth of from about 1 nanometer to about 2000 nanometers in the first dielectric to form fence conductors in a semiconductor integrated circuit die Way. 7. The method according to any one of claims 1 to 6,
Wherein generating the at least one trench comprises forming the at least one trench at a depth of from about 1 nanometer to about 100 nanometers in the first dielectric material to form fence conductors in the semiconductor integrated circuit die Way. 8. The method according to any one of claims 1 to 7,
Wherein the step of creating the at least one trench comprises forming the at least one trench having a width of from about 1 nanometer to about 2000 nanometers in the first dielectric to form fence conductors in the semiconductor integrated circuit die How to. 9. The method according to any one of claims 1 to 8,
Wherein the step of creating the at least one trench comprises forming the at least one trench having a width of about 1 nanometer to about 100 nanometers in the first dielectric, How to. 10. The method according to any one of claims 1 to 9,
Wherein depositing the sacrificial thin film comprises depositing the sacrificial thin film to a thickness of from about 1 nanometer to about 2000 nanometers. 11. The method according to any one of claims 1 to 10,
Wherein depositing the sacrificial thin film comprises depositing the sacrificial thin film to a thickness of between about 1 nanometer and about 100 nanometers. 12. The method according to any one of claims 1 to 11,
Wherein depositing the second dielectric comprises depositing the second dielectric to a thickness between about 1 nanometer and about 2000 nanometers. ≪ Desc / Clms Page number 21 > 13. The method according to any one of claims 1 to 12,
Wherein depositing the second dielectric comprises depositing the second dielectric to a thickness between about 1 nanometer and about 100 nanometers. ≪ Desc / Clms Page number 21 > 14. The method according to any one of claims 1 to 13,
Depositing at least one of the first dielectric, the second dielectric, or the sacrificial thin film using an atomic layer deposition (ALD) process to form the fence conductors. 15. The method according to any one of claims 1 to 14,
Wherein the sacrificial thin film is selected from the group consisting of SiN, SiO 2, and SiO x N y . 16. The method according to any one of claims 1 to 15,
Wherein the conductive material is selected from the group consisting of Al, Ag, Au, Fe, Ta, TaN, Ti and TiN. 17. The method according to any one of claims 1 to 16,
Further comprising depositing a barrier layer on the at least one narrow channel prior to depositing the conductive material in the at least one narrow channel. 18. The method according to any one of claims 1 to 17,
Wherein dividing the portions of the conductive material comprises dividing portions of the conductive material by reactive-ion etching (RIE). 19. The method of claim 18,
Further comprising filling the gaps produced by the RIE with a dielectric and chemically-mechanically planarizing (CMP) polishing the surface. A semiconductor substrate;
A first dielectric on the surface of the semiconductor substrate;
At least one trench in the first dielectric;
At least two narrow channels in the at least one trench formed by the walls of the at least one trench and the sacrificial thin films on the second dielectric wherein the second dielectric is between the sacrificial thin films on the walls of the at least one trench Thereby removing the sacrificial thin films to form the at least two narrow channels; And
And a conductive material filling the at least two narrow channels, wherein the conductive material in the at least two narrow channels is divided to be used as fence conductors connecting the active elements of the semiconductor die.
KR1020177031585A 2015-05-18 2016-05-11 Method of forming fence conductor using spacer etched trenches KR20180008442A (en)

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US14/714,475 2015-05-18
US14/714,475 US9583435B2 (en) 2013-03-15 2015-05-18 Forming fence conductors using spacer etched trenches
PCT/US2016/031741 WO2016186912A1 (en) 2015-05-18 2016-05-11 Forming fence conductors using spacer etched trenches

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US5618383A (en) * 1994-03-30 1997-04-08 Texas Instruments Incorporated Narrow lateral dimensioned microelectronic structures and method of forming the same
US20090124084A1 (en) * 2007-11-14 2009-05-14 Elliot Tan Fabrication of sub-resolution features for an integrated circuit
US9034758B2 (en) * 2013-03-15 2015-05-19 Microchip Technology Incorporated Forming fence conductors using spacer etched trenches
US9385043B2 (en) * 2013-03-15 2016-07-05 Microchip Technology Incorporated Spacer enabled poly gate

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