KR20170085229A - 4k UHD ENCODING APPRATUS USING PLURALITY OF FPGA - Google Patents

4k UHD ENCODING APPRATUS USING PLURALITY OF FPGA Download PDF

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KR20170085229A
KR20170085229A KR1020160004579A KR20160004579A KR20170085229A KR 20170085229 A KR20170085229 A KR 20170085229A KR 1020160004579 A KR1020160004579 A KR 1020160004579A KR 20160004579 A KR20160004579 A KR 20160004579A KR 20170085229 A KR20170085229 A KR 20170085229A
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signal
video
hevc
uhd
pcie
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KR1020160004579A
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Korean (ko)
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KR101793971B1 (en
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양영한
강일석
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(주)캐스트윈
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/242—Synchronization processes, e.g. processing of PCR [Program Clock References]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4307—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

The present invention relates to a 4k UHD encoding apparatus using a plurality of FPGAs, and more particularly to a 4k UHD encoding apparatus using a plurality of FPGAs, which corrects errors of a video signal and an audio signal of a UHD (Ultra High Definition) video source, converts the video signal into four deserializing digital signals A 4k input processor for converting the audio signal into a deserializing digital signal; A first HEVC processor for receiving the first video signal and the audio signal of the converted video signal and converting the first video signal and the audio signal into a PCIe signal; Second, third and fourth HEVC processors respectively receiving the second, third, and fourth video signals of the converted video signal and converting the second, third, and fourth video signals, respectively, into a PCIe signal; A PCIe switch for receiving the first, second, third, and fourth video signals converted into the PCIe signal and the audio signal; A first codec FPGA for receiving a first video signal converted from the PCIe switch into the PCIe signal, compressing and encoding the first video signal into an HEVC format, and compressing and encoding the audio signal received from the PCIe switch; And a second, third, and fourth codec FPGAs, respectively, for receiving second, third, and fourth video signals converted from the PCIe switch to the PCIe signal and compressively encoding the second, third, and fourth video signals, respectively, in an HEVC format, The first, second, third, and fourth video signals compressively encoded in the first, second, third, and fourth codec FPGAs, and the audio signal compression-encoded in the first codec FPGA through a PCIe switch, And processes and packetizes the HEVC compressed image in the 4k UHD format.

Figure P1020160004579

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a 4 k UHD encoding apparatus using a plurality of FPGAs,

An embodiment of the present invention relates to a 4k UHD encoding apparatus using a plurality of FPGAs.

BACKGROUND ART [0002] With the development of broadcasting technology, conventional analog broadcasting is stopped, and the conversion and dissemination of digital broadcasting, which has excellent broadcasting quality and can transmit various information together, is rapidly progressing. In recent years, UHD (Ultra High Definition) digital broadcasting has started trial broadcasting.

On the other hand, broadcasting equipment such as an encoder and a transcoder plays a very important role in providing a digital data transmission stream required for UHD (Ultra High Definition) digital broadcasting.

Therefore, high efficiency video coding (HEVC) technology approved by ITU-T as H.265 standard is actively under development, and HEVC provides more than 2 times compression performance with less loss.

Accordingly, the HEVC technology has been proposed through various documents such as the HEVC lossless level coding method and apparatus of Korean Patent Laid-Open Publication No. 2014-0056600, the HEVC coding apparatus and the coding method using the HEVC lossless level coding apparatus and the Korean Laid-Open Patent Application No. 2015-0027530 .

However, conventionally, due to the high capacity of video data and the complexity of the codec, it is not possible to process digital broadcasting contents in a compression format as well as uncompressed format in one HEVC transcoder, and its input and output can be variously formatted including DVB- And it has a problem that it can not efficiently encode 4k UHD (Ultra High Definition) contents.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the above-described problems, and it is an object of the present invention to provide a method and apparatus for encoding 4k UHD (Ultra High Definition) contents into HEVC format using a plurality of FPGAs, and outputting both DVB- To provide UHD digital broadcasting suitable for digital TV and IP communication environment.

A 4k UHD encoding apparatus using a plurality of FPGAs according to this embodiment for correcting the above problems corrects errors of a video signal and an audio signal of a UHD (Ultra High Definition) video source and outputs the video signal to four parallel a 4k input processor for converting the audio signal into a deserializing digital signal and converting the audio signal into a deserializing digital signal; A first HEVC processor for receiving the first video signal and the audio signal of the converted video signal and converting the first video signal and the audio signal into a PCIe signal; Second, third and fourth HEVC processors respectively receiving the second, third, and fourth video signals of the converted video signal and converting the second, third, and fourth video signals, respectively, into a PCIe signal; A PCIe switch for receiving the first, second, third, and fourth video signals converted into the PCIe signal and the audio signal; A first codec FPGA for receiving a first video signal converted from the PCIe switch into the PCIe signal, compressing and encoding the first video signal into an HEVC format, and compressing and encoding the audio signal received from the PCIe switch; And a second, third, and fourth codec FPGAs, respectively, for receiving second, third, and fourth video signals converted from the PCIe switch to the PCIe signal, and compressively encoding the second, third, and fourth video signals, respectively, in an HEVC format, The first, second, third, and fourth video signals compressively encoded in the first, second, third, and fourth codec FPGAs, and the audio signal compression-encoded in the first codec FPGA through the PCIe switch, ) To process and packetize the 4k UHD format HEVC compressed image.

According to another embodiment of the present invention, the 4k input processor receives a UHD (Ultra High Definition) video source input through 12G-SDI or HDMI 2.0 or a UHD video source input with four 3G-SDI have.

According to another embodiment of the present invention, a TS processor for inserting PIS (Program Specific Information) or PSIP (Program and System Information Protocol), which is moving picture data of UHD standard, into the packetized 4k UHD format HEVC compressed image and outputting it; As shown in FIG.

According to another embodiment of the present invention, the first codec FPGA compression-encodes the received video signal in the HEVC format, and outputs the received audio signal to the multi-audio Dolby Digital AC-3, MPEG-1 Layer 2, As shown in FIG.

According to another embodiment of the present invention, the second, third, and fourth HEVC processors may synchronize the second, third, and fourth video signals using a single sync signal.

According to another embodiment of the present invention, the TS processor converts the packetized 4k UHD format HEVC compressed image into a DVB-ASI formatted transport stream (TS) or outputs it to an IP packet (Internet Protocol Packet) And output it.

According to the embodiment of the present invention, it is possible to encode 4k UHD (Ultra High Definition) contents into HEVC format using a plurality of FPGAs, to provide both DVB-ASI format output and IP stream format output, It is possible to provide UHD digital broadcasting suited to the environment.

1 is a block diagram of a 4k UHD encoding apparatus using a plurality of FPGAs according to an embodiment of the present invention.
2 is a diagram for explaining a 4k UHD video according to an embodiment of the present invention.
3 is a flowchart illustrating a 4k UHD encoding method using a plurality of FPGAs according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention. In addition, the size of each component in the drawings may be exaggerated for the sake of explanation and does not mean a size actually applied.

FIG. 1 is a block diagram of a 4k UHD encoding apparatus using a plurality of FPGAs according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a 4k UHD video according to an embodiment of the present invention.

A configuration of a 4k UHD encoding apparatus using a plurality of FPGAs according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

1, a 4k UHD encoding apparatus using a plurality of FPGAs according to an embodiment of the present invention includes a 4k input processor 110, first, second, third, and fourth HEVC processors 121, 122, 123, 124, a PCIe switch 130, first, second, third, and fourth codec FPGAs 141, 142, 143, 144, and a TS processor 150.

The 4k input processor 110 corrects errors of the video signal and the audio signal of the UHD (Ultra High Definition) video source. Further, the 4k input processor 110 converts the video signal into four deserializing digital signals, and converts the audio signals into a deserializing digital signal.

At this time, the 4k input processor 110 may receive a UHD (Ultra High Definition) video source input by 12G-SDI or HDMI 2.0 or a UHD video source input by four 3G-SDI.

More specifically, the 4k input processor 110 receives one UHD video source for HDMI 2.0 and 12G-SDI, converts the signal into four deserializing digital signals, Serial Digital Interface) as a video source.

The 4k input processor 110 inputs the converted parallel video signals to the first, second, third, and fourth HEVC processors 121, 122, 123, and 124 and outputs the converted parallel audio signals to the first HEVC And inputs it to the processor 121.

The first HEVC processor 121 receives the first video signal and the audio signal of the converted video signal, and converts the received first video signal into a PCIe signal.

The second, third, and fourth HEVC processors 122, 123, and 124 receive the second, third, and fourth video signals of the converted video signal, respectively, and convert the second, third, and fourth video signals into PCIe signals, respectively.

More specifically, the second HEVC processor 122 receives the second video signal of the converted video signal and converts the second video signal into a PCIe signal, and the third HEVC processor 123 converts the third video And converts it into a PCIe signal. The fourth HEVC processor 124 receives the fourth video signal of the converted video signal and converts the fourth video signal into a PCIe signal.

The first, second, third, and fourth HEVC processors 121, 122, 123, and 124 may synchronize the first, second, third, and fourth video signals using a single sync signal.

The PCIe switch 130 receives the first, second, third, and fourth video signals converted into the PCIe signal and the audio signal, and converts the first, second, , And transmits the received audio signal to the first codec FPGA 141 (142, 143, 144).

In more detail, the first codec FPGA 141 receives the first video signal converted from the PCIe signal from the PCIe switch 130, compresses and encodes the first video signal into the HEVC format, And compresses and encodes the audio signal.

Also, the second codec FPGA 142 receives the second video signal converted from the PCIe signal from the PCIe switch 130 and compresses and encodes the second video signal into the HEVC format, and the third codec FPGA 143 receives the PCIe switch 130 And compresses the third video signal into the HEVC format. The fourth codec FPGA 144 receives the second video signal converted from the PCIe signal from the PCIe switch 130 It can be compression-encoded in the HEVC format.

The first codec FPGA 141 compresses and encodes a video signal received through the PCIe switch 130 into an HEVC format and outputs the received audio signal to a multi-audio Dolby Digital AC-3, MPEG-1 Layer 2 Or compressed according to the AAC standard.

Also, the first HEVC processor 121 receives the first, second, and third compression codes coded by the first, second, third, and fourth codec FPGAs 141, 142, 143, and 144 through the PCIe switch 130 And receives the 4-bit video signal and the audio signal compression-encoded in the first codec FPGA 141.

Accordingly, as shown in FIG. 2, the first HEVC processor 121 combines the compression-encoded first, second, third, and fourth video signals 101, 102, 103, MUX) to be processed and packetized into a HEVC compressed image of the 4k UHD (4096 * 2160) format.

The TS processor 150 receives the packetized 4k UHD format HEVC compressed image from the first HEVC processor 121 and inserts the HEVC compressed image of the packetized 4k UHD format into a PIS Program specific information) or PSIP (Program and System Information Protocol).

In this case, the program specific information (PSI) refers to metadata defined in the MPEG standard, and the program and system information protocol (PSIP) are transmitted from a digital TV based on the ATSC standard specification. And the information that is required to receive the TV.

In more detail, the PSIP is a set of tables designed to operate in all transport streams (TS) for the digital TV. It describes necessary information of a virtual channel transmitted in a specific TS, The basic table includes a STT (System Time Table) for transmitting time information, a Master Guide Table (MGT) for managing transmission tables, a VCT (Virtual Channel Table) for providing virtual channel information, And a Rating Region Table (RRT) that defines the rating criteria.

At this time, the TS processor 150 converts the packetized 4k UHD format HEVC compressed image into a DVB-ASI formatted transport stream (TS) or outputs it to an IP packet (Internet Protocol Packet) have.

The DVB-ASI (Digital Video Broadcasting-Asynchronous Serial Interface) refers to a serial digital broadcast transmission stream (TS). The TS processor 150 adds UDP and IP to a transport stream (TS) It can send out.

Accordingly, the TS processor 150 according to the present invention can provide UHD digital broadcasting in digital TV and IP communication environment by providing both DVB-ASI format output and IP stream format output.

3 is a flowchart illustrating a 4k UHD encoding method using a plurality of FPGAs according to an embodiment of the present invention.

Hereinafter, a 4k UHD encoding method using a plurality of FPGAs according to an embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 3, first, a 4k input processor corrects an error of a video signal and an audio signal of a UHD (Ultra High Definition) video source. Further, the 4k input processor 110 converts the video signal into four deserializing digital signals and converts the audio signals into a deserializing digital signal (S305).

At this time, the 4k input processor 110 may receive a UHD (Ultra High Definition) video source input by 12G-SDI or HDMI 2.0 or a UHD video source input by four 3G-SDI.

More specifically, the 4k input processor receives one UHD video source in the case of HDMI 2.0 and 12G-SDI, converts the signal into four deserializing digital signals, or four 4-input serial digital interface ) As a video source.

The 4k input processor inputs the converted four parallel video signals to the first, second, third, and fourth HEVC processors, and inputs the converted parallel audio signals to the first HEVC processor.

Accordingly, the first HEVC processor receives the first video signal and the audio signal of the converted video signal, and converts the received first video signal and the audio signal into a PCIe signal (S310).

The second, third, and fourth HEVC processors respectively receive the second, third, and fourth video signals of the converted video signal, respectively, and convert the second, third, and fourth video signals into PCIe signals, respectively (S315).

That is, a second HEVC processor receives a second video signal of the converted video signal and converts it into a PCIe signal, a third HEVC processor receives a third video signal of the converted video signal, converts the third video signal into a PCIe signal, And a fourth HEVC processor receives the fourth video signal of the converted video signal and converts the fourth video signal into a PCIe signal.

The first, second, third, and fourth HEVC processors may synchronize the first, second, third, and fourth video signals using a single sync signal.

Thereafter, the PCIe switch receives the first, second, third, and fourth video signals converted into the PCIe signal and the audio signal, and transmits the first, second, 4 codec FPGAs 141, 142, 143, and 144, respectively, and transmits the audio signals to the first codec FPGA 141 (S320).

Accordingly, the first codec FPGA receives the first video signal converted from the PCIe signal from the PCIe switch, compresses and encodes the first video signal into the HEVC format, and compresses and encodes the audio signal received from the PCIe switch at step S325.

In addition, the second codec FPGA receives the second video signal converted from the PCIe switch into the HEVC format, and the third codec FPGA receives the third video signal converted from the PCIe signal into the PCIe signal, The fourth codec FPGA receives and compresses the second video signal converted from the PCIe signal into the HEVC format in step S330.

The first codec FPGA compresses and encodes a video signal received through the PCIe switch into an HEVC format and compresses the received audio signal into a multi-audio Dolby Digital AC-3, MPEG-1 Layer 2, or AAC standard Can be encoded.

Also, the first HEVC processor may transmit the first, second, third, and fourth video signals compressively encoded in the first, second, third, and fourth codec FPGAs, and the audio compressed and encoded in the first codec FPGA Signal.

Accordingly, the first HEVC processor combines the compression-encoded first, second, third, and fourth video signals 101, 102, 103, and 104 with the compression-encoded audio signal to generate 4k UHD 4096 * 2160) type HEVC compressed image (S335).

Thereafter, the TS processor receives the packetized 4k UHD format HEVC compressed image from the first HEVC processor, and adds PIS (Program Specific Information), which is UHD standard moving picture data, to the packetized 4k UHD format HEVC compressed image. Or a PSIP (Program and System Information Protocol) is inserted and output (S340).

In this case, the program specific information (PSI) refers to metadata defined in the MPEG standard, and the program and system information protocol (PSIP) are transmitted from a digital TV based on the ATSC standard specification. And the information that is required to receive the TV.

In more detail, the PSIP is a set of tables designed to operate in all transport streams (TS) for the digital TV. It describes necessary information of a virtual channel transmitted in a specific TS, The basic table includes a STT (System Time Table) for transmitting time information, a Master Guide Table (MGT) for managing transmission tables, a VCT (Virtual Channel Table) for providing virtual channel information, And a Rating Region Table (RRT) that defines the rating criteria.

At this time, the TS processor may convert the packetized 4k UHD format HEVC compressed image into a DVB-ASI formatted transport stream (TS) or output it, or convert it into an IP packet (Internet Protocol Packet) ).

The DVB-ASI (Digital Video Broadcasting-Asynchronous Serial Interface) refers to a serial digital broadcast transmission stream (TS). The TS processor adds UDP and IP to a transport stream (TS) have.

Accordingly, the TS processor according to the present invention can provide both DVB-ASI format output and IP stream format output, and can provide UHD digital broadcasting in digital TV and IP communication environment.

In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical spirit of the present invention should not be limited to the above-described embodiments of the present invention, but should be determined by the claims and equivalents thereof.

110: 4k input processor
121: First HEVC processor
122: second HEVC processor
123: Third HEVC processor
124: fourth HEVC processor
130: PCIe switch
141: First Codec FPGA
142: Second Codec FPGA
143: Third Codec FPGA
144: Fourth codec FPGA
150: TS processor

Claims (6)

A 4k input for correcting errors of a video signal and an audio signal of a UHD (Ultra High Definition) video source, converting the video signal into four deserializing digital signals and converting the audio signals into a deserializing digital signal A processor;
A first HEVC processor for receiving the first video signal and the audio signal of the converted video signal and converting the first video signal and the audio signal into a PCIe signal;
Second, third and fourth HEVC processors respectively receiving the second, third, and fourth video signals of the converted video signal and converting the second, third, and fourth video signals, respectively, into a PCIe signal;
A PCIe switch for receiving the first, second, third, and fourth video signals converted into the PCIe signal and the audio signal;
A first codec FPGA for receiving a first video signal converted from the PCIe switch into the PCIe signal, compressing and encoding the first video signal into an HEVC format, and compressing and encoding the audio signal received from the PCIe switch; And
A second, third, and fourth codec FPGAs that respectively receive second, third, and fourth video signals converted from the PCIe switch to the PCIe signal and compression-encode the second, third, and fourth video signals, respectively, in an HEVC format;
Lt; / RTI >
Wherein the first HEVC processor comprises:
The first, second, third, and fourth video signals compressively encoded in the first, second, third, and fourth codec FPGAs, and the audio signal compression-encoded in the first codec FPGA through the PCIe switch, ), And processes and packetizes the 4k UHD format HEVC compressed image using a plurality of FPGAs. The method according to claim 1,
The 4k input processor includes:
A 4k UHD encoding device using a plurality of FPGAs that receives a UHD (Ultra High Definition) video source input with 12G-SDI or HDMI 2.0 or a UHD video source input with four 3G-SDIs. The method according to claim 1,
And a TS processor for inserting PIS (Program Specific Information) or PSIP (Program and System Information Protocol), which is moving picture data of the UHD standard, into the packetized 4k UHD format HEVC compressed image and outputting 4k UHD encoding device. The method according to claim 1,
The first codec FPGA includes:
A plurality of FPGAs for compressing and coding the received video signal in an HEVC format and compression-encoding the received audio signal in a multi-audio Dolby Digital AC-3, MPEG-1 Layer 2 or AAC standard. The method according to claim 1,
The first, second, third, and fourth HEVC processors,
A 4k UHD encoder using a plurality of FPGAs to synchronize the first, second, third, and fourth video signals using a single sync signal. The method of claim 3,
The TS processor,
A 4k UHD encoding apparatus using a plurality of FPGAs that converts the packetized 4k UHD format HEVC compressed image into a DVB-ASI formatted transport stream (TS) or converts it into an IP packet (Internet Protocol Packet).
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190013063A (en) * 2017-07-31 2019-02-11 서울대학교산학협력단 Method for controlling accelerator of heterogeneous system, and heterogeneous system for performing the same
CN111726700A (en) * 2020-06-10 2020-09-29 北京中联合超高清协同技术中心有限公司 Video relay system and video receiving system
CN113890977A (en) * 2021-10-13 2022-01-04 中国电子科技集团公司第三研究所 Airborne video processing device and unmanned aerial vehicle with same

Family Cites Families (2)

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Publication number Priority date Publication date Assignee Title
KR101347956B1 (en) * 2013-07-29 2014-01-10 주식회사 리버스톤미디어 System for stream transformation and restoration of ultra high-definition image and method for stream transformation and restoration of ultra high-definition image therefor
KR101571271B1 (en) * 2015-07-23 2015-11-24 (주)캐스트윈 Multi Format Ultra High Definition HEVC Encoder/Transcoder

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190013063A (en) * 2017-07-31 2019-02-11 서울대학교산학협력단 Method for controlling accelerator of heterogeneous system, and heterogeneous system for performing the same
CN111726700A (en) * 2020-06-10 2020-09-29 北京中联合超高清协同技术中心有限公司 Video relay system and video receiving system
CN113890977A (en) * 2021-10-13 2022-01-04 中国电子科技集团公司第三研究所 Airborne video processing device and unmanned aerial vehicle with same

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