KR20170030698A - Memory device using magnetic tunnel junction - Google Patents

Memory device using magnetic tunnel junction Download PDF

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KR20170030698A
KR20170030698A KR1020150127679A KR20150127679A KR20170030698A KR 20170030698 A KR20170030698 A KR 20170030698A KR 1020150127679 A KR1020150127679 A KR 1020150127679A KR 20150127679 A KR20150127679 A KR 20150127679A KR 20170030698 A KR20170030698 A KR 20170030698A
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magnetic tunnel
tunnel junction
layer
gate
coupled
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KR1020150127679A
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Korean (ko)
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김재관
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에스케이하이닉스 주식회사
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Publication of KR20170030698A publication Critical patent/KR20170030698A/en

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    • H01L43/08—
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  • Mram Or Spin Memory Techniques (AREA)

Abstract

A memory device using a magnetic tunnel junction (MTJ) comprises: a first transistor having a source terminal and a first gate terminal; a second transistor having a drain terminal and a second gate terminal, and coupled with the first transistor through a common connection terminal; a first magnetic tunnel junction coupled to the first gate terminal; a second magnetic tunnel junction coupled to the second gate terminal; and a conductive line arranged to set the resistance characteristics of the first magnetic tunnel junction and the second magnetic tunnel junction to be opposite to each other.

Description

[0001] The present invention relates to a memory device using a magnetic tunnel junction,

BACKGROUND OF THE INVENTION [0002] Various embodiments of the present disclosure are directed to memory devices, and more particularly to memory devices that utilize magnetic tunnel junctions.

BACKGROUND ART A memory device using a magnetic tunnel junction (MTJ), for example, a magnetic random access memory (MRAM) is a memory device capable of storing nonvolatile data with a low power consumption. Volatile data storage using the thin film magnetic body of the thin film magnetic body of the thin film magnetic body and random access to each of the plurality of thin film magnetic bodies. The magnetic tunnel junction is composed of a structure in which a pinned layer including a first ferromagnetic layer, a tunneling barrier, and a free layer including a second ferromagnetic layer are sequentially stacked. The magnetization direction of the first ferromagnetic layer is fixed and the magnetization direction of the second ferromagnetic layer can be changed through recording. The information of the memory device using the magnetic tunnel junction can be realized through the difference in electrical resistance of the magnetic tunnel junction structure. That is, when the magnetization directions of the first and second ferromagnetic materials are parallel to each other, they have a low resistance, that is, data "0". When the magnetization directions are antiparallel to each other, they have high resistance, that is, data "1".

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device implemented using two transistors and magnetic tunnel junctions having different threshold voltage values.

A memory device according to an example includes a first transistor having a source terminal and a first gate terminal, a second transistor having a drain terminal and a second gate terminal and coupled through a connection terminal shared with the first transistor, A second magnetic tunnel junction coupled to the second gate terminal, and a second magnetic tunnel junction coupled to the first magnetic tunnel junction and the second magnetic tunnel junction coupled to the conductive line < RTI ID = 0.0 > .

The memory device according to one example comprises a first n + type junction region and a second n + type junction region arranged to be spaced apart by a first channel layer in an upper region of the substrate, a second n + type junction region in an upper region of the substrate, A third n + type junction region disposed to be spaced apart by a second channel layer; a first gate insulating layer and a first gate conductive layer disposed over the first channel layer; and a second gate insulating layer And a second gate conductive layer; a first magnetic tunnel junction disposed to be coupled to the first gate conductive layer; a second magnetic tunnel junction disposed to be coupled to the second gate conductive layer; and a second magnetic tunnel junction, Lt; RTI ID = 0.0 > 2 < / RTI > magnetic tunnel junctions.

According to various embodiments, programming and erasing are performed by a magnetic field caused by current flowing in a conductor, a cell can be constructed that stores data without being influenced by the gate structure and has a high operation speed. In addition, An advantage is provided that the junction always exhibits opposite characteristics.

1 is a diagram illustrating a memory device using a magnetic tunnel junction according to an example.
2 is a diagram showing an equivalent circuit configuration of the memory device of FIG.
3 and 4 are diagrams for explaining the operation of the memory device of FIG.

In the description of the examples of the present application, descriptions such as " first "and" second "are for distinguishing members, and are not used to limit members or to denote specific orders. Further, the description that a substrate located on the "upper", "lower", or "side" of a member means a relative positional relationship means that the substrate is in direct contact with the member, or another member The present invention is not limited to a particular case. It is also to be understood that the description of "connected" or "connected" to one component may be directly or indirectly electrically or mechanically connected to another component, Separate components may be interposed to form a connection relationship or a connection relationship.

1 is a diagram illustrating a memory device using a magnetic tunnel junction according to an example. Referring to FIG. 1, a memory device 100 according to the present example includes a first transistor 210 and a second transistor 220 disposed on a substrate 110. In one example, the first transistor 210 and the second transistor 220 may be a MOS field effect transistor (MOSFET). In another example, the first transistor 210 and the second transistor 220 may be a charge storage transistor having a charge trap layer, or a stacked gate transistor having a stacked gate structure in which a floating gate and a control gate are stacked. The first transistor 210 and the second transistor 220 may be of n-channel type, and the substrate 110 may have a p-type conductivity. The first transistor 210 and the second transistor 220 may be disposed in an active region of the substrate 110. The active region of the substrate 110 may be defined by the trench isolation layer 112.

The first transistor 210 includes a first n + type junction region 211, a second n + type junction region 212, a first gate insulating layer 213, and a first gate electrode layer 214. The first n + type junction region 211 and the second n + type junction region 212 are arranged to be spaced apart from each other by the first channel layer 215 in the upper region of the substrate 110. [ The first n + type junction region 211 and the second n + type junction region 212 may have a lightly doped drain (LDD) structure. The first channel layer 215 has a first threshold voltage value. In one example, the first threshold voltage value may be approximately 0.7V. The first n + -type junction region 211 may be a source region and is coupled to the source terminal S. The second n + type junction region 212 may be shared with the second transistor 220. A first gate insulating layer 213 is disposed over the first channel layer 215. The first gate electrode layer 214 is disposed over the first gate insulating layer 213. The first gate electrode layer 214 is coupled to the first gate terminal G1. A first gate spacer layer 216 may be disposed on both sides of the first gate insulating layer 213 and the first gate electrode layer 214, respectively.

The second transistor 220 includes a second n + type junction region 212, a third n + type junction region 221, a second gate insulating layer 223, and a second gate electrode layer 224. The second n + type junction region 212 and the third n + type junction region 221 are arranged to be spaced apart from each other by the second channel layer 225 in the upper region of the substrate 110. The third n + -type junction region 221 may have a lightly doped drain (LDD) structure. The second channel layer 225 has a second threshold voltage value. In one example, the second threshold voltage value may be approximately 0.5V. The third n + -type junction region 221 may be a drain region and is coupled to the drain terminal D. A second gate insulating layer 223 is disposed over the second channel layer 225. The second gate electrode layer 224 is disposed over the second gate insulating layer 223. And the second gate electrode layer 224 is coupled to the second gate terminal G2. A first gate spacer layer 226 may be disposed on both sides of the first gate insulating layer 223 and the first gate electrode layer 224.

The first gate terminal G1 is coupled to the first node A. [ The first magnetic tunnel junction 310 and the ground terminal GND are branched at the first node A. [ The first magnetic tunnel junction 310 includes a first pinned layer 311, a first tunneling barrier 312, and a first free layer 313. do. The first pinned layer 311 and the first free layer 313 may be formed of a ferromagnetic plate. The polarity of the ferromagnetic material constituting the first pinned layer 311 is fixed in one direction, while the polarity of the ferromagnetic material constituting the first free layer 313 may be changed by the magnetic field. The first pinned layer 311 is coupled to the first node A and the first free layer 313 is coupled to the gate bias applied terminal GB. A first resistor 331 for a gate bias at the first node A may be disposed between the first node A and the ground terminal GND. The first resistor 331 has a first resistance value R1. The first resistor 331 together with the first magnetic tunnel junction 310 constitute a voltage divider circuit. Therefore, a voltage equal to the difference in voltage dropped by the first magnetic tunnel junction 310 is applied to the first node A at a voltage applied from the gate bias applying terminal GB.

And the second gate terminal G2 is coupled to the second node B. [ The second magnetic tunnel junction 320 and the ground terminal GND are branched at the second node B. [ The second magnetic tunnel junction 320 is composed of a structure in which the second pinning layer 321, the second tunneling barrier 322, and the second free layer 323 are bonded. The second pinned layer 321 and the second free layer 323 may be made of a ferromagnetic plate. The polarity of the ferromagnetic material constituting the second pinning layer 321 is fixed in one direction, while the polarity of the ferromagnetic material constituting the second free layer 323 may be changed by the magnetic field. The second pinned layer 321 is coupled to the second node B and the second free layer 323 is coupled to the gate bias applied terminal GB. A second resistor 332 for gate bias at the second node B may be disposed between the second node B and the ground terminal GND. The second resistor 332 has a second resistance value R2. The second resistance value R2 of the second resistor 332 may be substantially equal to the first resistance value R1 of the first resistor 331. [ The second resistor 332 together with the second magnetic tunnel junction 320 constitute a voltage divider circuit. Therefore, a voltage equal to the difference in voltage dropped by the second magnetic tunnel junction 320 is applied to the second node B at the voltage applied from the gate bias applying terminal GB.

A conductive line 350 is disposed between the first magnetic tunnel junction 310 and the second magnetic tunnel junction 320. The conductive line 350 is disposed parallel to the surface of the first free layer 313 of the first magnetic tunnel junction 310 and the surface of the second free layer 323 of the second magnetic tunnel junction 320. Therefore, when a current is supplied through the conductive line 350, a magnetic field is formed around the conductive line 350, and the direction of the magnetic field is opposite to that of the first magnetic tunnel junction 310 and the second magnetic tunnel junction 320 . The magnetization direction of the ferromagnetic body constituting the first free layer 313 of the first magnetic tunnel junction 310 and the magnetization direction of the ferromagnetic body constituting the second free layer 323 of the second magnetic tunnel junction 320, The directions can be opposite to each other.

2 is a diagram showing an equivalent circuit configuration of the memory device of FIG. In Fig. 2, the same reference numerals as those in Fig. 1 denote the same components. 2, the memory device 100 includes a first transistor 210 having a source terminal S, a connection terminal J, and a first gate terminal G1, D, a connection terminal J, and a second gate terminal G2. The first transistor 210 and the second transistor 220 are coupled to each other through a connection terminal J. The first gate terminal G1 of the first transistor 210 is coupled to the first node A. In the first node A, the gate bias applying terminal GB and the ground terminal GND are branched. A first magnetic tunnel junction 310 is disposed between the first node A and the gate bias applying terminal GB. The first magnetic tunnel junction 310 may have a first magnetic tunnel junction resistance value Rm1. A first resistor 331 having a first resistance value R1 is disposed between the first node A and the ground terminal GND. And the second gate terminal G2 of the second transistor 220 is coupled to the second node B. [ At the second node B, the gate bias applying terminal GB and the ground terminal GND are branched. A second magnetic tunnel junction 320 is disposed between the second node B and the gate bias applying terminal GB. The second magnetic tunnel junction 320 may have a second magnetic tunnel junction resistance value Rm2. A second resistor 332 having a second resistance value R2 is disposed between the second node B and the ground terminal GND. The first magnetic tunnel junction resistance value Rm1 of the first magnetic tunnel junction 310 is a high resistance value or a low resistance value depending on the direction of the current flowing in the conductive line 350. [ The second magnetic tunnel junction resistance value Rm2 of the second magnetic tunnel junction 320 also becomes a high resistance value or a low resistance value depending on the direction of the current flowing in the conductive line 350. [ However, if the direction of current flowing in the conductive line 350 is in any direction and the first magnetic tunnel junction resistance value Rm1 is a high resistance value, the second magnetic tunnel junction resistance value Rm2 becomes a low resistance value, When the first magnetic tunnel junction resistance value Rm1 is a low resistance value, the second magnetic tunnel junction resistance value Rm2 becomes a high resistance value.

The voltage VA applied to the first node A and the voltage VB applied to the second node B are calculated by the following Equation 1,

Figure pat00001

Figure pat00002

Here, VGB represents the voltage applied to the bias application terminal GB. When the first resistance value R1 of the first resistor 331 is equal to the second resistance value R2 of the second resistor 332, the voltage VA applied to the first node A, The voltage VB applied to the first magnetic tunnel junction resistance B depends on the first magnetic tunnel junction resistance value Rm1 and the second magnetic tunnel junction resistance value Rm2. Since the first magnetic tunnel junction resistance value Rm1 and the second magnetic tunnel junction resistance value Rm2 have mutually opposite values, the voltage VA applied to the first node A and the voltage VA applied to the second node B The applied voltages also have opposite values.

3 and 4 are diagrams for explaining the operation of the memory device of FIG. Referring to FIG. 3, when a current flows through the conductive line 350 in a direction to penetrate the ground, the magnetization direction of the ferromagnetic material constituting the first free layer 313 of the first magnetic tunnel junction 310 is shifted upward As a result, the magnetization direction of the ferromagnetic material forming the first pinning layer 311 of the first magnetic tunnel junction 310 becomes anti-parallel to the magnetization direction of the ferromagnetic material. Therefore, the first magnetic tunnel junction resistance value Rm1 of the first magnetic tunnel junction 310 becomes a high resistance value. On the other hand, the magnetization direction of the ferromagnetic material constituting the second free layer 323 of the second magnetic tunnel junction 320 is set to be downward, so that the second pinning layer 321 of the second magnetic tunnel junction 320 And becomes parallel to the magnetization direction of the constituting ferromagnetic body. Therefore, the second magnetic tunnel junction resistance value Rm2 of the second magnetic tunnel junction 320 becomes a low resistance value.

The first magnetic tunnel junction resistance value Rm1 of the first magnetic tunnel junction 310 becomes a high resistance value and the second magnetic tunnel junction resistance value Rm2 of the second magnetic tunnel junction 320 becomes a low resistance value The voltage VA applied to the first node A is smaller than the voltage VB applied to the second node B. As a result, The voltage applied to the first gate terminal G1 of the first transistor 210 is relatively small and the voltage applied to the second gate terminal G2 of the second transistor 220 is relatively large . In one example, the first transistor 210 has a relatively high threshold voltage value, for example, a threshold voltage value of 0.7 V, and the second transistor 220 has a relatively low threshold voltage value, The voltage applied to the first gate terminal G1 of the first transistor 210 or the voltage VA applied to the first node A is 0.7 V which is the threshold voltage value of the first transistor 210 For example, 0.6V. The magnitude of the voltage VA applied to the first node A can be controlled by appropriately setting the first resistance value R1 and the first magnetic tunnel junction resistance value Rm1. The voltage applied to the second gate terminal G2 of the second transistor 220 or the voltage VB applied to the second node B is lower than the threshold voltage value 0.5V of the second transistor 220 So that a large-sized voltage, for example, a voltage of 1 V is obtained. The magnitude of the voltage VB applied to the second node B can be controlled by appropriately setting the second resistance value R2 and the second magnetic tunnel junction resistance value Rm2. In this case, the second transistor 220 is turned on, but the first transistor 210 is turned off so that the data line (D) does not flow from the drain terminal D to the source terminal S low state.

Referring to FIG. 4, when a current flows through the conductive line 350 in a direction passing through the ground, the magnetization direction of the ferromagnetic material forming the first free layer 313 of the first magnetic tunnel junction 310 is downward As a result, the magnetization direction of the first pinned layer 311 of the first magnetic tunnel junction 310 becomes parallel to the magnetization direction of the ferromagnetic body. Therefore, the first magnetic tunnel junction resistance value Rm1 of the first magnetic tunnel junction 310 becomes a low resistance value. On the other hand, the magnetization direction of the ferromagnetic material constituting the second free layer 323 of the second magnetic tunnel junction 320 is set in the upward direction, so that the second pinning layer 321 of the second magnetic tunnel junction 320 And becomes anti-parallel to the magnetization direction of the constituent ferromagnetic body. Therefore, the second magnetic tunnel junction resistance value Rm2 of the second magnetic tunnel junction 320 becomes a high resistance value.

The first magnetic tunnel junction resistance value Rm1 of the first magnetic tunnel junction 310 becomes a low resistance value and the second magnetic tunnel junction resistance value Rm2 of the second magnetic tunnel junction 320 becomes a high resistance value The voltage VA applied to the first node A is larger than the voltage VB applied to the second node B. In this case, The voltage applied to the first gate terminal G1 of the first transistor 210 is relatively large and the voltage applied to the second gate terminal G2 of the second transistor 220 is relatively small . In one example, the first transistor 210 has a relatively high threshold voltage value, for example, a threshold voltage value of 0.7 V, and the second transistor 220 has a relatively low threshold voltage value, The voltage applied to the first gate terminal G1 of the first transistor 210 or the voltage VA applied to the first node A is 0.7 V which is the threshold voltage value of the first transistor 210 For example, 1 V. < / RTI > The magnitude of the voltage VA applied to the first node A can be controlled by appropriately setting the first resistance value R1 and the first magnetic tunnel junction resistance value Rm1. The voltage applied to the second gate terminal G2 of the second transistor 220 or the voltage VB applied to the second node B is lower than the threshold voltage value 0.5V of the second transistor 220 So that a large-sized voltage, for example, a voltage of 0.6 V is obtained. The magnitude of the voltage VB applied to the second node B can be controlled by appropriately setting the second resistance value R2 and the second magnetic tunnel junction resistance value Rm2. In this case, both the first transistor 210 and the second transistor 220 are turned on, and thus the memory element is turned on at the data high (Ids) through which the current IDS flows from the drain terminal D to the source terminal S high state.

Although the embodiments of the present application as described above illustrate and describe the drawings, it is intended to illustrate what is being suggested in the present application and is not intended to limit what is presented in the present application in a detailed form.

100 ... memory element 110 ... substrate
112 ... trench isolation layer 210 ... first transistor
211 ... first n + type junction region 212 ... second n + type junction region
213 ... first gate insulating layer 214 ... first gate conductive layer
215 ... first channel layer 216 ... first gate spacer layer
220 ... second transistor 221 ... third n + -type junction region
223 ... second gate insulating layer 224 ... second gate conductive layer
225 ... second channel layer 226 ... second gate spacer layer
310 ... first magnetic tunnel junction 311 ... first fixed layer
312 ... first tunnel barrier 313 ... first free layer
320 ... second magnetic tunnel junction 321 ... second fixed layer
322 ... second tunnel barrier 323 ... second free layer
331 ... first resistor 332 ... second resistor
350 ... Challenge line

Claims (21)

A first transistor having a source terminal and a first gate terminal;
A second transistor having a drain terminal and a second gate terminal and coupled through a connection terminal shared by the first transistor;
A first magnetic tunnel junction coupled to the first gate terminal;
A second magnetic tunnel junction coupled to the second gate terminal; And
And a conductive line arranged to reverse the resistance characteristics of the first magnetic tunnel junction and the second magnetic tunnel junction. The method according to claim 1,
Wherein the first transistor and the second transistor are MOS field effect transistors. 3. The method of claim 2,
Wherein the first transistor and the second transistor have different threshold voltage values. The method of claim 3,
Wherein a threshold voltage of the first transistor is greater than a threshold voltage of the second transistor. The method of claim 1, wherein the first magnetic tunnel junction comprises:
A first pinned layer coupled to the first gate terminal;
A first tunnel barrier bonded to the first pinning layer; And
And a first free layer coupled to the gate bias line while being coupled to the first tunnel barrier. 6. The method of claim 5, wherein the second magnetic tunnel junction comprises:
A second pinned layer coupled to the second gate terminal;
A second tunnel barrier bonded to the second pinning layer; And
And a second free layer coupled to the gate bias line while being coupled to the second tunnel barrier. The method according to claim 6,
Wherein the conductive line is disposed such that a magnetization direction of the first free layer and a magnetization direction of the second free layer are opposite to each other due to a current flowing through the conductive line. 8. The method of claim 7,
Wherein the conductive line is disposed in parallel with the first free layer surface and the second free layer surface between the first magnetic tunnel junction and the second magnetic tunnel junction. The method according to claim 1,
And a first node between the first magnetic tunnel junction and the first gate terminal, and is branched to the ground terminal through the first resistor at the first node. 10. The method of claim 9,
And a second node between the second magnetic tunnel junction and the second gate terminal, and is branched to the ground terminal through the second resistor at the second node. 11. The method of claim 10,
Wherein a resistance value of the first resistor and a resistance value of the second resistor are the same. A first n + type junction region and a second n + type junction region arranged to be separated from each other by a first channel layer in an upper region of the substrate;
A third n + type junction region disposed in the upper region of the substrate so as to be separated by the second n + type junction region and the second channel layer;
A first gate insulating layer and a first gate conductive layer disposed on the first channel layer;
A second gate insulating layer and a second gate conductive layer disposed on the second channel layer;
A first magnetic tunnel junction disposed to be coupled to the first gate conductive layer;
A second magnetic tunnel junction disposed to couple to the second gate conductive layer; And
And a conductive line arranged to reverse the resistance characteristics of the first magnetic tunnel junction and the second magnetic tunnel junction. 13. The method of claim 12,
Wherein a threshold voltage value of the first channel layer and a threshold voltage value of the second channel layer are different from each other. 14. The method of claim 13,
Wherein a threshold voltage value of the first channel layer is greater than a threshold voltage value of the second channel layer. 13. The method of claim 12, wherein the first magnetic tunnel junction comprises:
A first pinned layer coupled to the first gate terminal;
A first tunnel barrier bonded to the first pinning layer; And
And a first free layer coupled to the gate bias line while being coupled to the first tunnel barrier. 16. The method of claim 15, wherein the second magnetic tunnel junction comprises:
A second pinned layer coupled to the second gate terminal;
A second tunnel barrier bonded to the second pinning layer; And
And a second free layer coupled to the gate bias line while being coupled to the second tunnel barrier. 17. The method of claim 16,
Wherein the conductive line is disposed such that a magnetization direction of the first free layer and a magnetization direction of the second free layer are opposite to each other due to a current flowing through the conductive line. 18. The method of claim 17,
Wherein the conductive line is disposed in parallel with the first free layer surface and the second free layer surface between the first magnetic tunnel junction and the second magnetic tunnel junction. The method according to claim 1,
And a first node between the first magnetic tunnel junction and the first gate terminal, and is branched to the ground terminal through the first resistor at the first node. 20. The method of claim 19,
And a second node between the second magnetic tunnel junction and the second gate terminal, and is branched to the ground terminal through the second resistor at the second node. 21. The method of claim 20,
Wherein a resistance value of the first resistor and a resistance value of the second resistor are the same.
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