KR20160147427A - Uv light emitting device and method for fabricating the same - Google Patents

Uv light emitting device and method for fabricating the same Download PDF

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Publication number
KR20160147427A
KR20160147427A KR1020150084161A KR20150084161A KR20160147427A KR 20160147427 A KR20160147427 A KR 20160147427A KR 1020150084161 A KR1020150084161 A KR 1020150084161A KR 20150084161 A KR20150084161 A KR 20150084161A KR 20160147427 A KR20160147427 A KR 20160147427A
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semiconductor layer
layer
temperature
substrate
polarity
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KR1020150084161A
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Korean (ko)
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허정훈
한창석
최효식
김화목
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서울바이오시스 주식회사
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Publication of KR20160147427A publication Critical patent/KR20160147427A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

An ultraviolet light emitting element and a method for fabricating the same are disclosed. According to the present invention, a first semiconductor layer of a column shape is grown at a first temperature. The column shape of the first semiconductor layer is maintained on the first semiconductor layer at a second temperature. A second semiconductor layer doped with a first polarity is grown. A third semiconductor layer doped with the first polarity is grown on the second semiconductor layer at a third temperature higher than the second temperature. The doping concentration of the third semiconductor layer is higher than the doping concentration of the second semiconductor layer. The third semiconductor layer has a cone shape or a cone shape of which the upper part is cut. So, the ultraviolet light emitting element with excellent light extraction efficiency can be provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a UV light emitting device,

The present invention relates to an ultraviolet light-emitting device and a method of manufacturing the same.

In general, a light emitting diode is an inorganic semiconductor device that emits light generated by recombination of electrons and holes. Particularly, an ultraviolet light emitting diode that emits light in the ultraviolet (UV) region is small in size, low in maintenance cost, Has replaced traditional mercury lamps and is increasingly used in a variety of applications including sterilization, curing, medical applications, and security applications.

The ultraviolet light emitting diode emits light with a relatively short peak wavelength (400 nm or less). When such an ultraviolet light emitting diode is manufactured, an active layer is formed by using a material having a band gap energy corresponding to the relatively short peak wavelength to emit light. For example, when an active layer is formed using a semiconductor, aluminum gallium nitride (AlGaN) having an aluminum (Al) content of 10% or more is used.

When the band gap energy of the n-type and p-type semiconductor layers is smaller than the energy of ultraviolet light emitted from the active layer, the ultraviolet light emitted from the active layer can be absorbed by the n-type and p-type semiconductor layers in the light emitting diode. Therefore, not only the active layer of the ultraviolet light emitting diode, but also other semiconductor layers located in the light emitting direction of the light emitting diode are made to have an Al content of 10% or more.

When ultraviolet light generated in the active layer is emitted to the outside, light incident at an angle of more than a critical angle due to a difference in refractive index between the nitride based semiconductor material and the outside is reflected and then totally reflected inside the device, .

In order to solve such a problem, the exposed semiconductor layer is WET-etched using an etchant such as KOH, NaOH, H 2 O 2 or the like to form a cone on the surface to improve the light extraction efficiency of the ultraviolet light- There was an attempt.

However, in the case of the semiconductor layer having a high Al content, the height of the cones formed by the WET etching is low and the shape thereof is not uniform, and there is a limitation in increasing the light extraction efficiency.

SUMMARY OF THE INVENTION The present invention provides an ultraviolet light emitting device having excellent light extraction efficiency and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a method of manufacturing an ultraviolet light emitting device, the method including: loading a substrate into a chamber; Growing a first semiconductor layer in the form of a column at a first temperature; Growing a second semiconductor layer doped with a first polarity on the first semiconductor layer at a second temperature while maintaining the columnar shape of the first semiconductor layer; And growing a third semiconductor layer doped with the first polarity on the second semiconductor layer at a third temperature higher than the second temperature, And the third semiconductor layer may be a cone shape or an upper cone shape.

The method of manufacturing an ultraviolet light emitting device of an embodiment of the present invention may further include forming an undoped buffer layer on the substrate at a fourth temperature lower than the first temperature before the growth of the first semiconductor layer have.

The method of manufacturing an ultraviolet light emitting device according to an embodiment of the present invention may further include the step of growing a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer at a fifth temperature higher than the first temperature .

In one embodiment of the present invention, the second semiconductor layer may grow at a first pressure, and the third semiconductor layer may grow at a second pressure lower than the first pressure.

In the method of manufacturing an ultraviolet light emitting device according to an embodiment of the present invention, the second and third semiconductor layers include AlInGaN, the second and third semiconductor layers have the same Al composition ratio, or the Al The composition ratio may be higher than the Al composition ratio of the second semiconductor layer.

A method of manufacturing an ultraviolet light-emitting device according to an embodiment of the present invention includes: forming an active layer that emits light in an ultraviolet region on the third semiconductor layer; And forming a fifth semiconductor layer having a polarity opposite to that of the third semiconductor layer on the active layer.

A method of manufacturing an ultraviolet light emitting device according to an embodiment of the present invention includes: forming a supporting substrate on the fifth semiconductor layer; And removing the substrate and the first semiconductor layer to expose the second semiconductor layer.

The method of manufacturing an ultraviolet light emitting device according to an embodiment of the present invention may further include a step of performing surface etching on the second semiconductor layer to expose a cone-shaped third semiconductor layer.

According to another aspect of the present invention, there is provided an ultraviolet light emitting device comprising: a substrate; A first polarity semiconductor layer disposed on the substrate; An active layer disposed on the first polarized semiconductor layer and emitting light in an ultraviolet region; And a second polarity semiconductor layer disposed on the active layer and having a plurality of cones formed on one surface thereof and having a polarity opposite to that of the first polarity semiconductor layer, wherein an Al composition ratio of the second polarity semiconductor layer is substantially 10 % ≪ / RTI >

According to another aspect of the present invention, there is provided an ultraviolet light emitting device comprising: a substrate; A first semiconductor layer disposed on the substrate; An active layer disposed on the first semiconductor layer and emitting light in an ultraviolet region; A second semiconductor layer disposed on the active layer, the second semiconductor layer having a cone shape or an inverted cone shape, the polarity of which is opposite to that of the first semiconductor layer; And a third semiconductor layer disposed on the second semiconductor layer, the third semiconductor layer having the same polarity as the second semiconductor layer and having a higher doping concentration than the second semiconductor layer.

In one embodiment of the invention, the cone shape may include hexagonal or truncated hexagonal cone shapes.

The ultraviolet light-emitting device of one embodiment of the present invention may further include an undoped fourth semiconductor layer between the substrate and the first semiconductor layer.

In one embodiment of the present invention, the first and second semiconductor layers include AlInGaN, the first and second semiconductor layers have the same Al composition ratio, or the second semiconductor layer has an Al composition ratio of the first May be higher than the Al composition ratio of the semiconductor layer.

The present invention as described above has an effect of improving the light extraction efficiency because the semiconductor layer having a high Al composition can be formed with a high height and a uniform cone by surface etching.

FIG. 1 is an exemplary diagram for explaining the relationship between the growth temperature, the growth pressure, and the flow rate of the n-type dopant source according to the growth time in one embodiment of the present invention.
2 to 12 are cross-sectional views illustrating a method of manufacturing an ultraviolet light-emitting device according to an embodiment of the present invention.
FIG. 13 is an exemplary view for explaining the relationship between the growth temperature, the growth pressure, and the flow rate of the n-type dopant source according to the growth time according to another embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "on top" or "on" another element, it is understood that each element is referred to as being "directly on top" But also includes the case where there are other components in between. Like reference numerals designate like elements throughout the specification.

The composition ratios, growth methods, growth conditions, thicknesses, and the like for the semiconductor layer described below are examples, and the present invention is not limited by the description below. For example, when it is represented by aluminum gallium nitride (AlGaN), the composition ratio of aluminum (Al) and gallium (Ga) can be variously applied according to the needs of ordinary artisans.

In addition, the semiconductor layer described below can be grown using various methods generally known to those skilled in the art, including, for example, metal organic chemical vapor deposition (MOCVD), molecular beam And may be grown using molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HVPE). However, in the embodiment described below, it will be described that the semiconductor layer is grown in the same chamber using MOCVD.

In the growth process of the semiconductor layer, the source introduced into the chamber may be a source known to the ordinarily skilled artisan. For example, the Ga source may be trimethyl gallium (TMGa) or triethyl gallium (TEGa), and the Al source may be trimethyl aluminum (TMA) or triethyl aluminum (TEA). Also, the N source may be ammonia (NH 3 ). However, the present invention is not limited thereto, and various sources may be used.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is an exemplary view for explaining the relationship between the growth temperature, the growth pressure, and the flow rate of the n-type dopant source in the method of manufacturing an ultraviolet light-emitting device according to an embodiment of the present invention.

As shown in the drawing, a cleaning process may be performed in which the growth substrate is first loaded into a chamber, and then the substrate is annealed in a hydrogen atmosphere for a predetermined time at a temperature T A to remove an oxide film on the substrate surface (A).

Thereafter, the temperature in the chamber can be lowered to T D , and a GaN layer can be formed at a low temperature (B). Semiconductor materials such as gallium nitride (GaN) typically grow on a sapphire substrate because there is no substrate with a matching lattice constant and thermal expansion coefficient, wherein the lattice constant and thermal expansion coefficient between the sapphire substrate and the semiconductor material grown thereon To prevent the lowering of the crystallinity, a thin GaN layer is formed at a low temperature.

At this time, when the GaN buffer layer is grown on the sapphire substrate, the columnar GaN crystal is primarily grown. Then, the GaN layer as a seed (seed), increasing the temperature in the chamber up to T C, to be flat in the lateral secondary growth and slightly lower than the re-T A (C), after the determination of a certain thickness growth T B , the GaN layer can grow (D).

At this time, when the temperature is increased to T B and the pressure is lowered (P B ), crystal growth of a relatively flat single crystal becomes possible.

Thereafter, the n-type semiconductor layer of the present invention can be first grown on the undoped GaN layer, but the n-type semiconductor layer can be grown at T C lower than the growth temperature T B of the GaN layer (E). At this time, the pressure again grows under the condition of P A , and the flow rate of an n-type dopant source (for example, sealant (SiH 4 )) introduced into the chamber may correspond to F A.

When the growth temperature of the n-type semiconductor layer is lowered, the ratio of the vertical growth rate to the horizontal growth rate is increased to grow in an island-like manner, and then a doping layer may be formed on the upper and side surfaces of the grown island by doping.

Since the region where the doping is formed has a higher etching rate than the undoped region, the shape of the surface etching along the island shape can be determined. Thus, the primary growth time of the n-type semiconductor layer can be determined according to the depth of the cone produced by the surface etching. By the primary growth of the n-type semiconductor layer, a cone-shaped or cone-shaped cone-shaped structure can be formed. The cone-shaped or cone-shaped cone-shaped structures are connected to each other, so that a concave cone shape can be formed at the connecting portion. At this time, the cone shape may be hexagonal horns. This will be described in more detail with reference to the drawings.

Thereafter, the temperature can be increased again to T B , the pressure can be lowered to P B , and the n-type semiconductor layer can be secondary grown (F). The flow rate of the n-type dopant source introduced into the chamber may correspond to F B lower than F A. By such secondary growth, an n-type semiconductor layer can be formed in a flat shape on the top of a cone-shaped or top-cut cone-shaped structure formed by primary growth.

By forming the n-type semiconductor layer in this way, the n-type semiconductor layer of low concentration is etched in the surface etching process, and cones of a desired height can be formed.

2 to 12 are cross-sectional views illustrating a method of manufacturing an ultraviolet light-emitting device according to an embodiment of the present invention.

2, the GaN layer 20 may be formed on the substrate 10 according to the manufacturing method of the present invention.

The substrate 10 is not limited as long as it is a substrate for growing a semiconductor layer. For example, sapphire, silicon carbide, spinel, or nitride such as GaN or AlN. In one embodiment of the present invention, the substrate 10 may comprise, but is not limited to, sapphire. The substrate 10 can be subjected to cleaning by heat treatment at T A in Fig.

The undoped GaN layer 20 may be grown on the substrate 10 in the form of a column with a thickness of about 3 탆 or less, and may be grown to a thickness of, for example, 1 탆. When the Figure 1 as a reference, GaN layer 20, and under P A pressure, by a low temperature growth at a temperature T D is a buffer layer for the seed is formed, and after raising the temperature to T C starts to be flat to grow laterally, When crystals of a certain thickness are grown, the temperature can be increased up to T B to grow flat. At this time, at the temperature T B , the pressure can be lowered to P A to enable smooth growth. That is, the sections B to D are the sections for the growth of the buffer layer.

Referring to FIG. 3, the first n-type semiconductor layer 32 may be grown on the GaN layer 20. At this time, the first n-type semiconductor layer 32 may be formed in a cone shape or an upper cone shape. The cone-shaped or cone-shaped cone-shaped structures are connected to each other, so that a concave cone shape can be formed at the connecting portion.

The 1n-type semiconductor layer 32 is Al x Ga (1-x) N (0 <x <1) may be, n-type dopant is SiH 4 is injected into the chamber a silicon (Si) doped Al x Ga (1-x) N thin film can be grown. In the first n-type semiconductor layer 32, the composition ratio of Al can be very high, for example, 10% or more or 40% or less.

The growth time of the first n-type semiconductor layer 32 can be determined in proportion to the height of the desired cone.

At this time, the first n-type semiconductor layer 32 is grown at a temperature T B lower than T A and a pressure P A higher than P B , and the flow rate of the n-type dopant source is F A &lt; / RTI &gt;

Referring to FIG. 4, a second n-type semiconductor layer 35 may be grown on the first n-type semiconductor layer 32. The second n-type semiconductor layer 35 is formed of the same material as the first n-type semiconductor layer 32 or the second n-type semiconductor layer 35 has a higher Al composition than that of the first n- .

Further, the flow rate of the n-type dopant source to be injected may be smaller than the flow rate of the n-type dopant source at the time of forming the first n-type semiconductor layer 32. Thereby, the doping concentration of the first n-type semiconductor layer 32 may be higher than the doping concentration of the second n-type semiconductor layer 35. That is, the first n-type semiconductor layer 32 can be highly doped with the second n-type semiconductor layer 35 relatively.

The first and second n-type semiconductor layers 32 and 35 may form the n-type semiconductor layer 30 in the light emitting device of the embodiment of the present invention.

The first n-type semiconductor layer 32 is etched by subsequent surface etching. When the first n-type semiconductor layer 32 is etched, a cone structure is formed in the second n- .

Referring to FIG. 1 in detail, it can be seen that, in the growth of the first n-type semiconductor layer 32, the pressure rises in a falling temperature range. At this time, it can be seen that the n-type dopant source can be introduced into the chamber at a flow rate of F A when the temperature drop or pressure rise is completed at the set temperature or pressure.

Further, in the growth of the second n-type semiconductor layer 35, the pressure falls in the rising section of the temperature, and when the temperature rise or pressure drop is completed at the set temperature or pressure, the flow rate of the n- .

On the other hand, the first n-type semiconductor layer 32 and the second n-type semiconductor layer 35 may have different growth rates due to differences in growth pressure.

However, the present invention is not limited thereto, and the flow rate of the dopant may be changed while changing the temperature and the pressure, , The temperature and the introduction flow rate of the dopant may be changed while the pressure is not changed. Alternatively, the temperature may not be changed while varying the pressure and the introduction flow rate of the dopant. In either case, the crystallinity of the second n-type semiconductor layer 35 and the crystallinity of the first n-type semiconductor layer 32 may be different from each other, The etching rate of the first n-type semiconductor layer 32 is increased in the subsequent surface etching step, and a plurality of cones having a high height and a uniform shape can be easily formed.

5, the active layer 40 and the p-type semiconductor layer 50 may be formed on the n-type semiconductor layer 30.

The active layer 40 may include (Al, Ga, In) N and may emit light having a peak wavelength of a desired ultraviolet region by controlling the composition ratio of the semiconductor. The active layer 40 may be formed of a multiple quantum well structure (MQW) including alternately stacked barrier layers and well layers. For example, the active layer 40 can be provided by growing a four-component semiconductor such as AlInGaN to constitute a barrier layer and a well layer under a temperature condition of about 700 to 1000 DEG C and a pressure of about 100 to 400 Torr.

In addition, the barrier layer closest to the n-type semiconductor layer 30 may have a higher Al content than other barrier layers. By forming the barrier layer closest to the n-type semiconductor layer 30 to have a band gap larger than that of the other barrier layers, it is possible to effectively reduce electron overflow by decreasing the electron migration rate. In addition, the barrier layer close to the n-type semiconductor layer 30 may be thicker than some other barrier layers, and the final barrier layer may have an Al composition that is thicker or higher than some other barrier layers. For example, the first and second barrier layers may be thicker than the third barrier layer, and the last barrier layer may be thicker than the third barrier layer.

The p-type semiconductor layer 50 may be grown on the active layer 40 and may be formed to a thickness of about 0.2 μm or less at a temperature of 900 to 1000 ° C. and a pressure of about 100 to 400 Torr. The p-type semiconductor layer 50 may include a nitride semiconductor such as AlGaN, for example, biscyclopentadienyl magnesium (C 5 H 5 ) 2 Mg) is injected into the chamber to form a Mg-doped p-type nitride A semiconductor layer can be formed.

Furthermore, the p-type semiconductor layer 50 may further include a delta doping layer (not shown) for lowering ohmic contact resistance, and may further include an electron blocking layer (not shown). The electron blocking layer may comprise an AlGaN layer.

Further, the electron blocking layer may include a first electron blocking layer (not shown) and a second electron blocking layer (not shown) disposed on the first electron blocking layer, and the first electron blocking layer may include a second electron blocking layer An Al composition ratio higher than that of the barrier layer can be obtained.

Referring to FIG. 6, a supporting substrate 60 may be formed on the p-type semiconductor layer 50.

The supporting substrate 60 may be an insulating substrate, a conductive substrate, or a circuit substrate. For example, the support substrate 60 may be composed of any one of sapphire, GaN, glass, silicon carbide, silicon, a metal, a laminated structure of a plurality of metals, an alloy, and ceramics. The supporting substrate 60 may be bonded to the p-type semiconductor layer 50 so that a bonding layer (not shown) for bonding the supporting substrate 60 and the p-type semiconductor layer 50 therebetween is formed. Can be formed.

The bonding layer may comprise a metallic material. For example, the bonding layer may comprise gold-tin (AuSn) and the bonding layer comprising AuSn may be process bonded to the supporting substrate 60 and the p-type semiconductor layer 50. When the supporting substrate 60 is a conductive substrate, the bonding layer may be configured to electrically connect the p-type semiconductor layer 50 and the supporting substrate 60.

Further, a metal layer (not shown) may be further formed between the supporting substrate 60 and the p-type semiconductor layer 50.

The metal layer may include a reflective metal layer (not shown) and a barrier metal layer (not shown), and a barrier metal layer may be formed on the reflective metal layer.

The reflective metal layer may be formed through deposition and lift-off. The reflective metal layer may serve to reflect light and may serve as an electrode electrically connected to the p-type semiconductor layer 50. Thus, the reflective metal layer preferably comprises a material capable of forming an ohmic contact with high reflectivity to ultraviolet light. That is, the reflective metal layer may be formed of, for example, Ni, Pt, Pd, Rh, W, Ti, Al, Ag, ). &Lt; / RTI &gt;

The barrier metal layer can prevent interdiffusion of the reflective metal layer and other materials. Thus, it is possible to prevent an increase in contact resistance and a reduction in reflectivity due to damage to the reflective metal layer. The barrier metal layer may include Ni, Cr (Cr), Ti, W, and may be formed of multiple layers.

Thereafter, referring to FIG. 7, the substrate 10 can be separated from the GaN layer 20. At this time, the substrate 10 can be removed by laser lift off (LLO). That is, when the excimer laser light having the wavelength of the predetermined region is irradiated onto the substrate 10 and the irradiation is focused, thermal energy is concentrated on the interface between the substrate 10 and the GaN layer 20 so that the interface of the GaN layer 20 becomes Ga and N Separation of the substrate 10 may occur instantaneously at a portion where laser light passes while being separated into molecules. However, this is an example, and the removal of the substrate 10 is not performed only by the LLO, but may be separated by various methods such as chemical lift off, stress lift off, thermal lift off, and the like. 8 shows a semiconductor layer in a state where the substrate 10 is removed. The GaN layer 20 is removed and one side of the n-type semiconductor layer 30 is exposed. That is, one surface of the first n-type semiconductor layer 32 is exposed.

9, when a chemical solution is used for surface etching while one surface of the n-type semiconductor layer 30 is exposed, the doping concentration is selectively high or the growth pressure is low and the crystallinity is low Since the etching rate of the first n-type semiconductor layer 32 is high, it can be etched first. Therefore, etching is performed along the doped region formed along the top or side surface of the island to increase the height or density of the etched cone, which improves the light extraction efficiency.

At this time, the surface etching may be WET etching using, for example, photo-enhanced chemical (PEC) or an etchant such as KOH, NaOH, H 2 O 2 or the like, and various other surface etching methods may be used .

Referring to FIG. 10, the first n-type semiconductor layer 32 is etched first, and thus the second n-type semiconductor layer 35 remains, thereby forming the cone A. Referring to FIG.

The cone thus formed can be formed at a desired height even in the n-type semiconductor layer 30 having a high Al composition ratio, so that the light extraction efficiency of the ultraviolet light emitting device of the present invention can be improved.

Referring to FIG. 11, the device dividing trench 80 can be formed by patterning the n-type semiconductor layer 30, the active layer 40, and the p-type semiconductor layer 50. The upper surface of the supporting substrate 60 can be partially exposed by forming the element dividing grooves 80 and further the n type electrodes 70 are formed on the respective element regions divided by the element dividing grooves 80 . The patterning of the n-type semiconductor layer 30, the active layer 40 and the p-type semiconductor layer 50 may be performed by etching or the side surface of the element isolation trench 80 may have a predetermined inclination .

The n-type electrode 70 may supply external power to the n-type semiconductor layer 30 and may be formed using a deposition and lift-off technique.

Subsequently, by separating the supporting substrate 60 in the region under each element dividing groove 80 along S1, the ultraviolet light emitting element 1 as shown in Fig. 12 can be provided.

According to this embodiment of the present invention, a cone having a high height can be formed by surface etching even for a semiconductor layer having a high Al composition, and the light extraction efficiency can be improved. Further, according to the embodiment of the present invention, since the semiconductor layer having a high Al composition can be formed with a cone having a uniform height even by performing surface etching, the light extraction efficiency can be improved.

FIG. 13 is an exemplary view for explaining the relationship between the growth temperature, the growth pressure, and the flow rate of the n-type dopant source according to the growth time according to another embodiment of the present invention. The embodiment of FIG. 13 is generally similar to the embodiment described with reference to FIG. 1 and differs in that the growth temperature and growth pressure of the GaN layer 20 are constant. Hereinafter, differences will be mainly described.

Referring to FIG. 13, the substrate 10 is subjected to a cleaning process by heat-treating the substrate 10 in a hydrogen atmosphere at a high temperature for a predetermined period of time.

Next, the GaN buffer layer can be formed by lowering the temperature in the growth chamber to a low temperature. Then, the GaN layer 20 may be formed on the GaN buffer layer using the GaN buffer layer as a seed layer. Unlike the case of FIG. 1, the GaN layer 20 is first grown at a somewhat low temperature, It can grow at one time at a high temperature without secondary growth. At this time, unlike the embodiment of FIG. 1 in which a high pressure is maintained at a rather low temperature and a low temperature is maintained at a higher temperature, when the temperature rises, the pressure can be lowered to grow the GaN layer 20.

The subsequent description is the same as described above, so a detailed description will be omitted.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Accordingly, the true scope of the present invention should be determined by the following claims.

10: substrate 20: GaN layer
32, 35: n-type semiconductor layer 40: active layer
50: p-type semiconductor layer 60:
70: Electrode

Claims (13)

Loading a substrate into a chamber;
Growing a first semiconductor layer in the form of a column at a first temperature;
Growing a second semiconductor layer doped with a first polarity on the first semiconductor layer at a second temperature while maintaining the columnar shape of the first semiconductor layer; And
Growing a third semiconductor layer doped with the first polarity on the second semiconductor layer at a third temperature higher than the second temperature,
Wherein a doping concentration of the third semiconductor layer is higher than a doping concentration of the second semiconductor layer, and the third semiconductor layer has a cone shape or an upper cone shape.
The method according to claim 1,
Further comprising forming an undoped buffer layer on the substrate at a fourth temperature lower than the first temperature before the growth of the first semiconductor layer.
The method according to claim 1,
Further comprising growing a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer at a fifth temperature higher than the first temperature.
2. The method of claim 1, wherein the second semiconductor layer is grown at a first pressure and the third semiconductor layer is grown at a second pressure lower than the first pressure.
The semiconductor laser device according to claim 1, wherein the second and third semiconductor layers include AlInGaN, the second and third semiconductor layers have the same Al composition ratio, or the third semiconductor layer has an Al composition ratio of the second semiconductor layer Wherein the Al composition ratio is higher than the Al composition ratio.
The method according to claim 1,
Forming an active layer for emitting light in an ultraviolet region on the third semiconductor layer; And
And forming a fifth semiconductor layer having a polarity opposite to that of the third semiconductor layer on the active layer.
The method according to claim 6,
Forming a support substrate on the fifth semiconductor layer; And
And removing the substrate and the first semiconductor layer to expose the second semiconductor layer.
The method according to claim 6,
And performing a surface etching on the second semiconductor layer to expose the third semiconductor layer in the shape of a cone.
Board;
A first polarity semiconductor layer disposed on the substrate;
An active layer disposed on the first polarized semiconductor layer and emitting light in an ultraviolet region; And
A second polarity semiconductor layer disposed on the active layer and having a plurality of cones formed on one surface thereof and having a polarity opposite to that of the first polarity semiconductor layer,
And an Al composition ratio of the second polarity semiconductor layer is substantially 10% or more.

Board;
A first semiconductor layer disposed on the substrate;
An active layer disposed on the first semiconductor layer and emitting light in an ultraviolet region;
A second semiconductor layer disposed on the active layer, the second semiconductor layer having a cone shape or an inverted cone shape, the polarity of which is opposite to that of the first semiconductor layer; And
And a third semiconductor layer disposed on the second semiconductor layer and having the same polarity as the second semiconductor layer and having a higher doping concentration than the second semiconductor layer.
The ultraviolet light emitting device according to claim 10, wherein the cone shape comprises a hexagonal horn or a truncated hexagonal horn.
11. The method of claim 10,
Further comprising an undoped fourth semiconductor layer between the substrate and the first semiconductor layer.
11. The method of claim 10, wherein the first and second semiconductor layers include AlInGaN, the first and second semiconductor layers have the same Al compositional ratio, or the second semiconductor layer has an Al composition ratio of the first semiconductor layer Is higher than the Al composition ratio of the ultraviolet light emitting element.
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