KR20150111390A

KR20150111390A - Thin Film Transistor comprising double layer gate insulator and fabricating method thereof

Info

Publication number: KR20150111390A
Application number: KR1020140032709A
Authority: KR
Inventors: 정재경; 제소연; 손병근
Original assignee: (주)디엔에프
Priority date: 2014-03-20
Filing date: 2014-03-20
Publication date: 2015-10-06

Abstract

The present invention relates to a thin film transistor and to a manufacturing method thereof. The thin film transistor according to an embodiment of the present invention comprises: an activated layer including at least one oxide among indium (in), zinc (Zn), tin (Sn), aluminum (Al), magnesium (Mg), hafnium (Hf), gallium (Ga) and titanium (Ti); a gate insulator arranged on top of the activated layer; a gate conductive film overlapping with at least part of the activated layer with the gate insulator therebetween; and a thin film transistor including source and drain regions formed at both side parts of the activated layer, which are separated by the conductive film. The gate insulator includes: a lower insulator including silicon (Si) and having excellent electrical characteristics; and an upper insulator including an oxide of at least one among zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti) and lanthanum (La) and having excellent dielectric characteristics.

Description

[0001] The present invention relates to a thin film transistor including a double layer gate insulator and a method of manufacturing the same,

The present invention relates to a semiconductor device, and more particularly, to a thin film transistor including a double-layer gate insulating film and a method of manufacturing the same.

Metal oxide thin film transistors (TFTs) have advantages of high mobility, transparency to visible light, and low temperature processability compared to amorphous silicon thin film transistors, so that flexible, foldable and / or transparent And is a semiconductor device noticed as a switching device for information display. In order to use a plastic substrate for the flexible display, all processes such as deposition and heat treatment must be performed at a low temperature of 250 ° C or less to prevent deformation or warping of the plastic substrate.

Since conventional sputtered semiconductor oxide films can be manufactured at room temperature, it is simple to fabricate a plastic-compatible metal oxide channel layer with high mobility in the case of metal oxide semiconductors. However, a high quality gate dielectric layer, such as SiO ₂ , must be deposited at a high temperature above 300 ° C using an expensive vacuum-based PECVD system. Recently, a wet process gate dielectric layer comprising Al ₂ O ₃ , Y ₂ O ₃ , HfO ₂ and ZrO ₂ has been intensively studied for low cost fabrication. Although metal oxide thin film transistors with gate dielectrics in wet processes achieve good results, high annealing temperatures above 300 DEG C are still required to provide a reasonable gate leakage current and low off-state drain current.

Further, in order to be used in a flexible display, a thin film transistor must be bent or folded to a thickness of 1 mm or less. In this case, more mechanical defects are generated in the contact film, such as the gate insulating film, than the separation film such as the channel and the electrode region. Therefore, from the viewpoint of mechanical stability, it is preferable to use the polymer organic film for the insulating film of the metal oxide thin film transistor.

However, there is a problem that the organic insulating film can not be treated at high temperature, and when using an organic solvent for modifying the surface of the insulating film, the surface characteristics of the organic insulating film are rather deteriorated. In addition, when an organic insulating film is used in the manufacture of a device, there is a disadvantage that the device can exhibit hysteresis.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a thin film transistor including a dual-layer gate insulating film made of materials and structures that improve device characteristics such as mobility, sub-threshold gate swing, threshold voltage, and Ion / .

Another object of the present invention is to provide a method of manufacturing a thin film transistor including a double-layer gate insulating film having a flexible characteristic in a low-temperature wet process and having good oxide semiconductor and interface characteristics.

In order to achieve the above object, the present invention provides a thin film transistor comprising at least one of indium, zinc, tin, aluminum, magnesium, hafnium, gallium, and titanium, An active layer containing at least one of oxides; A gate insulating film disposed on the active layer; A gate conductive layer overlapping at least a part of the active layer with the gate insulating film interposed therebetween; And And a thin film transistor including source and drain regions formed on both sides of the active layer spaced apart by the conductive film, wherein the gate insulating film includes a lower insulating film including silicon (Si) and having excellent electrical characteristics; And an upper insulating film containing an oxide of at least one of zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti) and lanthanum have.

The thin film transistor may have a top gate structure in which the gate insulating film and the gate conductive film are sequentially formed on the active layer. Alternatively, the thin film transistor may have a bottom gate structure in which the gate insulating film and the active layer are sequentially formed on the gate conductive film.

The lower insulating layer may be a silicon oxide layer, and the upper insulating layer may include a high dielectric constant dielectric layer having a higher dielectric constant than the silicon oxide layer.

The lower insulating layer may have a thickness of 1 to 10 mm, and the upper insulating layer may have a thickness of 1 to 10 mm.

At least one of the source and drain electrodes may include a transparent conductive oxide thin film.

The transparent conductive oxide thin film may include at least one selected from the group consisting of Indium-Zinc-Oxide (IZO), Indium-Tin-Oxide (ITO), Fluorinated Tin Oxide (Indium Oxide) and tin oxide (SnO2), or a combination thereof.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, including: forming a gate conductive layer over a gate insulating layer disposed on an active layer to overlap with at least a portion of the active layer; And source and drain electrodes respectively connected to both sides of the active layer spaced apart by the gate conductive film, the method comprising: providing a substrate on which the thin film transistor is to be formed; Forming a lower insulating film including silicon oxide on the substrate; And an upper dielectric layer including an oxide of at least one of zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and lanthanum (La) And may include an insulating film.

According to the embodiment of the present invention, it is possible to provide a thin film transistor having improved performance such as a subthreshold swing and a threshold voltage by including a multilayer insulating film including silicon oxide and an inorganic insulator .

According to another embodiment of the present invention, a method of manufacturing a thin film transistor having a flexible and stable device characteristic can be provided by forming a gate insulating film using a solution process. Also, by providing a multi-layered gate insulating film, it is possible to provide a thin film transistor manufacturing method capable of improving the interfacial characteristics with the channel at low process temperatures, having a low sub-threshold gate swing value, .

1A and 1B are cross-sectional views respectively showing thin film transistors according to an embodiment of the present invention.
2A to 2C show the source-drain currents of the thin film transistors according to Comparative Examples 1 and 2 and Experimental Example of the present invention.
3A and 3B are atomic force microscope (AFM) images of the gate insulating film of Comparative Example 1 and Experimental Example of the present invention.

Hereinafter, the present invention will be described in more detail with reference to examples.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed and will become apparent to those skilled in the art. It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

In the following drawings, thickness and size of each layer are exaggerated for convenience and clarity of description, and the same reference numerals denote the same elements in the drawings. As used herein, the term "and / or" includes any and all combinations of any of the listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" include singular forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups.

In the following description, when a layer is described as being "on" another layer, it refers to a layer formed directly on top of another layer, or to a layer formed on an intermediate or intermediate layer formed on another layer You may. It will also be appreciated by those skilled in the art that structures or shapes that are "adjacent" to other features may have portions that overlap or are disposed below the adjacent features.

As used herein, the terms "below," "above," "upper," "lower," "horizontal," or " May be used to describe the relationship of one constituent member, layer or regions with other constituent members, layers or regions, as shown in the Figures. It is to be understood that these terms encompass not only the directions indicated in the Figures but also the other directions of the devices.

Although the terms first, second, etc. are used herein to describe various elements, components, regions, layers and / or portions, these members, components, regions, layers and / It is obvious that no. These terms are only used to distinguish one member, component, region, layer or section from another region, layer or section. Thus, a first member, component, region, layer or section described below may refer to a second member, component, region, layer or section without departing from the teachings of the present invention.

As used herein, the term " unstructured structure "generally refers to an amorphous structure having a low degree of orderliness in which atoms lack definite periodic arrangements, including structures in which microcrystals are formed in the amorphous structure .

In the following, embodiments of the present invention will be described with reference to cross-sectional views schematically illustrating ideal embodiments (and intermediate structures) of the present invention. In these figures, for example, the size and shape of the members may be exaggerated for convenience and clarity of explanation, and in actual implementation, variations of the illustrated shape may be expected. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein. In addition, reference numerals of members in the drawings refer to the same members throughout the drawings.

1A and 1B are cross-sectional views respectively showing thin film transistors according to an embodiment of the present invention.

Referring to FIGS. 1A and 1B, thin film transistors 100 and 200 are formed on a substrate 10. The substrate 10 may be selected from a material that is compatible with the formation process of the thin film transistors 100 and 200 and can provide an insulating surface on which the thin film transistors 100 and 200 are to be formed. For example, the substrate 10 can be a III-V compound semiconductor such as GaAs, or a II-VI semiconductor such as CdS, May be formed of a material. However, these are only illustrative, and the present invention is not limited thereto. For example, the substrate 10 may be formed of a metal sheet coated with a ceramic material or an insulating film such as aluminum oxide.

In some embodiments, the substrate 10 may be a translucent material. The transparent material may be glass or a resin-based material. A substrate formed of a resin material is preferable because it has flexibility. The resin material may be a polyester resin such as polyethylene naphthalate (PEN); Polyethylene resin; Polyvinyl chloride resin; Polycarbonate (PC); Polyethersulfone (PES); Polyetheretherketone (PEEK); And polyphenylene sulfide (PPS), or a combination thereof. The above-mentioned resin-based material is merely an example, and the present invention is not limited thereto.

In some embodiments, before the thin film transistors 100 and 200 are formed on the substrate 10, appropriate surface treatment is performed to remove impurities on the surface of the substrate 10 or to improve the diffusion or adherence characteristics of the impurities . For example, impurities can be removed from the surface of the substrate 10 by a plasma treatment or a cleaning process using a chemical liquid such as hydrogen peroxide, ethanol and acetone, or deionized water. An additional layer (not shown) such as a silicon oxide film, a metal oxide film, or a metal nitride film is formed on the substrate 10 in order to improve the diffusion and attachment characteristics of impurities generated between the substrate 10 and the thin film transistors 100 and 200 ) May be performed.

The thin film transistor 100 is formed on the substrate 10 prepared as described above. The thin film transistor 100 includes a gate conductive film 11a and source and drain electrodes 15a and 15b which are overlapped with at least a part of the active layer 14a through the active layer 14a and the gate insulating films 12a and 13a . In some embodiments, additional layers (not shown) for the ohmic contact may be further formed between the active layer 14a and the source and drain electrodes 15a and 15b.

In some embodiments, the thin film transistor 100 is formed by sequentially forming the gate insulating films 12a and 13a and the gate conductive film 11a on the active layer 14a as shown in FIG. 1A, . 1B, the thin film transistor 200 is formed so as to have a bottom gate structure in which the gate insulating films 12b and 13b and the active layer 14b are sequentially formed on the gate conductive film 11b . The structure of the thin film transistors 100 and 200 shown in FIGS. 1A and 1B is illustrative, and the present invention is not limited thereto. For example, the thin film transistor may have a double gate structure, as is well known in the art, and the source and drain electrodes 15a and 15b may be formed on the active layers 14a and 14b where the gate conductive films 11a and 11b are located, (Coplanar structure) disposed on the same plane as the plane of the first and second electrodes 14a and 14b.

In some embodiments, Ti, Cr, W, Ta, Mo, Ni, or their alloys may be used to improve adhesion characteristics between the gate insulating films 12a, 12b, 13a, 13b and the gate conductive films 11a, Additional selected layers (not shown) may be further formed.

The active layers 14a and 14b are formed of tin (Sn) which is an element constituting the main matrix and an oxide including at least any one of aluminum (Al), magnesium (Mg) and titanium (Ti). The present inventors experimentally and oxides operate with the N-type enhancement (enhanced) containing Sn and Al of the amorphous structure of, 0.4 cm ² / V · s or more field effect charge carrier mobility (μ _FE), 10 ⁶ degrees of I _{on / off} , and a threshold voltage of about 10.4V. This tendency is expected to be the same for magnesium and titanium of similar atomic size. This corresponds to a level that can be sufficiently applied as an active driving device of an actual display device or an image pickup device.

The active layers 14a and 14b including an oxide film containing tin (Sn) and at least any one of aluminum (Al), magnesium (Mg), and titanium (Ti) The characteristics of the thin film transistor having the same or better than the charge mobility characteristic obtained in the conventional amorphous silicon thin film transistor can be secured even when the temperature is lower than 200 ° C. The active layers 14a and 14b may be formed by a sol gel method, an electron beam deposition method, a laser ablation method, or a sputtering method capable of a low temperature deposition process. Accordingly, a lightweight resin-based flexible substrate as described above can be used in addition to the conventional glass substrate. In particular, when a flexible substrate is applied, a roll-to-roll process is possible, and thus a large-area deposition process of thin film transistors including an active layer is possible.

The gate insulating films 12a, 12b, 13a, and 13b in contact with the active layers 14a and 14b may be formed by a sputtering or atomic layer deposition process capable of a low temperature deposition process. The gate insulating films 12a, 12b, 13a and 13b are formed by sequentially forming lower insulating films 12a and 12b including silicon oxide having excellent electrical characteristics and upper insulating films 13a and 13b including high dielectric constant materials having a higher dielectric constant than silicon oxide . The upper insulating films 13a and 13b may be formed of at least one oxide or nitride selected from a high-permittivity material having a higher dielectric constant than silicon oxide, for example, Hf, Y, Al, Ta, Sn, La and Zr. Preferably, the upper insulating films 13a and 13b may be formed of an oxide film containing Zr and La. In some embodiments, the upper insulating films 13a and 13b may be formed by mixing a compound containing zirconium (Zr) and a compound containing lanthanum (La) in a ratio of 2: 1.

The upper insulating film and the lower insulating film may each have a thickness of 1 to 10 mm. The thickness of the lower insulating layer may be adjusted within the above range to prevent breakdown of the device. In addition, the upper insulating film and the lower insulating film can not only prevent the device from failing within the above range, but also improve the interface characteristics with the oxide semiconductor.

In some embodiments, after forming the upper insulating films 13a and 13b and / or the lower insulating films 12a and 12b, the gate insulating film including the upper insulating film and / or the lower insulating film may be subjected to heat treatment. The heat treatment may be performed at a temperature of 300 DEG C or lower. Thereafter, the heat-treated gate insulating film can be dried.

The gate conductive films 11a and 11b may be formed by depositing a metal layer by a method such as sputtering, electron beam evaporation, PECVD or CVD, and patterning the metal layer. The metal layer may be formed of, for example, Al, Au, Ag, Ti, Cu or an alloy thereof having low resistance and excellent thermal stability.

The source and drain electrodes 14a and 14b are connected to both sides of the active layers 13a and 13b, respectively. At least one of the source and drain electrodes 14a and 14b may be a transparent electrode. The transparent electrode may be formed of, for example, indium-zinc oxide (IZO), indium tin oxide (ITO), fluorinated tin oxide (FTO) A transparent conductive oxide such as indium oxide (IO) and tin oxide (SnO2), a transparent conductive resin such as polyacetylene, or a conductive resin containing conductive metal fine particles, or a combination thereof . The source and drain electrodes 14a and 14b may be formed by depositing a conductive film by PECVD, CVD, sputtering, electron beam evaporation, silk screening, inkjet or the like, patterning the conductive film, and further performing a heat treatment process.

Hereinafter, the specific characteristics and manufacturing method of the above-described insulating film will be described in detail with reference to experimental examples and various analysis results.

Comparative Example 1

In this experiment, high density doped silicon wafers were used as gates. First, a solution of perhydropolysilazane was spin-coated at 3000 rpm for 30 seconds, pre-baked at 150 ° C for 5 minutes, and subjected to H ₂ O steam annealing at 180 ° C for 1 hour to form a SiO ₂ thin film Respectively. The SiO 2 thin film was used as a single-layer gate insulating film, and an ITO electrode was stacked on the single-layer gate insulating film to form a capacitor to confirm JE and CV curves. IZO (Indium Tin Oxide) semiconductor channels were deposited on the single-layer gate insulating film using a sputtering process, and ITO (Indium Tin Oxide) S / D electrodes were deposited on the single-layer gate insulating film and annealed at 180 ° C for 1 hour.

Comparative Example 2

A 0.15 M ZrLaO 3 solution was prepared by dissolving zirconium chloride and lanthanum nitrate hexahydrate in ethanol at a ratio of 2: 1 using a high density doped silicon wafer as a gate, And coated at 5000 rpm for 30 seconds. Baked at 100 ° C for 10 minutes, and then heat-treated at 180 ° C for 1 hour. The J-E and C-V curves were confirmed by stacking ITO electrodes on the single-layer gate insulating film thus fabricated to fabricate capacitors. IZO (Indium Tin Oxide) semiconductor channels were deposited on the single-layer gate insulating film using a sputtering process, and ITO (Indium Tin Oxide) S / D electrodes were deposited on the single-layer gate insulating film and annealed at 180 ° C for 1 hour.

Experimental Example

In this experiment, high density doped silicon wafers were used as gates. First, a solution of perhydropolysilazane was spin-coated at 3000 rpm for 30 seconds, pre-baked at 150 ° C for 5 minutes, and subjected to H ₂ O steam annealing at 180 ° C for 1 hour to form a SiO ₂ thin film Respectively. Then, zirconium chloride and lanthanum nitrate hexahydrate were dissolved in ethanol at a ratio of 2: 1 (ZrCl ₄ : La (NO ₃ ) ₃ 6H ₂ O = 2: 1) to prepare a 0.15 M ZrLaO 3 solution And then coated by spin coating at 5000 rpm for 30 seconds. Baked at 100 ° C for 10 minutes, and then heat-treated at 180 ° C for 1 hour. A capacitor was fabricated by stacking ITO electrodes on the bilayer gate insulating film thus fabricated to confirm JE and CV curves. IZO (Indium Zinc Oxide) semiconductor channel was deposited on the double layer gate insulating film by sputtering, and ITO (Indium Tin Oxide) S / D electrode was deposited and annealed at 180 ℃ for 1 hour.

2A to 2C show the source-drain currents of the thin film transistors according to Comparative Examples 1 and 2 and Experimental Example of the present invention.

Referring to FIGS. 2A to 2C, the thin film transistor including the double layer gate insulating film of Experimental Example has a leakage current of 10 ³ to 10 ⁷ times as much as that of the thin film transistor including the single layer gate insulating film of Comparative Example 1 and Comparative Example 2 Low. The leakage current of the thin film transistor including the double layer gate insulating film of Experimental Example is about 10 ⁷ times lower than that of the thin film transistor of Comparative Example 2 including the ZrLaO gate insulating film of Comparative Example 2. Therefore, And the device characteristics are improved.

Table 1 shows the migration characteristics of the thin film transistor including the gate insulating film of Comparative Example 1 and Experimental Example. The mobility (μ _FE ), the subthreshold gate swing (SS), the threshold voltage (V _th ), and the ratio of Ion / off (I _{on / off} ratio) were measured as transfer characteristics.

Comparative Example 1 Experimental Example Mobility (㎠ / Vs) 21 20 Sub-threshold gate swing
(V / decade) 0.87 0.16 Threshold voltage (V) -3.25 -0.76 I _{on / off} Ratio 10 ⁶ 10 ⁷

Referring to Table 1, it can be seen that the threshold voltage of the thin film transistor of the experimental example is reduced by about 5 times as compared with the thin film transistor of the comparative example 1. [ Therefore, it can be seen that the characteristics of the double layered gate insulating film thin film transistor of the experimental example are remarkably improved as compared with the single layer gate insulating film thin film transistor including the silicon oxide or ZrLaO gate insulating film.

When a thin film transistor is manufactured in a low-temperature process, the density or purity of the thin film may be deteriorated and the device characteristics of the thin film transistor may be deteriorated. The thin film transistor including the double layer gate insulating film according to an embodiment of the present invention can prevent breakdown of the device by controlling the thickness of the lower insulating film including silicon oxide. In addition, by using an upper insulating film including an oxide of a material having high dielectric constant characteristics such as zirconium (Zr) and lanthanum (La), the interface characteristics with the oxide semiconductor can be improved and the characteristics of the thin film transistor can be improved.

3A and 3B are atomic force microscope (AFM) images of the gate insulating film of Comparative Example 1 and Experimental Example of the present invention. Referring to FIGS. 3A and 3B, it can be seen that the double-layer gate insulating film is coated at a higher density than the single-layer gate insulating film. Therefore, the thin film transistor including the double layer gate insulating film has a high purity due to low impurity content and a high density of the thin film, so that the device characteristics such as the mobility of the thin film transistor, the threshold voltage, and the sub threshold gate swing can be remarkably improved.

As described above, the lower insulating film including silicon (Si) and the lower insulating film including zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti) And an upper insulating film including an oxide of at least any one of the lanthanum (La) are improved in device characteristics such as mobility, threshold voltage, Ion / off ratio, and sub-threshold gate swing have. In addition, it can be used in a rollable flexible display since it is manufactured using a low temperature process.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be clear to those who have knowledge.

Claims

An active layer including an oxide of at least one of indium (In), zinc (Zn), tin (Sn), aluminum (Al), magnesium (Mg), hafnium (Hf), gallium (Ga), and titanium ;
A gate insulating film disposed on the active layer;
A gate conductive layer overlapping at least a part of the active layer with the gate insulating film interposed therebetween; And
And a thin film transistor including source and drain regions formed on both sides of the active layer spaced apart by the conductive film,
Wherein the gate insulating layer comprises a lower insulating layer containing silicon (Si) and having excellent electrical characteristics; And an upper insulating film containing an oxide of at least one of zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti) and lanthanum (La) transistor.

The method according to claim 1,
Wherein the thin film transistor has a top gate structure in which the gate insulating film and the gate conductive film are sequentially formed on the active layer.

The method according to claim 1,
Wherein the thin film transistor has a bottom gate structure in which the gate insulating film and the active layer are sequentially formed on the gate conductive film.

The method according to claim 1,
Wherein the lower insulating film is silicon oxide,
Wherein the upper insulating film comprises a high dielectric constant dielectric material having a higher dielectric constant than the silicon oxide.

The method according to claim 1,
Wherein the lower insulating layer has a thickness of 1 to 10 mm, and the upper insulating layer has a thickness of 1 to 10 mm.

The method according to claim 1,
Wherein at least one of the source and drain electrodes comprises a transparent conductive oxide thin film.

The method according to claim 6,
The transparent conductive oxide thin film may include at least one selected from the group consisting of Indium-Zinc-Oxide (IZO), Indium-Tin-Oxide (ITO), Fluorinated Tin Oxide (I), tin oxide (SnO2), or a combination thereof.

A gate conductive film overlying at least a part of the active layer through a gate insulating film disposed on the active layer; And source and drain electrodes connected to both sides of the active layer spaced apart by the gate conductive film, the method comprising the steps of:
Providing a substrate on which the thin film transistor is to be formed;
Forming a lower insulating film including silicon oxide on the substrate; And
And an upper insulating film including an oxide of at least one of zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and lanthanum (La) Wherein the thin film transistor is formed on the substrate.

9. The method of claim 8,
Wherein the lower insulating layer has a thickness of 1 to 10 mm, and the upper insulating layer has a thickness of 1 to 10 mm.

9. The method of claim 8,
Wherein the lower insulating film is silicon oxide,
Wherein the upper insulating film comprises a high dielectric constant dielectric material having a higher dielectric constant than the silicon oxide.

The method of claim 8, wherein
After forming the lower insulating film or the upper insulating film,
Heat treating the gate insulating film; And
And drying the heat-treated gate insulating film.

12. The method of claim 11,
Wherein the heat treatment is performed at a temperature of 300 DEG C or less.

9. The method of claim 8,
Wherein at least one of the source and drain electrodes comprises a transparent conductive oxide thin film.

14. The method of claim 13,
The transparent conductive oxide thin film may include at least one selected from the group consisting of Indium-Zinc-Oxide (IZO), Indium-Tin-Oxide (ITO), Fluorinated Tin Oxide (I), tin oxide (SnO2), or a combination thereof.