KR20150026406A - Method of manufacturing display substrate - Google Patents

Method of manufacturing display substrate Download PDF

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Publication number
KR20150026406A
KR20150026406A KR20130105187A KR20130105187A KR20150026406A KR 20150026406 A KR20150026406 A KR 20150026406A KR 20130105187 A KR20130105187 A KR 20130105187A KR 20130105187 A KR20130105187 A KR 20130105187A KR 20150026406 A KR20150026406 A KR 20150026406A
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KR
South Korea
Prior art keywords
substrate
base substrate
layer
protective film
pattern
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KR20130105187A
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Korean (ko)
Inventor
옥윤덕
강성호
노도영
Original Assignee
삼성디스플레이 주식회사
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Priority to KR20130105187A priority Critical patent/KR20150026406A/en
Publication of KR20150026406A publication Critical patent/KR20150026406A/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

A method for manufacturing a display substrate includes the steps of: attaching a protection film on a first surface of a base substrate; forming a display device and a driving device on a second surface of the base substrate; and separating the protection film which is attached on the base substrate. Thereby, the manufacturing process of the display substrate is performed by attaching the protection film on the base substrate. An additional etching process to reduce the thickness of the substrate is omitted. Therefore, manufacturing costs are reduced.

Description

[0001] METHOD OF MANUFACTURING DISPLAY SUBSTRATE [0002]

The present invention relates to a method of manufacturing a display substrate, and more particularly, to a method of manufacturing a display substrate that does not require an etching process for the substrate.

As the modern industrial society develops into a highly information age, the importance of the display industry, which visualizes various information from various devices and transmits them to humans, is increasing. This trend is expected to continue for some time to come. With the deepening, generalization and popularization of informatization, the desire for human information has also grown. Accordingly, in the field of display, which is a man-machine interface of information transmission, researches for expressing near-natural color and close-to-nature sophistication so as to satisfy a human visual sense, It is actively proceeding.

In general, displays are widely used, ranging from televisions, monitors, or mobile phones. However, there is a need for a display that is light in weight, has a large display area, is excellent in resolution, and has a high display speed.

In order to meet such a demand, efforts have been actively made to increase the size of the display device and to reduce the density and thickness of the substrate constituting the display device. Accordingly, in order to reduce the thickness of the product, an etching process for the substrate is required, which causes additional costs in the manufacturing process.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a display substrate capable of reducing manufacturing costs by omitting a step of further etching a substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a display substrate, including the steps of: bonding a protective film to a first surface of a base substrate; forming a driving element and a display element on a second surface of the base substrate; And separating the protective film adhered to the base substrate.

In one embodiment of the present invention, the protective film includes a support having a first side bonded to the base substrate and a second side opposite to the first side, and an adhesive layer formed on the first side of the support .

In one embodiment of the present invention, the thickness of the protective film may be 0.2 mm.

In one embodiment of the present invention, the support is formed of a material selected from the group consisting of polyimide, polyester, polyolefin, polyethylene terephthalate and polybutylenes terephthalate At least one material selected from the group consisting of:

In one embodiment of the present invention, the adhesive layer may have an adhesive strength in the range of 0.2 to 60 N / 100 mm.

In one embodiment of the present invention, the adhesive layer may include at least one material selected from the group consisting of an acrylic adhesive, a silicon based adhesive, and an epoxy based adhesive.

In one embodiment of the present invention, the thickness of the base substrate may be 0.3 mm.

In one embodiment of the present invention, the step of separating the protective film bonded to the base substrate may be a method of irradiating ultraviolet rays.

In one embodiment of the present invention, the step of separating the protective film adhered to the base substrate may be a method of immersing in a chemical solvent.

In one embodiment of the present invention, the chemical solvent may be an organic solvent.

In one embodiment of the present invention, the organic solvent may include at least one solution selected from the group consisting of chemical solutions having benzene, toluene, xylene, acetone and aldehyde groups.

In one embodiment of the present invention, the driving element may include a thin film transistor.

In one embodiment of the present invention, the display element may include a liquid crystal element.

According to the embodiment of the present invention, since the manufacturing process of the display substrate is performed by attaching the protective film to the base substrate, an additional etching process for reducing the thickness of the substrate can be omitted. Thus, the manufacturing cost can be reduced.

1 is a cross-sectional view of a protective film according to an embodiment of the present invention.
2 is a plan view of a display substrate according to an embodiment of the present invention.
3 is a cross-sectional view taken along line II 'of FIG.
FIGS. 4 to 16 are cross-sectional views illustrating a method of manufacturing the display substrate shown in FIGS. 2 and 3. FIG.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a cross-sectional view of a protective film according to an embodiment of the present invention.

Referring to FIG. 1, a protective film 30 according to an embodiment of the present invention may include a support 31 and an adhesive layer 32.

The protective film 30 is attached to the base substrate to prevent the base substrate from being damaged during the manufacturing process of the display substrate. In addition, the protective film 30 is attached to the flexible substrate in the process of manufacturing the flexible display substrate, thereby preventing the flexible substrate from being warped or damaged.

The support 31 may be at least one selected from the group consisting of poly (ethylene terephthalate), poly (butylenes terephthalate), polyimide, polyester and polyolefine. ≪ / RTI > The polyolefin may include polyethlene, polypropylene, or polyisobutylene. Preferably, the support 31 may be polyimide. This is because polyimide has properties such as excellent heat resistance and chemical resistance.

The adhesive layer 32 may be applied to one side of the support 31 to be adhered to the base substrate. The adhesive layer 32 may have an adhesive strength in the range of 0.2 to 60 N / 100 mm. If the adhesive strength of the adhesive layer 32 is less than 0.2 N / 100 mm, the space between the base substrate and the adhesive layer 32 can be separated by the stress applied during the manufacturing process of the display substrate. Further, when the adhesive strength of the adhesive layer 32 is more than 60 N / 100 mm, elements formed on the base substrate may be chemically and / or physically damaged in the step of separating the protective film from the base substrate.

The adhesive layer 32 may include at least one adhesive material selected from an acrylic adhesive, a silicon based adhesive, and an epoxy based adhesive.

2 is a plan view of a display substrate according to an embodiment of the present invention. 3 is a cross-sectional view taken along line I-I 'of FIG.

2 and 3, the thin film transistor substrate 101 includes a gate line GL, a data line DL crossing the gate line GL, a thin film transistor SW as a switching element, and a pixel electrode PE ). The thin film transistor SW is connected to the gate line GL and the data line DL and the pixel electrode PE is connected to the thin film transistor SW through a contact hole CNT.

The color filter substrate 201 may include a base substrate 210, a light shielding pattern 220, a color filter 230, an overcoat layer 240, and a common electrode 250. A liquid crystal layer 301 may be formed between the thin film transistor substrate 101 and the color filter substrate 201.

The gate line GL and the data line DL define a pixel region. Although only one pixel region is shown for convenience of explanation, the display device according to the embodiments of the present invention actually has a plurality of pixels formed in a plurality of pixel regions. The pixel region is arranged in a matrix form having a plurality of rows and a plurality of rows. Since the pixel regions have the same structure, only one pixel region will be described as an example for convenience of explanation. Here, the pixel region has a rectangular shape elongated in one direction, but is not limited thereto. The shape of the pixel region may be variously modified such as a V-shape or a Z-shape.

The switching element includes a gate electrode GE, an active pattern AP, a source electrode SE and a drain electrode DE. The gate electrode GE of the switching element protrudes in the second direction D2 from the gate line GL. The gate electrode GE overlaps the active pattern AP.

Hereinafter, a pattern formed together with the same metal layer as the gate line GL in the step of forming the gate line GL will be referred to as a "gate pattern ". That is, all the components included in the gate pattern have substantially the same layered structure. A pattern formed together with the same metal layer as the data line DL in the process of forming the data line DL will be referred to as a "source pattern SP ". The components included in the source pattern SP all have substantially the same layered structure.

The thin film transistor substrate 101 includes a first insulating layer 130 formed on the gate pattern, an active pattern AP of the thin film transistor SW, and a buffer layer 130 formed on the source pattern SP. And a second insulating layer 170 formed on the base substrate 110 on which the pattern BL and the buffer pattern BL are formed.

The gate pattern is formed on the base substrate 110 and includes a gate electrode GL of the thin film transistor SW connected to the gate line GL and the gate line GL. Although only the layered structure of the gate electrode GE is shown in FIG. 2, the layered structure of the gate line GL is substantially the same as the gate electrode GE.

The gate electrode GE is electrically connected to the gate line GL. The gate electrode GE includes at least one of copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese A multi-layer structure including a single layer structure or a plurality of metal layers including different materials. For example, the data line DL may include a copper (Cu) layer and a titanium (Ti) layer formed on top and / or bottom of the copper (Cu) layer.

The first insulating layer 130 may entirely cover the base substrate 110 on which the gate pattern is formed. The first insulating layer 130 may include silicon nitride (SiNx) and / or silicon oxide (SiOx).

An active pattern (AP) is formed on the first insulating layer (130). The active pattern AP is formed on the first insulating layer 130 in the region where the gate electrode GE is formed. The active pattern AP overlaps with the gate electrode GE and partially overlaps with each of the source electrode SE and the drain electrode DE. The active pattern AP is interposed between the gate electrode GE and the source electrode SE and may be interposed between the gate electrode GE and the drain electrode DE.

The active pattern AP may include a semiconductor layer 141 and an ohmic contact layer 143 formed on the semiconductor layer 141. The semiconductor layer 141 may include a silicon semiconductor material, for example, amorphous silicon. The ohmic contact layer 143 is interposed between the semiconductor layer 141 and the source electrode SE and interposed between the semiconductor layer 141 and the drain electrode DE. The ohmic contact layer 143 may include amorphous silicon doped with an n-type impurity at a high concentration.

A dummy pattern having a substantially same layered structure as the active pattern AP may be formed between the data line DL and the first insulating layer 130. [

The source pattern SP includes a data line DL, a source electrode SE of the thin film transistor SW connected to the data line DL, and a drain electrode DE spaced apart from the source electrode SE. . The source electrode SE and the drain electrode DE are disposed apart from each other on the active pattern AP.

The source electrode SE and the drain electrode DE may be formed of one selected from the group consisting of copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese A single-layer structure containing these alloys, or a multi-layer structure including a plurality of metal layers including different materials. For example, the source electrode SE and the drain electrode DE may include a copper (Cu) layer and a titanium (Ti) layer formed on top and / or bottom of the copper (Cu) layer.

The second insulating layer 170 is formed to cover the source pattern SP and the drain electrode DE includes the contact hole CNT partially exposed. The second insulating layer 170 may be formed of a material including silicon nitride (SiNx) or silicon oxide (SiOx).

Although not shown in the drawings, an organic layer may be formed between the second insulating layer 170 and the pixel electrode PE to planarize the surface of the TFT substrate 101. At this time, the contact hole CNT may be defined as a portion penetrating the second insulating layer 170 and the organic layer to expose the drain electrode DE.

The pixel electrode PE is formed on the second insulating layer 170 and the pixel electrode PE contacts the drain electrode DE through the contact hole CNT. Accordingly, the pixel electrode PE may be connected to the thin film transistor SW, the gate line GL, and the data line DL. The pixel electrode PE may be formed of indium zinc oxide (IZO) or indium tin oxide (ITO).

FIGS. 4 to 16 are cross-sectional views illustrating a method of manufacturing the display substrate shown in FIGS. 2 and 3. FIG.

Referring to FIG. 4, a protective film 30 is attached to one surface of a base substrate 110.

The base substrate 110 may be a glass substrate, a quartz substrate, a silicon substrate, a plastic substrate, or the like. The base substrate 110 may be a flexible substrate. The base substrate 110 according to an embodiment of the present invention may have a thickness of 0.3 mm.

The protective film 30 is attached to one surface of the base substrate 110. A driving device and a display device may be formed on the other surface of the base substrate 110. The driving element may include a thin film transistor. The display element may include a liquid crystal element. The protective film 30 may have a thickness of 0.2 mm. That is, the sum of the thickness of the base substrate 110 and the thickness of the protective film 30 may be 0.5 mm.

A protective film 30 according to an embodiment of the present invention is attached to the base substrate 110, and the manufacturing process of the display substrate proceeds. Therefore, the etching process for reducing the thickness of the base substrate 110 can be omitted, and the manufacturing cost can be reduced.

Referring to FIG. 5, a gate metal layer is formed on the base substrate 110. The gate metal layer may be formed as a single layer or a double layer structure. For example, the gate metal layer may be formed in a bilayer structure consisting of a first metal layer including titanium or a titanium alloy and a second metal layer including copper. The gate metal layer may be formed by a sputtering method.

A first photoresist pattern PR1 is formed on the base substrate 110 on which the gate metal layer is formed. The first photoresist pattern PR1 is disposed in a region where the gate electrode GE is formed. The first photoresist pattern PR1 is formed by forming a first photoresist layer including a photosensitive material on the base substrate 110 on which the gate metal layer is formed, exposing the first photoresist layer using the first mask 10, . The first mask 10 includes a light-transmitting portion 12 for transmitting light and a light-shielding portion 14 for blocking light. The first photoresist layer corresponding to the transparent portion 12 is removed by the developer. The first photoresist layer corresponding to the light-shielding portion 14 remains on the gate metal layer without being removed by the developer.

The gate metal layer is patterned using the first photoresist pattern PR1 as an etch stopping layer to form a gate pattern including the gate electrode GE.

6, a first insulating layer 130, the semiconductor layer 141, the ohmic contact layer 143, and a metal layer 150 for forming a source pattern are formed on the base substrate 100 on which the gate pattern is formed. And a buffer layer 160 are sequentially stacked.

The first insulating layer 130 may include silicon nitride (SiNx) or silicon oxide (SiOx). The semiconductor layer 141 may include a silicon semiconductor material, for example, amorphous silicon. The ohmic contact layer 143 is interposed between the semiconductor layer 141 and the source electrode SE and interposed between the semiconductor layer 141 and the drain electrode DE. The ohmic contact layer 143 may include amorphous silicon doped with an n-type impurity at a high concentration.

The metal layer 150 for forming the source pattern may be formed of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese Layer structure including an alloy, or a multi-layer structure including a plurality of metal layers including different materials. For example, the metal layer 150 for forming the source pattern may include a copper (Cu) layer and a titanium (Ti) layer formed on the top and / or bottom of the copper (Cu) layer. A buffer layer 160 is stacked on a base substrate on which the metal layer 150 for forming the source pattern is formed. The buffer layer 160 prevents the copper (Cu) on the source electrode SE and the drain electrode DE from being reputtered when the plasma treatment is performed before the passivation layer is deposited in a subsequent process.

7, the gate electrode GE, the first insulating layer 130, the semiconductor layer 141, the ohmic contact layer 143, the metal layer 150 for forming a source pattern, and the buffer layer 160 are formed. The second photoresist pattern PR2 is formed on the base substrate 110 sequentially stacked. The second photoresist pattern PR2 is formed by forming a second photoresist layer on the base substrate 110 on which the buffer layer 160 is formed and exposing the second photoresist layer using a second mask 20 Followed by development.

The second mask 20 includes a light-transmitting portion 22 for transmitting light, a light-shielding portion 24 for blocking light, and a translucent portion 26 for transmitting only a part of light. The second photoresist layer corresponding to the light-shielding portion 24 remains on the buffer layer 160 with the first thickness T1 without being removed by the developer. The first thickness T1 may be substantially equal to the initial thickness of the second photoresist layer. A portion of the second photoresist layer corresponding to the translucent portion 26 is removed by the developer, and a part thereof remains. Accordingly, the second photoresist layer remains in the second thickness T2 in a region corresponding to the semitransparent portion 26. The second thickness T2 is thinner than the first thickness T1. The second photoresist layer corresponding to the transparent portion 22 is removed by the developer. A second photoresist PR21 including the first photoresist pattern PR21 having the first thickness T1 and the second photoresist PR22 having the second thickness d2 is formed on the buffer layer 160. [ A pattern PR2 is formed.

Referring to FIG. 8, the buffer layer 160, the metal layer 150 for forming the source pattern, the ohmic contact layer 143, and the semiconductor layer (not shown) are formed using the second photoresist pattern PR2 as an etch- 141) is etched. The buffer layer 160, the metal layer 150 for forming the source pattern, the ohmic contact layer 143, and the semiconductor layer 141 may be simultaneously etched using an integrated etchant. The integrated etchant may include tetrachloroethane (TCE). Thus, a preliminary buffer layer 165, a preliminary electrode pattern 155, and a preliminary active pattern 145 are formed on the base substrate 110.

Referring to FIG. 9, the second photolithography pattern PR2 of the second photoresist pattern PR2 is removed to form a residual pattern PR3. The second photoresist pattern PR2 is removed by removing the thickness of the second photoresist pattern PR2 by the second thickness T2 and the first photoresist pattern PR21 is removed by the third thickness T3, The residual pattern PR3 can be formed. The third thickness T3 may be substantially equal to a value obtained by subtracting the second thickness T2 from the first thickness T1. A part of the spare buffer layer 155 is exposed as the second photolithography pattern PR22 is removed.

Referring to FIG. 10, a part of the spare buffer layer 155 is removed using the residual pattern PR3 as an etch stopping layer. The spare buffer layer 155 may be etched by a dry etching process. Then, a part of the preliminary electrode pattern 155 is removed. The preliminary electrode pattern 155 may be etched by a wet etching process. As a result, a part of the preliminary active pattern 145 is exposed. Subsequently, a part of the second semiconductor pattern 143 of the preliminary active pattern 145 is removed. The second semiconductor pattern 143 may be etched through a dry etching process.

Referring to FIG. 11, the residual pattern PR3 is removed using a stripper. Thus, the thin film transistor SW including the gate electrode GE, the active pattern AP, the source electrode SE, and the drain electrode DE is formed.

On the other hand, in a thin-film transistor of a back-channel etched (BCE) structure, since a channel layer is formed and an ohmic contact layer and a source / drain are formed, the defect density of the back channel surface is increased due to etching. Therefore, the plasma treatment is performed to reduce such defects and improve the back channel characteristics. The plasma treatment may be performed using H2, NH3, N2, O2, He or the like.

12, after the passivation layer 170 is formed on the base substrate 110 on which the thin film transistor SW is formed, an annealing process for applying heat to the passivation layer 170 is performed . The annealing process may be performed in an oxygen or nitrogen atmosphere at about 200 ° C to about 400 ° C for about 10 minutes to about 2 hours. The passivation layer 170 may be formed of silicon oxide (SiOx). The passivation layer 170 is patterned to form a contact hole CNT exposing the drain electrode DE.

Referring to FIG. 13, a transparent electrode layer is formed on the base substrate 110 on which the contact hole CNT is formed, and the transparent electrode layer is patterned to form a pixel electrode PE. The pixel electrode PE is electrically connected to the drain electrode DE through the contact hole CNT.

Referring to FIG. 14, a protective film 30 is attached to a base substrate 210 of a color filter substrate 201. The base substrate 210 may be a glass substrate, a quartz substrate, a silicon substrate, a plastic substrate, or the like. The base substrate 210 may be a flexible substrate. The base substrate 210 according to an embodiment of the present invention may have a thickness of 0.3 mm.

The protective film 30 is attached to one surface of the base substrate 210. A driving device and a display device may be formed on the other surface of the base substrate 210. The protective film 30 may have a thickness of 0.2 mm. That is, the sum of the thickness of the base substrate 210 and the thickness of the protective film 30 may be 0.5 mm.

Referring to FIG. 15, a base substrate 210, a light shielding pattern 220, a color filter 230, an overcoat layer 240, and a common electrode 250 are formed on the base substrate 210. The protective film 30 is attached to one surface of the base substrate 201 and the light shielding pattern 220, the color filter 230, the overcoat layer 240, And the common electrode 250 may be formed.

Referring to FIG. 16, the thin film transistor substrate 101 and the color filter substrate 201 are combined. The color filter substrate 201 may include a base substrate 210, a light shielding pattern 220, a color filter 230, an overcoat layer 240, and a common electrode 250. A liquid crystal layer 301 may be formed between the thin film transistor substrate 101 and the color filter substrate 201. Protective films 30 are attached to the base substrate 110 of the thin film transistor substrate 101 and the base substrate 210 of the color filter substrate 201, respectively.

The protective film 30 is removed in a subsequent step. The protective film 30 may be removed by irradiating ultraviolet rays. The adhesive strength of the adhesive layer 32 included in the protective film 30 may be lowered due to a chemical reaction caused by irradiated ultraviolet rays. Accordingly, the protective film 30 can be easily separated from the base substrate. Therefore, the protective film 30 may be removed to complete the display substrate.

As another method for removing the protective film 30, a method of immersing in a chemical solvent may be used. The chemical solvents may be organic solvents. The organic solvent may include at least one solution selected from benzene, toluene, xylene, acetone, and a chemical solution having an aldehyde group (-CHO).

The display substrate to which the thin film transistor substrate 101 and the color filter substrate 201 are bonded is immersed in the chemical solvent. The adhesive layer 32 included in the protective film 30 may chemically react with the chemical solvent to lower the adhesive strength. Accordingly, the protective film 30 can be easily separated from the base substrate. Therefore, the protective film 30 may be removed to complete the display substrate.

According to the embodiment of the present invention, since the manufacturing process of the display substrate is performed by attaching the protective film to the base substrate, an additional etching process for reducing the thickness of the substrate can be omitted. Thus, the manufacturing cost can be reduced.

The liquid crystal display device according to the embodiments of the present invention has industrial applicability that can be used in various types of display devices.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It will be understood.

101: thin film transistor substrate 110: base substrate
130: first insulating layer 141: semiconductor layer
143: ohmic contact layer AP: active pattern
GE: gate electrode SE: source electrode
DE: drain electrode 170: second insulating layer
30: Protective film

Claims (13)

Bonding a protective film to the first surface of the base substrate;
Forming a driving element and a display element on a second surface of the base substrate; And
And separating the protective film adhered to the base substrate. The method of claim 1, wherein the protective film
A support having a first side bonded to the base substrate and a second side opposite to the first side; And
And an adhesive layer formed on the first surface of the support. The method according to claim 2, wherein the thickness of the protective film is 0.2 mm. The method according to claim 2, wherein the support is at least one selected from the group consisting of polyimide, polyester, polyolefine, polyethylene terephthalate and polybutylenes terephthalate Wherein the first substrate and the second substrate are made of a single material. The method of manufacturing a display substrate according to claim 2, wherein the adhesive layer has an adhesive strength in the range of 0.2 to 60 N / 100 mm. The display device according to claim 2, wherein the adhesive layer comprises at least one material selected from the group consisting of an acrylic adhesive, a silicon based adhesive, and an epoxy based adhesive. ≪ / RTI > The method according to claim 2, wherein the thickness of the base substrate is 0.3 mm. The method of manufacturing a display substrate according to claim 1, wherein the step of separating the protective film adhered to the base substrate is a method of irradiating ultraviolet light. The method of claim 1, wherein the step of separating the protective film adhered to the base substrate is a method of immersing the protective film in a chemical solvent. The method of manufacturing a display substrate according to claim 9, wherein the chemical solvent is an organic solvent. 11. The method of claim 10, wherein the organic solvent comprises at least one solution selected from the group consisting of chemical solutions having benzene, toluene, xylene, acetone, and aldehyde groups. The method according to claim 1, wherein the driving element includes a thin film transistor. The method of manufacturing a display substrate according to claim 1, wherein the display element includes a liquid crystal element.
KR20130105187A 2013-09-03 2013-09-03 Method of manufacturing display substrate KR20150026406A (en)

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