KR20140142960A - SPI NAND Flash memory with parallel pipelined double latch - Google Patents

SPI NAND Flash memory with parallel pipelined double latch Download PDF

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Publication number
KR20140142960A
KR20140142960A KR1020130064768A KR20130064768A KR20140142960A KR 20140142960 A KR20140142960 A KR 20140142960A KR 1020130064768 A KR1020130064768 A KR 1020130064768A KR 20130064768 A KR20130064768 A KR 20130064768A KR 20140142960 A KR20140142960 A KR 20140142960A
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KR
South Korea
Prior art keywords
data
latch
write
read
page buffer
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KR1020130064768A
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Korean (ko)
Inventor
김용수
Original Assignee
중소기업은행
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Priority to KR1020130064768A priority Critical patent/KR20140142960A/en
Priority to PCT/KR2014/004588 priority patent/WO2014196753A1/en
Publication of KR20140142960A publication Critical patent/KR20140142960A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

Abstract

The present invention relates to a SPI-NAND flash memory including parallel pipeline double latch. The SPI-NAND flash memory includes: a page buffer; a plurality of read latches; and a plurality of write latches. When the data is read, a step of reading data from the page buffer and storing the data in a single read latch, and a step of outputting pre-stored data in another read latch are executed at the same time. Also, when the data is stored, a step of receiving data from an external source and storing the data in a single write latch, and a step of registering pre-stored data of another write latch in a write register of the page buffer are executed at the same time.

Description

[0001] SPI NAND Flash memory with parallel pipelined double latch [

The present invention relates to a SPI NAND flash memory driven by a parallel pipeline double latch.

FIG. 1 is a block diagram of a conventional SPI NAND flash memory 100. Referring to FIG.

1, unlike a general NAND flash memory, the SPI NAND flash memory 100 further includes a control logic 109 for SPI communication, and a command / address / The input of data (Data) is inputted through one pin (Pin), and is configured in units of bytes. Therefore, it is necessary to collect serial data input (externally applied serial data input) byte by byte and write to the write register of the internal page buffer (101), and perform a read operation It is necessary to read data from the memory array 103 byte by byte and output the data to the external SO pin serially.

When data is to be written, a serial-to-parallel conversion is performed between the DIN buffer 107 and the page buffer 101 to convert serial data (ex: 1 bit) into parallel data (ex: 8 bits) Parallel conversion circuit (Serial-to-Parallel Circuit) 105 is required. In order to read data, parallel data (ex: 8 bit) is connected between the page buffer 101 and the DOUT buffer 108 as serial data (Parallel-to-Serial Circuit) 106 for changing the bit rate to a bit rate (ex: 1 bit).

In order to perform a satisfactory read / write operation, a register / register for temporarily storing data is provided between the serial-parallel conversion circuit 105 / parallel-serial conversion circuit 106 and the page buffer 101, Latch is required. This will be described in more detail with reference to FIG. 2 and FIG.

FIG. 2 shows a program load timing diagram of a general SPI NAND flash memory, and FIG. 3 shows a random read out timing diagram of a general SPI NAND flash memory.

2, when the program is loaded, the last serial data (ex: last 1 bit) of the section (ex: total 8 bits) P201 is input to the first serial data input in the first write interval P201 The parallel data is changed to parallel data. However, this point 20 may overlap with the starting point 21 of the second writing period P202 in which the second data is input. At this time, if the SRAM cache register 102 block is not provided in the block diagram of FIG. 1, erroneous data may be written in the page buffer 101. For example, in the case of the first bit of the first data (ex: 8 bits) to be written in the page buffer 101 in the second write interval P202, the first data input from the outside in the first write interval P201 The second data input from the outside in the second write period P202 may be recorded although it should be recorded.

This can be similarly explained in a data read operation. 3, the first parallel data (ex: 8 bit) read from the page buffer 101 in the read dummy period P301 is read out from the page buffer 101 in the same manner as in the program loading, The serial data is changed to serial data only after the last data (ex: last 1 bit) is read. This time point 22 may overlap with the starting point 23 of the first reading period P302 for reading the second data have. At this time, if the SRAM cache register 102 block is not provided in the block diagram shown in FIG. 1, erroneous data may be outputted through the SO pin. For example, if the first bit of the first data (ex: 8 bits) to be output through the SO pin in the first reading interval P302 is the first bit read from the page buffer 101 in the dummy reading interval P301 The second data read from the page buffer 101 in the first read period P302 may be output.

Therefore, in order to prevent such a malfunction, it is necessary to store the data temporarily in the middle and to transmit the data to the page buffer 101 at a necessary time. For this purpose, It is a Cache Register. 1, in the SPI NAND flash memory 100 according to the related art, the SRAM cache register 102 may exist between the page buffer 101 and the column decoder (Y-Decoder) 104. At this time, the memory size of the SRAM cache register 102 has a size of, for example, 512 Bytes / 2K Bytes and is related to the page size of the NAND flash used and may become larger as the density increases. In addition, since the SRAM cache register 102 is drawn together with the page buffer 101, the chip size overhead is worsened, which limits production cost reduction.

Hereinafter, another conventional SPI NAND flash memory provided to reduce the burden of drawing together the SRAM cache register 102 and the page buffer 101 will be described with reference to FIG.

4 shows a block diagram of a SPI NAND flash memory 200 according to another prior art.

4, the SPI NAND flash memory 100 draws the SRAM cache register 102 between the page buffer 101 and the column decoder 104, whereas the SPI NAND flash memory 200 is a non- Has a structure in which the SRAM cache register 102 is drawn in a peripheral area. With this configuration, it is possible to reduce the burden of drawing the SRAM cache register 102 and the page buffer 101 together.

In the SPI NAND flash memories 100 and 200 according to FIGS. 1 to 4, since the SRAM cache register 102 is drawn together with the page buffer 101, the chip size overhead becomes severe and the column decoder 104 is redundantly provided There is a burden to do. Also, it is not desirable to make the data bus width between the SRAM cache register 102 and the page buffer 101, for example, 512 Bytes / 2K Bytes. As the number of buses increases, the layout overhead becomes larger as the number of buses increases. Therefore, the bus width should be 8bit / 16bit / 32bit / 64bit / 128bit, so that it does not affect layout overhead and performance. And so on. However, this selection has a direct effect on the read / program load performance. For example, in the case of reading, data can be externally output only after the data in the page buffer 101 is transferred to the SRAM cache register 102. In the case of a program load, all data is written in the SRAM cache register 102 It takes a long time to move the data to the page buffer 101, thereby affecting the actual program time.

In the present invention, an SPI NAND flash memory for solving such a problem is provided.

According to an aspect of the present invention, there is provided an SPI NAND flash memory including: a page buffer; And reading the data from the page buffer and storing the read data in one read latch; And outputting data already stored in the other read latch. Reading the other data from the page buffer immediately after the outputting step ends and storing the read data in the other one of the read latches; And outputting the data stored in the one read latch at the same time. In this case, the outputting step may be a step of outputting the already stored data on a 1-bit basis. The SPI NAND flash memory further includes a parallel-to-serial conversion circuit for converting parallel data into serial data, and the parallel data stored in the read latch is output as serial data after passing through the parallel-to-serial conversion circuit have.

According to another aspect of the present invention, there is provided an SPI NAND flash memory including: a page buffer; And a plurality of write latches, receiving data from the outside and storing the data in one write latch; And writing the data already stored in the other write latch into the write register of the page buffer. The method of claim 1, further comprising: receiving another data from the outside immediately after the writing step ends and storing the same in another write latch; and writing the data stored in the one write latch into a write register of the page buffer So that it can be performed simultaneously. In this case, the storing step is a step of storing data received from the outside in units of a plurality of bits. The SPI NAND flash memory may further include a serial-to-parallel conversion circuit for converting the serial data into parallel data. The serial data input from the outside may be transferred to the write latch As shown in Fig.

According to still another aspect of the present invention, an SPI NAND flash memory includes a page buffer, a first read latch, and a second read latch, and reads first data of a plurality of bits from the page buffer, In a first step; And a second step of outputting a plurality of bits of second data stored in the second read latch. At this time, the first step is completed while the second step is performed. In this case, the output of the second data is performed on a 1-bit basis.

According to another aspect of the present invention, there is provided an SPI NAND flash memory including a page buffer, a first write latch, and a second write latch, step; And a second step of writing the second data to the write register of the page buffer in the second write latch.

According to the present invention, it is possible to provide a low-cost and high-performance device without affecting the read / program time, reducing the size of the buffer required for the SPI operation and without incurring a large overhead in the performance of the layout area.

1 shows a block diagram of a conventional SPI NAND flash memory.
Figure 2 shows a timing diagram of a random data read of a general SPI NAND flash memory.
3 shows a program load timing diagram of a general SPI NAND flash memory.
4 shows a block diagram of another prior art SPI NAND flash memory.
5 shows a block diagram of an SPI NAND flash memory according to an embodiment of the present invention.
FIG. 6 illustrates a read path block diagram of an SPI NAND flash memory according to an embodiment of the present invention.
7 illustrates a program load path block diagram of an SPI NAND flash memory according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, but may be implemented in various other forms. The terminology used herein is for the purpose of understanding the embodiments and is not intended to limit the scope of the present invention. In addition, the singular forms used below include plural forms unless the phrases expressly have the opposite meaning.

FIG. 5 illustrates a block diagram of an SPI NAND flash memory 300 according to an embodiment of the present invention.

5 is compared with SPI NAND flash memories 100 and 200 according to the prior art shown in FIGS. 1 and 4, the SPI NAND flash memories 100 and 200 include SRAM cache registers 102 While the SPI NAND flash memory 300 according to an embodiment of the present invention includes a parallel pipeline double latch 301. [ That is, the SPI NAND flash memory 300 according to an embodiment of the present invention includes a parallel pipeline double latch 301 in place of the SRAM cache register 102, a page buffer 101, a serial-to-parallel conversion circuit 105, -To-serial conversion circuit 106. [0034] At this time, it may further comprise a double latch control circuit 302 for controlling the parallel pipeline double latch 301. At this time, the parallel pipeline double latch 301 includes a plurality of write latches 301_1 and a plurality of read latches 301_2.

The read path and the write path of the SPI NAND flash memory 300 according to an embodiment of the present invention will be described with reference to FIGS. 2, 3, 6, and 7. FIG.

FIG. 6 illustrates a read path block diagram of a SPI NAND flash memory 300 according to an embodiment of the present invention, and FIG. 7 illustrates a write path block diagram of a SPI NAND flash memory 300 according to an embodiment of the present invention. FIG.

Referring to FIG. 6, the read path of the SPI NAND flash memory 300 according to an embodiment of the present invention includes, for example, a dummy read period P301, a first read period P302, (P303).

During the dummy read period P301, the first reading step S61 described below may be executed.

First reading step S61: In the random data reading timing diagram shown in FIG. 3, the first (n = 8) bits (ex: 8 bits, n = 8) are read from the page buffer 101 during the dummy reading period P301 Th parallel data is read and stored in the first read latch 303.

The following second reading step (S62) and third reading step (S63) may be executed during the first reading interval (P302).

Second reading step (S62): The second parallel data of plural bits is read from the page buffer (101) and stored in the second reading latch (304).

Third reading step S63: The first parallel data stored in the first reading latch 303 during the dummy reading period P301 is transferred to the parallel-to-serial converting circuit 106 to generate serial data (ex: 1 bit) And is output to the SO terminal through the DOUT buffer 108 in synchronization with an external clock (Clock).

That is, the second reading step S62 and the third reading step S63 may be performed simultaneously during the first reading period P302.

During the second reading interval P303, the fourth reading step S64 and the fifth reading step S65 may be performed.

Fourth Reading Step S64: After the third reading step S63 of the first reading interval P302 is ended, the third parallel data of a plurality of bits is read from the page buffer 101 and the first reading latch 303 .

Fifth reading step S65: The second parallel data stored in the second reading latch 304 during the first reading period P302 is transferred to the parallel-to-serial converting circuit 106, converted into serial data, And output to the SO terminal through the buffer 108. [

At this time, the fourth reading step S64 and the fifth reading step S65 may be performed simultaneously during the second reading interval P303.

At this time, it can be easily understood that the first step (S61) to the fifth step (S65) can be repeated with increasing address (for example, column address).

7, the program load (write) path according to an embodiment of the present invention may include, for example, a first write period P201, a second write period P202, and a third write period P203).

During the first writing period P201, the first writing step S71 described below can be executed.

First write step S71: The first serial data inputted from the SI terminal during the first write period P201 in the program load timing diagram shown in FIG. 4 is transferred to the serial-to-parallel converter circuit 105 to be converted into parallel data And is stored in the first write latch 305 after being converted.

The second writing step S72 and the third writing step S73 below can be executed during the second writing period P202.

Second writing step S72: During the second writing period P202, the second serial data inputted from the SI terminal is transferred to the serial-to-parallel converting circuit 105, converted into parallel data, Write latch 306 as shown in FIG.

Third write step S73: The first serial data stored in the first write latch 305 during the first write period P201 is written to the page buffer 101 corresponding to the previously provided column address Lt; / RTI >

At this time, the second writing step S72 and the third writing step S73 may be performed simultaneously during the second writing period P202.

During the third writing period P203, the fourth writing step S74 and the fifth writing step S75 may be executed.

Fourth write step (S74): After the third write step (S73) of the second write section (P202) ends, the third serial data inputted from the SI terminal is transferred to the serial-to-parallel conversion circuit (105) And is stored in the first write latch 305 after being converted into data.

The second serial data stored in the second write latch 306 during the second write interval P202 is written in the page buffer 101 corresponding to the previously provided column address Lt; / RTI >

At this time, the fourth writing step S74 and the fifth writing step S75 may be performed simultaneously during the third writing period P203.

As described above, the SPI NAND flash memory 300 according to the embodiment of the present invention includes the parallel pipeline double latch 301, so that the data of the page buffer 101 can be outputted to the SO terminal without a time delay . This is possible because the dummy read period P301 exists in the read operation and the double latch 301 can appropriately use the time of the dummy read period P301 appropriately. In addition, even when a program load operation is performed, data input from the outside can be written into the write register of the page buffer 101 without delay.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the essential characteristics thereof. The contents of each claim in the claims may be combined with other claims without departing from the scope of the claims.

Claims (12)

A page buffer; And a plurality of read latches,
Reading data from the page buffer and storing the read data in one read latch; And outputting data already stored in the other read latch,
Memory. 2. The method of claim 1, further comprising: immediately after the outputting step, reading another data from the page buffer and storing it in the other read latch; And outputting the data stored in the one read latch.
Memory. The memory according to claim 1, wherein the step of outputting is a step of outputting the already stored data on a 1-bit basis. The semiconductor memory device according to claim 1, further comprising a parallel-to-serial conversion circuit for converting parallel data into serial data, wherein the parallel data stored in the read latch is output as serial data after passing through the parallel-
Memory. A page buffer; And a plurality of write latches,
Receiving data from outside and storing the data in a write latch; And writing the data already stored in the other write latch into the write register of the page buffer.
Memory. The method as claimed in claim 5, further comprising the steps of: receiving another data from the outside immediately after completion of the writing step and storing the same in another write latch; and writing the data stored in the one write latch to a write register Recording step,
Memory. 6. The memory according to claim 5, wherein the storing step stores the data received from the outside in units of a plurality of bits. 6. The method of claim 5,
Further comprising a serial-to-parallel conversion circuit for converting the serial data into parallel data,
Wherein the serial data inputted from outside is stored in the write latch as parallel data after passing through the serial-
Memory. A page buffer, a first read latch, and a second read latch,
A first step of reading the first data of a plurality of bits from the page buffer and storing the read first data in the first read latch; And a second step of outputting a plurality of bits of second data stored in the second read latch,
Memory. 10. The memory of claim 9, wherein the first step is to be completed while the second step is performed. 10. The memory according to claim 9, wherein the output of the second data is in units of one bit. A page buffer, a first write latch, and a second write latch,
A first step of receiving first data from outside and storing the first data in a first write latch; And a second step of writing second data to a write register of the page buffer in a second write latch,
Memory.
KR1020130064768A 2013-06-05 2013-06-05 SPI NAND Flash memory with parallel pipelined double latch KR20140142960A (en)

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KR1020130064768A KR20140142960A (en) 2013-06-05 2013-06-05 SPI NAND Flash memory with parallel pipelined double latch
PCT/KR2014/004588 WO2014196753A1 (en) 2013-06-05 2014-05-22 Spi nand flash memory driven by parallel pipeline double latch

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Cited By (3)

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CN104461401A (en) * 2014-12-25 2015-03-25 珠海煌荣集成电路科技有限公司 Data reading and writing management method and device for SPI flash memory
CN106445398A (en) * 2015-08-04 2017-02-22 深圳市中兴微电子技术有限公司 Novel memory-based embedded file system and realization method thereof
CN111856131A (en) * 2020-07-17 2020-10-30 许继集团有限公司 Load data recording method and device

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JP2001344987A (en) * 2000-05-29 2001-12-14 Nec Corp Semiconductor memory and read-out method of data
KR100454119B1 (en) * 2001-10-24 2004-10-26 삼성전자주식회사 Non-volatile semiconductor memory device with cache function and program, read and page copy-back operations thereof
US7817470B2 (en) * 2006-11-27 2010-10-19 Mosaid Technologies Incorporated Non-volatile memory serial core architecture
US8103936B2 (en) * 2007-10-17 2012-01-24 Micron Technology, Inc. System and method for data read of a synchronous serial interface NAND
US8102710B2 (en) * 2007-10-17 2012-01-24 Micron Technology, Inc. System and method for setting access and modification for synchronous serial interface NAND
KR20110110106A (en) * 2008-12-09 2011-10-06 램버스 인코포레이티드 Non-volatile memory device for concurrent and pipelined memory operations

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104461401A (en) * 2014-12-25 2015-03-25 珠海煌荣集成电路科技有限公司 Data reading and writing management method and device for SPI flash memory
CN106445398A (en) * 2015-08-04 2017-02-22 深圳市中兴微电子技术有限公司 Novel memory-based embedded file system and realization method thereof
CN106445398B (en) * 2015-08-04 2019-05-31 深圳市中兴微电子技术有限公司 A kind of embedded file system and its implementation based on novel memory devices
CN111856131A (en) * 2020-07-17 2020-10-30 许继集团有限公司 Load data recording method and device
CN111856131B (en) * 2020-07-17 2023-12-15 许继集团有限公司 Recording method and device for load data

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