KR20140124053A - Column level refresh control logic and semiconductor memory device comprising the same - Google Patents

Column level refresh control logic and semiconductor memory device comprising the same Download PDF

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Publication number
KR20140124053A
KR20140124053A KR20130041073A KR20130041073A KR20140124053A KR 20140124053 A KR20140124053 A KR 20140124053A KR 20130041073 A KR20130041073 A KR 20130041073A KR 20130041073 A KR20130041073 A KR 20130041073A KR 20140124053 A KR20140124053 A KR 20140124053A
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South Korea
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pxid
voltage
driver
sub
ref
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KR20130041073A
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Korean (ko)
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이치환
김명오
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삼성전자주식회사
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Publication of KR20140124053A publication Critical patent/KR20140124053A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4065—Low level details of refresh operations

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

A column-by-column refresh control logic and a semiconductor memory device are provided. The column-unit refresh control logic includes a PXID driver receiving a sub-word line control signal PXIB and generating a sub-word line drive signal PXID for driving a sub-word line driver according to the PXIB, A LA driver for receiving a first sense amplifier driving signal LAPG and generating a first sensing signal LA of a first voltage for sensing data of a sub memory cell array according to the LAPG, And a LAB driver for generating a second sensing signal (LAB) of a second voltage for sensing data of the sub-memory cell array according to the LANG, wherein each of the PXID driver, the LA driver, and the LAB driver, A column-by-column refresh control signal (REF) for selecting at least one column among a plurality of columns, and a column-by-column refresh control signal REF that is enabled when the REF is at a first level, When the display is enabled.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a column-level refresh control logic and a semiconductor memory device including the same,

The present invention relates to a column-unit refresh control logic and a semiconductor memory device including the same.

The volatile memory device must perform a refresh operation essentially in order to maintain the data. For example, DRAM (Dynamic Random Access Memory) uses a method of storing one bit of data by charging or discharging a capacitor in a memory cell. The charge charged in the capacitor is leaked according to a predetermined time constant. In order to retain the data of the memory cell, the charge amount of all the memory cells must be restored in every predetermined refresh period.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a column-by-column refresh control logic that can control refreshing in units of columns to reduce power consumption and noise generation in refreshing.

Another problem to be solved by the present invention is to provide a semiconductor memory device capable of reducing the power consumption and noise generated in the refresh operation by controlling the refresh in units of columns.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a column-by-column refresh control logic that receives a sub-word line control signal PXIB and generates a sub-word line drive signal PXID for driving the sub- A LA driver for receiving a first sense amplifier driving signal LAPG to generate a first sensing signal LA of a first voltage for sensing data of a sub memory cell array according to the LAPG, And an LAB driver which receives a second sense amplifier driving signal (LANG) and generates a second sensing signal (LAB) of a second voltage for sensing data of the sub memory cell array according to the LANG, The PXID driver, the LA driver, and the LAB driver of the first column receive the column-unit refresh control signal REF for selecting at least one column of the plurality of columns, Belin time is enabled and is disabled when the REF is in the second level.

In some embodiments of the present invention, the PXID driver uses the first voltage of the first voltage node and the second voltage of the second voltage node to output the PXID of the second voltage when the PXIB is at the first level And a PXID generating circuit for outputting the PXID of the first voltage when the PXIB is at the second level.

In some embodiments of the present invention, the subword line driver is driven when the PXID is at a first voltage, and is not driven when the PXID is a second voltage, and the PXID driver is configured such that the REF is at a first level A PXID enable circuit for supplying a first voltage of the first voltage node to the PXID generating circuit and not supplying the first voltage of the first voltage node to the PXID generating circuit when the REF is at a second level .

In some embodiments of the present invention, the PXID generation circuit includes a CMOS inverter for receiving the PXIB and outputting the PXID, the PXID enable circuit being connected to the CMOS inverter in series and having a gate to which the REF is input, . ≪ / RTI >

In some embodiments of the present invention, the LA driver includes: an LA generating circuit for generating a first sensing signal of the first voltage using a first voltage of a first voltage node; And a LA enable circuit for supplying a first voltage of the first voltage node to the LA generating circuit and not supplying the first voltage of the first voltage node to the LA generating circuit when the REF is at a second level .

In some embodiments of the present invention, the LA generating circuit includes a first transistor having a gate inputting the LAPG and providing a source voltage to the LA, the LA enable circuit being connected in series to the first transistor, And a second transistor to which the REF is input.

In some embodiments of the present invention, the LAB driver includes: an LAB generation circuit that generates a second sensing signal of the second voltage using a second voltage of a second voltage node; And an LAB enable circuit for blocking the output of the second sensing signal of the second voltage and blocking the output of the second sensing signal of the second voltage when the REF is at the second level.

In some embodiments of the present invention, the LAB generating circuit includes a first transistor having a gate applied with the LANG and a drain providing a voltage to the LAB, the LAB enable circuit being serially connected to the first transistor And a second transistor through which the REF is input to the gate.

In some embodiments of the present invention, the REF may correspond to sub-memory cell arrays disposed in a selected plurality of columns.

According to an aspect of the present invention, there is provided a semiconductor memory device comprising: a sub memory cell array including a plurality of memory cells arranged at intersections of a plurality of sub word lines and a plurality of bit lines to store data; A sub-word line driver disposed between the plurality of sub-memory cell arrays adjacent to each other in the column direction and activating selected sub-word lines of the plurality of neighboring sub-memory cell arrays; Sense amplifier for sensing the data of the corresponding sub-memory cell array, and a plurality of sense amplifiers disposed at a position where the sub-word line drivers and the sense amplifier cross each other, and driving the sub-word line drivers and the sense amplifiers , And the conformation includes a PXIB input And a PXID driver for generating a PXID for driving the sub-word line driver according to the PXIB, and a controller for receiving a LAPG and generating an LA of a first voltage for sensing data of the sub-memory cell array according to the LAPG LA driver, wherein the sense amplifier receives a LANG and generates an LAB of a second voltage for sensing data of the sub memory cell array according to the LANG, wherein each of the PXID drivers , The LA driver and the LAB driver receive the REF selecting at least one of the plurality of columns, and are enabled when the REF is at the first level and disabled when the REF is at the second level.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
2 is an enlarged block diagram of a portion A in Fig.
Fig. 3 is a circuit diagram for explaining the detailed configuration of the first junction of Fig. 2; Fig.
Fig. 4 is a circuit diagram for explaining the detailed configuration of the second junction of Fig. 2; Fig.
5 is a circuit diagram for explaining the detailed configuration of the third junction of FIG.
6 is a circuit diagram for explaining the detailed configuration of the first sense amplifier of FIG.
7 is a circuit diagram for explaining the detailed configuration of the second sense amplifier of FIG.
8 is a timing chart for explaining the operation of the column-unit refresh control logic of the semiconductor memory device of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

In an embodiment of the present invention, the semiconductor memory device may be a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), a LPDDR SDRAM, a Graphics Double Data Rate (SDRAM) SDRAM, a Rambus Dynamic Random Access Memory ), And the like, or any volatile memory device requiring a refresh operation.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

1, a semiconductor memory device 1 according to an embodiment of the present invention includes a sub memory cell array 100 (SMCA), a sub word line driver 200 (SWD), a sense amplifier 300 (SA) And a junction 400 (CJ).

The sub memory cell arrays 100 are arranged in the row direction (or the word line direction) and the column direction (or the bit line direction). The sub memory cell arrays 100 each include a plurality of memory cells MC. The plurality of memory cells are disposed at the intersections of the plurality of sub word lines SWL0 to SWL3 and the plurality of bit lines BL and BLB, respectively. The plurality of sub memory cell arrays 100 can be distinguished corresponding to DQ0 to DQ7 on a column basis.

The sub word line drivers 200 are arranged between a plurality of sub memory cell arrays 100 neighboring in the row direction and the plurality of sub memory cell arrays 100 neighboring in the row direction are arranged in a sub word And the line driver 200 are shared. The sub word line driver 200 can activate sub word lines SWL0 through SWL3 of a plurality of neighboring sub memory cell arrays 100. [ For convenience of description, it is assumed that the sub memory cell arrays 100 each include four sub word lines SWL0 to SWL3. In this case, the sub word line driver 200 can activate two sub word lines of the neighboring plurality of sub memory cell arrays 100, respectively.

The sense amplifier 300 is disposed between a plurality of sub memory cell arrays 100 neighboring in a column direction and the plurality of sub memory cell arrays 100 neighboring in a column direction are connected to a sense amplifier 300 ). The sense amplifier 300 can sense the data of the corresponding sub memory cell array 100. [ The sense amplifier 300 can sense data from the bit lines BL and BLB of the sub memory cell array 100. [ The sense amplifier 300 may perform pull-up sensing using the first sensing signal and may perform pull-down sensing using the second sensing signal.

The junction 400 may be disposed at a position where the sub word line drivers 200 and the sense amplifier 300 intersect each other. The junction 400 includes drivers for driving the sub-word line drivers 200 and the sense amplifiers 300.

Wirings for transmitting the column-unit refresh control signal REF can be arranged via the sense amplifier 300 region and the junction 400 region. The REF may be a signal that selects at least one of the plurality of columns. REF may correspond to the sub memory cell arrays 100 disposed in the selected column.

2 is an enlarged block diagram of a portion A in Fig.

2, the conversions 410 to 430 include PXID drivers 411 to 431 for driving the sub word line driver 200, LA drivers 412 to 412 for driving the sense amplifiers 310 to 320, 432). The sense amplifiers 310 to 320 include LAB drivers 311 to 321, respectively.

The PXID drivers 411 to 431 receive the sub word line control signal PXIB and generate a sub word line drive signal PXID for driving the corresponding sub word line driver 200 according to the PXIB. The LA drivers 412 to 432 receive the first sense amplifier driving signal LAPG and generate a first sensing signal LA of a first voltage for sensing data of the corresponding sub memory cell array 100 according to the LAPG, . The LAB drivers 311 to 321 receive the second sense amplifier driving signal LANG and generate a second sensing signal LAB of a second voltage for sensing data of the corresponding sub memory cell array 100 according to LANG, . For convenience of explanation, it is assumed that the first voltage represents the boosted voltage Vpp and the second voltage represents the ground voltage Vss. The first voltage node may represent a node providing Vpp and the second voltage node may represent a node providing Vss.

The PXID drivers 411 to 431, the LA drivers 412 to 432 and the LAB drivers 311 to 321 receive the above REF and are enaved when the REF is at the first level, 2 < / RTI > level. For convenience of explanation, it is assumed below that the first level indicates a high level and the second level indicates a low level. The voltage of the first level may represent the boosted voltage, and the voltage of the second level may represent the ground voltage.

Hereinafter, the column-by-column refresh control logic for refreshing a plurality of sub-memory cell arrays 100 on a column-by-column basis in the refresh operation of the semiconductor memory device 1 will be described. In one embodiment of the present invention, four bits of REF [0: 3] are used to select two of the plurality of columns, but this can be modified according to the embodiment. The plurality of column-by-column refresh control logic may include the above-described PXID drivers 411 to 431, LA drivers 412 to 432, and LAB drivers 311 to 321.

Fig. 3 is a circuit diagram for explaining the detailed configuration of the first junction of Fig. 2; Fig.

Referring to FIG. 3, the first conjugation 410 of FIG. 2 includes a PXID driver 411a for generating a PXID <0>, a PXID driver 411b for generating a PXID <2> signal, And an LA driver 412.

The PXID drivers 411a and 411b include PXID generation circuits 12 and 14 and PXID enable circuits 11 and 13 and the LA driver 412 includes an LA generation circuit 16 and an LA enable circuit 15).

The PXID generating circuit 12 for generating the PXID < 0 > may include an inverter. For example, the inverter may be a CMOS inverter in which a P-type transistor and an N-type transistor are connected in series. The CMOS inverter receives PXIB <0> and can output PXID <0>.

The PXID enable circuit 11 can be connected in series to the PXID generating circuit 12 that generates the PXID <0>. The PXID enable circuit 11 may include a transistor. For example, the PXID enable circuit 11 may include a P-type transistor. The source of the transistor is connected to the first voltage node, and REF < 0 > can be input to the gate. Specifically, REF <0> can be inverted and input to the gate of the transistor. The source of the P-type transistor of the CMOS inverter is connected to the drain of the transistor, and the source of the N-type transistor of the CMOS inverter is connected to the second voltage node.

The PXID generation circuit 14 that generates the PXID <2> may be configured substantially the same as the PXID generation circuit 12 that generates the PXID <0> described above. The CMOS inverter of the PXID generating circuit 14 that generates the PXID <2> receives the PXIB <2> and can output the PXID <2>. The PXID enable circuit 13 may also be connected in series to the PXID generating circuit 14 that generates the PXID <2>.

PXID <0> and PXID <2> drive the sub-word line driver 200 and the sub-word line driver 200 activates the first sub-word line SWL0 in response to PXID <0> The line driver 200 may activate the third sub word line SWL2 in response to PXID < 2 >.

The LA generator circuit 16 and the LA enable circuit 15 may each include at least one transistor. For example, the LA generating circuit 16 and the LA enable circuit 15 may each include an N-type transistor. LAPG is input to the gate of the transistor of the LA generation circuit 16, and the source voltage can be supplied to LA. The drain of the transistor of the LA enable circuit 15 is connected to the first voltage node, the source thereof is connected to the drain of the transistor of the LA generator circuit 16, and REF < 0 >

The PXID generating circuit 12 that generates the PXID <0> outputs the PXID <0> of the first voltage when the P-type transistor is turned on when the PXIB <0> is at the second level, The N-type transistor is turned on to output the PXID < 0 > of the second voltage. On the other hand, even when PXIB <0> is at the second level, since the N-type transistor of the PXID enable circuit 11 is turned off when REF <0> is at the second level, The first voltage of one voltage node is not supplied to the PXID generating circuit 12. [ In this case, the PXID < 0 > of the first voltage can not be output, and the sub word line driver 200 is not driven. That is, the PXID generation circuit 12 generating the PXID <0> supplies the first voltage from the PXID enable circuit 11 only when PXIB <0> is the second level and REF <0> And outputs the PXID <0> of the first voltage to drive the sub-word line driver 200. The sub word line driver 200 may activate the first sub word line SWL0 in response to the PXID < 0 > of the first voltage.

The PXID generation circuit 14 that generates the PXID <2> may also operate substantially the same as the PXID generation circuit 12 that generates the PXID <0> described above. That is, the PXID generation circuit 14 that generates the PXID <2> supplies the first voltage from the PXID enable circuit 13 only when PXIB <2> is the second level and REF <0> And outputs the PXID <2> of the first voltage to drive the sub word line driver 200. The sub word line driver 200 may activate the third sub word line SWL2 in response to the PXID < 2 > of the first voltage.

The LA generating circuit 16 can turn on the N-type transistor when the LAPG is at the first level and conduct the LA of the first voltage to the source. On the other hand, even when the LAPG is at the first level, since the N-type transistor of the LA enable circuit 15 is turned off when REF <0> is the second level, the LA enable circuit 15 is turned off, To the LA generator circuit. Therefore, the LA of the first voltage can not be conducted to the source of the LA generating circuit 16. That is, the LA generating circuit 16 receives the first voltage from the LA enable circuit 15 only when the LAPG is at the first level and REF <0> is at the first level, Can be provided.

Fig. 4 is a circuit diagram for explaining the detailed configuration of the second junction of Fig. 2; Fig. For convenience of explanation, differences from FIG. 3 will be mainly described.

Referring to FIG. 4, the second context 420 of FIG. 2 includes a PXID driver 421a for generating a PXID <1>, a PXID driver 421b for generating a PXID <3> And an LA driver 422.

The PXID generation circuit 22 for generating the PXID <1> can be configured substantially the same as the PXID generation circuit 12 for generating the PXID <0> described with reference to FIG. The CMOS inverter of the PXID generating circuit 22 that generates the PXID <1> receives the PXIB <1> and can output the PXID <1>. The PXID enable circuit 21 may be connected in series to the PXID generating circuit 22 that generates the PXID <1>.

The PXID generating circuit 24 for generating the PXID <3> may also be configured substantially the same as the PXID generating circuit 12 for generating the PXID <0> described with reference to FIG. The CMOS inverter of the PXID generating circuit 24 that generates the PXID <3> receives the PXIB <3> and can output the PXID <3>. The PXID enable circuit 23 may be connected in series to the PXID generating circuit 24 that generates the PXID <3>.

The LA generator circuit 26 and the LA enable circuit 25 may be configured substantially the same as the LA generator circuit 16 and the LA enable circuit 15 described with reference to Fig.

The PXID generating circuit 22 for generating the PXID <1> can operate substantially the same as the PXID generating circuit 12 for generating the PXID <0> described with reference to FIG. That is, the PXID generation circuit 22 that generates the PXID <1> supplies the first voltage from the PXID enable circuit 21 only when PXIB <1> is the second level and REF <0> And outputs the PXID <1> of the first voltage to drive the sub word line driver 200. The sub word line driver 200 may activate the second sub word line SWL1 in response to the PXID < 1 > of the first voltage.

The PXID generating circuit 24 for generating the PXID <3> can also operate substantially the same as the PXID generating circuit 12 for generating the PXID <0> described with reference to FIG. That is, the PXID generation circuit 24 generating the PXID <3> supplies the first voltage from the PXID enable circuit 23 only when PXIB <3> is the second level and REF <0> And outputs the PXID <3> of the first voltage to drive the sub word line driver 200. The sub word line driver 200 may activate the fourth sub word line SWL3 in response to the PXID <3> of the first voltage.

The LA generator circuit 26 can operate substantially the same as the LA generator circuit 16 described with reference to Fig.

5 is a circuit diagram for explaining the detailed configuration of the third junction of FIG. For convenience of explanation, differences from FIG. 3 will be mainly described.

5, the third match 430 of FIG. 2 includes a PXID driver 431a for generating a PXID <0>, a PXID driver 431b for generating a PXID <2> And an LA driver 432.

The PXID generation circuit 32 for generating the PXID <0> may be configured substantially the same as the PXID generation circuit 12 for generating the PXID <0> described with reference to FIG. The CMOS inverter of the PXID generation circuit 32 that generates the PXID <0> receives the PXIB <0> and can output the PXID <0>. The PXID enable circuit 31 may be connected in series to the PXID generating circuit 32 that generates the PXID <0>. REF < 1 > may be inverted and input to the gate of the transistor of the PXID enable circuit 31. [

The PXID generating circuit 34 for generating the PXID <2> may also be configured substantially the same as the PXID generating circuit 12 for generating the PXID <0> described with reference to FIG. The CMOS inverter of the PXID generating circuit 34 for generating the PXID <2> receives the PXIB <2> and can output the PXID <2>. The PXID enable circuit 33 may also be connected in series to the PXID generating circuit 34 that generates the PXID <2>. REF < 1 > may be inverted and input to the gate of the transistor of the PXID enable circuit 33. [

The LA generator circuit 36 and the LA enable circuit 35 may be configured substantially the same as the LA generator circuit 16 and the LA enable circuit 15 described with reference to Fig. REF < 1 > may be input to the gate of the transistor of the LA enable circuit 35. [

The PXID generating circuit 32 for generating the PXID <0> can operate substantially the same as the PXID generating circuit 12 for generating the PXID <0> described with reference to FIG. That is, the PXID generating circuit 32 generating the PXID <0> supplies the first voltage from the PXID enable circuit 31 only when PXIB <0> is the second level and REF <1> And outputs the PXID <0> of the first voltage to drive the sub-word line driver 200. The sub word line driver 200 may activate the first sub word line SWL0 in response to the PXID < 0 > of the first voltage.

The PXID generating circuit 34 for generating the PXID <2> can also operate substantially the same as the PXID generating circuit 12 for generating the PXID <0> described with reference to FIG. That is, the PXID generation circuit 34 generating the PXID <2> supplies the first voltage from the PXID enable circuit 33 only when PXIB <2> is the second level and REF <1> And outputs the PXID <2> of the first voltage to drive the sub word line driver 200. The sub word line driver 200 may activate the third sub word line SWL2 in response to the PXID < 2 > of the first voltage.

The LA generator circuit 36 can operate substantially the same as the LA generator circuit 16 described with reference to Fig. That is, the LA generating circuit 36 receives the first voltage from the LA enable circuit 35 only when the LAPG is at the first level and REF <1> is at the first level, Can be provided.

6 is a circuit diagram for explaining the detailed configuration of the first sense amplifier of FIG.

Referring to FIG. 6, the first sense amplifier 310 of FIG. 2 includes an LAB driver 311 for generating an LAB.

The LAB driver 311 may include an LAB generating circuit 42 and an LAB enable circuit 41.

The LAB generating circuit 42 and the LAB enable circuit 41 may each include at least one transistor. For example, the LAB generation circuit 42 and the LAB enable circuit 41 may each include an N-type transistor. LANG may be input to the gate of the transistor of the LAB generating circuit 42, and the source may be connected to the second voltage node. The LAB enable circuit 41 may include a plurality of transistors connected in parallel. The drain voltages of the plurality of transistors are provided to the LAB, the sources are connected to the drains of the transistors of the LAB generating circuit, and REF < 0 >

The LAB generation circuit 42 can turn on the N-type transistor when LANG is at the first level and conduct the LAB of the second voltage to the drain. On the other hand, even when LANG is at the first level, since the N-type transistor of the LAB enable circuit 41 is turned off when REF <0> is the second level, the LAB enable circuit 41 outputs the second voltage Block the output of the LAB. Therefore, the LAB of the second voltage can not be provided from the drain of the LAB generating circuit 42. [ That is, the LAB generating circuit 42 can be configured such that the LAB enable circuit 41 blocks the output of the LAB only when LANG is at the first level and REF <0> is at the first level, LAB can be provided.

7 is a circuit diagram for explaining the detailed configuration of the second sense amplifier of FIG. For convenience of description, differences from FIG. 6 will be mainly described.

Referring to FIG. 7, the second sense amplifier 320 of FIG. 2 includes an LAB driver 321 that generates an LAB.

The LAB driver 321 may be configured substantially the same as the LAB driver 311 described with reference to Fig. REF <0> and REF <1> may be input to the gates of the plurality of transistors of the LAB enable circuit 51 of the LAB driver 321, respectively.

The LAB generating circuit 52 can operate substantially the same as the LAB generating circuit 42 described with reference to Fig. In other words, the LAB generating circuit 52 is configured such that the LAB enable circuit 51 blocks the output of the LAB only when LANG is at the first level and REF <0> or REF <1> is at the first level, Lt; RTI ID = 0.0 &gt; LAB &lt; / RTI &gt;

8 is a timing chart for explaining the operation of the column-unit refresh control logic of the semiconductor memory device of FIG. 8, in order to refresh only the sub memory cell array 100 corresponding to DQ4 and DQ0 among the plurality of columns, the sub word line driver 200 and the sense amplifier which are involved in only the columns corresponding to DQ4 and DQ0 are driven The operation of the column-by-column refresh control logic will be described.

Referring to FIG. 8, first, PXIB <1> is changed from the first level to the second level, and PXIB <0>, PXIB <2>, and PXIB <3> are maintained at the first level. At the same time, REF <0> is changed from the second level to the first level, and REF <1>, REF <2>, and REF <3> are maintained at the second level.

Accordingly, the PXID driver 421a of the second junction 420 described with reference to FIG. 4 outputs the PXID <1> of the first voltage. Thereby, the second word line driver 200 adjacent to the second word line 420 is driven, and the sub word line driver 200 activates the second sub word line SWL1 corresponding to the PXID <1>. On the other hand, only the second sub word line SWL1 of the sub memory cell array 100 corresponding to DQ4 and DQ0 is activated and the second sub word line SWL1 of the sub memory cell array 100 corresponding to the remaining DQ is activated It is not activated. REF <2>, REF <2>, and REF <3> are maintained at the second level except for REF <0> Since the circuits are not supplied with the first voltage of the first voltage node.

Then, LANG and LAPG are changed from the second level to the first level.

Accordingly, the LA driver 422 of the second junction 420 described with reference to FIG. 4 outputs the LA of the first voltage and outputs the LA of the first voltage to the first and second sense amplifiers 310 The LAB drivers 311 to 312 of the first to the third voltage generation units output the LAB of the second voltage. As a result, the sense amplifiers 310 to 320 adjacent to the second control 420 are driven, and the sense amplifiers 310 to 320 sense the data stored in the memory cells arranged in the second sub word line SWL1 . On the other hand, only the sense amplifiers disposed in the columns corresponding to DQ4 and DQ0 are driven, and the sense amplifiers disposed in the columns corresponding to the remaining DQ are not driven. REF <1>, REF <2>, and REF <3> other than REF <0> are maintained at the second level, The circuits are not supplied with the first voltage of the first voltage node, and the other LAB generating circuits are cut off the LAB output of the voltage.

In order to refresh only the sub memory cell array 100 corresponding to DQ6 and DQ2, REF <1> may be changed from the first level to the second level. In order to refresh only the sub memory cell array 100 corresponding to DQ5 and DQ1, REF <2> may be changed from the first level to the second level. In order to refresh only the sub memory cell array 100 corresponding to DQ7 and DQ3, REF <3> may be changed from the first level to the second level.

In the above, it has been described with reference to FIG. 8 that two columns among a plurality of columns are selected and refreshed, but the present invention is not limited thereto. For example, when REF <1> and REF <3> are changed from the first level to the second level together, the sub memory cell arrays 100 corresponding to DQ6, DQ2, DQ7 and DQ3 can be refreshed. DQ2, DQ5, DQ1, DQ7 and DQ3 corresponding to REQ <1>, REF <2> and REF <3> are changed from the first level to the second level together, Cell arrays 100 can be refreshed. REF <2>, REF <3>, and REF <4> can all be changed from the first level to the second level in order to refresh the sub memory cell arrays 100 of all the columns.

Conventional semiconductor memory devices have activated the word lines of all the columns to refresh the memory cells disposed on one word line. The present invention allows refreshing for two, four, six, or eight columns on a column by column basis. Controlling the refresh of the semiconductor memory device 1 in units of columns can reduce the noise component induced in the power line and can significantly reduce the power consumed during the refresh. In addition, when the column-by-column refresh is selectively performed only on the memory cells having a large leakage current among the memory cell arrays, power consumption can be minimized while satisfying the refresh specification.

The steps of a method or algorithm described in connection with the embodiments of the invention may be embodied directly in hardware, software modules, or a combination of the two, executed by a processor. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any form of computer readable recording medium known in the art Lt; / RTI &gt; An exemplary recording medium is coupled to a processor, which is capable of reading information from, and writing information to, the recording medium. Alternatively, the recording medium may be integral with the processor. The processor and the recording medium may reside in an application specific integrated circuit (ASIC). The ASIC may reside within the user terminal. Alternatively, the processor and the recording medium may reside as discrete components in a user terminal.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: Sub memory cell array
200: Sub word line driver
300: Sense Amplifier
310: 1st sense amplifier
320: 2nd sense amp
311, 321: LAB driver
400: Conjunction
410: First Conjunction
420: Secondary junction
430: Third Conjunction
411, 421, 431: PXID driver
412, 422, 432: LA driver

Claims (10)

A PXID driver receiving the sub word line control signal PXIB and generating a sub word line drive signal PXID for driving the sub word line driver in accordance with the PXIB;
A LA driver receiving a first sense amplifier driving signal LAPG and generating a first sensing signal LA of a first voltage for sensing data of a sub memory cell array according to the LAPG; And
And an LAB driver which receives a second sense amplifier driving signal (LANG) and generates a second sensing signal (LAB) of a second voltage for sensing data of the sub memory cell array according to the LANG,
Wherein each of the PXID driver, the LA driver and the LAB driver receives a column-unit refresh control signal REF for selecting at least one column among a plurality of columns, and is enabled when the REF is at a first level, The column-by-column refresh control logic is disabled when the second level is the second level. The method according to claim 1,
The PXID driver outputs the PXID of the second voltage when the PXIB is at the first level using the first voltage of the first voltage node and the second voltage of the second voltage node, And a PXID generation circuit for outputting the PXID of the first voltage when the column voltage is lower than the first voltage. 3. The method of claim 2,
Wherein the sub word line driver is driven when the PXID is a first voltage and is not driven when the PXID is a second voltage,
Wherein the PXID driver supplies a first voltage of the first voltage node to the PXID generation circuit when the REF is at a first level and supplies the first voltage of the first voltage node to the PXID generation circuit when the REF is at a second level A column-by-column refresh control logic that includes a PXID enable circuit that supplies the PXID generator circuit. The method of claim 3,
Wherein the PXID generation circuit includes a CMOS inverter for receiving the PXIB and outputting the PXID, the PXID enable circuit including a transistor connected in series to the CMOS inverter and having a gate to which the REF is input, Logic. The method according to claim 1,
Wherein the LA driver comprises: an LA generating circuit for generating a first sensing signal of the first voltage using a first voltage of a first voltage node; To the LA generator circuit and to supply the first voltage of the first voltage node to the LA generator circuit when the REF is at a second level. 6. The method of claim 5,
Wherein the LA generating circuit includes a first transistor having a gate receiving the LAPG and providing a source voltage to the LA, the LA enable circuit having a first transistor connected in series to the first transistor and a second A column-by-column refresh control logic, including transistors. The method according to claim 1,
Wherein the LAB driver comprises: an LAB generation circuit for generating a second sensing signal of the second voltage using a second voltage of a second voltage node; and a second sensing signal of the second voltage when the REF is at a first level, And an LAB enable circuit for blocking output of the second sensing signal of the second voltage when the REF is at a second level. 8. The method of claim 7,
Wherein the LAB generation circuit includes a first transistor having a gate to which the LANG is applied and a drain to provide a voltage of the drain to the LAB, the LAB enable circuit being connected in series to the first transistor, Column-by-column refresh control logic, including two transistors. The method according to claim 1,
Wherein the REF corresponds to sub-memory cell arrays arranged in a selected plurality of columns. A sub memory cell array including a plurality of memory cells arranged at intersections of a plurality of sub word lines and a plurality of bit lines and storing data;
A sub word line driver disposed between the plurality of sub memory cell arrays neighboring in the row direction and activating the selected sub word lines of the plurality of neighboring sub memory cell arrays;
Sense amplifiers arranged between a plurality of sub memory cell arrays neighboring in a column direction and sensing data of a corresponding sub memory cell array; And
Word line drivers and a sense amplifier, wherein the sub word line drivers and the sense amplifiers are disposed at intersections of the sub word line drivers and the sense amplifiers,
The PXID driver receives a PXIB and generates a PXID for driving the sub-word line driver according to the PXIB. The PXID driver receives a LAPG and detects data of the sub-memory cell array according to the LAPG A LA driver for generating an LA of a first voltage,
The sense amplifier includes a LAB driver receiving a LANG and generating a LAB of a second voltage for sensing data of the sub memory cell array according to the LANG,
Wherein each of the PXID driver, the LA driver, and the LAB driver receives a REF that selects at least one column of a plurality of columns, and when the REF is enabled at a first level and the REF is at a second level, Lt; / RTI &gt;
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