KR20140117938A - Ring-type Voltage Controlled Oscillator - Google Patents

Ring-type Voltage Controlled Oscillator Download PDF

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Publication number
KR20140117938A
KR20140117938A KR1020130032917A KR20130032917A KR20140117938A KR 20140117938 A KR20140117938 A KR 20140117938A KR 1020130032917 A KR1020130032917 A KR 1020130032917A KR 20130032917 A KR20130032917 A KR 20130032917A KR 20140117938 A KR20140117938 A KR 20140117938A
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South Korea
Prior art keywords
mos
voltage
moss
ring
present
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KR1020130032917A
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Korean (ko)
Inventor
김규석
나유삼
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삼성전기주식회사
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Priority to KR1020130032917A priority Critical patent/KR20140117938A/en
Publication of KR20140117938A publication Critical patent/KR20140117938A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H03K3/0322—Ring oscillators with differential cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H03K2005/00208—Layout of the delay element using FET's using differential stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

The present invention relates to a ring type voltage controlling oscillator. In the ring type voltage controlling oscillator according to the present invention, multiple delay cells are connected in a chain form. The delay cell includes: first to fourth MOSs which control an oscillation frequency which oscillates through an output terminal (Vout); and a fifth MOS which is connected to the common node of each source of the first to fourth MOSs and controls the first to fourth MOSs. The present invention respectively controls a control voltage (Vctrl) of a fixed size which is applied to the gate terminal of the fifth MOS, a body voltage (Vbody) which is applied to a body, and a voltage which is applied to the gate terminal and the body. The present invention is able to improve a Kvco (VCO′s gain) by controlling two voltages at the same time by respectively applying to the gate and body of the fifth MOS which controls the first to fourth MOSs which control an oscillation frequency in the delay cell, and thereby is able to improve a PLL system function and a phase noise feature.

Description

[0001] The present invention relates to a Ring-type Voltage Controlled Oscillator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ring-type voltage-controlled oscillator used in a wireless communication system, and more particularly to a ring-type voltage-controlled oscillator capable of improving PLL (phase-locked loop) system performance and phase noise characteristics by improving gain of a voltage- will be.

A wireless communication system transmits information without loss with a specific frequency band and transmits and receives a high frequency signal with a constant voltage gain without loss in a high frequency part transmitting and receiving signals through an antenna.

1 is a schematic view showing a configuration of a general LO frequency signal generator.

Referring to FIG. 1, a local oscillator (LO) frequency signal generator 100 supplies an LO frequency signal for frequency synthesis in a wireless communication system, and includes a voltage controller oscillator A voltage controlled oscillator (VCO) 110, a buffer 120 for stably supplying the oscillated high frequency signal, and a frequency divider 130 for distributing a high frequency signal inputted through the buffer 120. The LO frequency signal generator 100 aims at maintaining a constant output voltage level in a frequency band in which a high frequency component oscillation signal is intended to be used.

The characteristic index representative of the performance of the voltage controlled oscillator 110 may be limited to phase noise, frequency tuning range, and Kvco (VCO's gain). Kvco characteristics are closely related to the characteristics of phase noise and frequency tuning range, especially in broadband systems, because it means the ratio of input voltage variation to output frequency variation. In view of the PLL system, since the Kvco factor of the VCO 110 directly affects the loop gain and the loop bandwidth, there is a continuing need to optimize the Kvco characteristic have.

FIG. 2 is a schematic configuration diagram of a conventional ring-shaped voltage-controlled oscillator, and FIG. 3 is an internal circuit diagram of a delay cell of the ring-shaped voltage-controlled oscillator of FIG.

As shown in FIG. 2, the conventional ring-shaped voltage controlled oscillator 200 has a structure in which a plurality of delay cells 210 are connected in a chain form. Therefore, to increase the oscillation frequency, the load capacitance must be reduced.

In the delay cell 210 of the ring-shaped voltage-controlled oscillator of FIG. 3, the elements for adjusting the oscillation frequency are PM1 and PM4. In the conventional ring type voltage controlled oscillator, the bias voltage Vco applied to the gate node of PM5 connected to the common source part of PM1 and PM4 is controlled to control PM1 and PM4. However, in the case of adjusting the bias voltage applied to the gate node as described above, there is a problem that the output frequency greatly changes even when the bias voltage is adjusted by a small value.

FIG. 4 is a graph showing frequency variation with respect to a control voltage variation amount according to the gate bias control of PM5 in the delay cell circuit of FIG. 3. FIG.

Referring to FIG. 4, in the VCO, Kvco (VCO's gain), which is a ratio of the input voltage variation and the output frequency variation, is represented by an important characteristic index. In the PLL system, since the Kvco index directly affects the loop gain and the loop bandwidth, the Kvco characteristic, that is, the frequency variation is large and the Kvco is required to be small. However, in the conventional VCO structure as described above, the size of the device must be reduced in order to perform a high-frequency operation. Therefore, the frequency characteristic is largely changed even in a small value voltage control, and thus, a Kvco index is high in a broadband high- have.

Korean Patent Publication No. 10-2009-0118199 Japanese Unexamined Patent Application Publication No. 2009-260607

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and it is an object of the present invention to improve a PLL system performance by improving Kvco (VCO's gain), which is a ratio of input voltage variation and output frequency variation, And a ring-shaped voltage-controlled oscillator capable of improving phase noise characteristics.

To achieve the above object, a ring-shaped voltage controlled oscillator according to the present invention includes:

A ring-shaped voltage-controlled oscillator in which a plurality of delay cells are connected in a chain,

The delay cell includes:

First and fourth MOSs for adjusting an oscillation frequency oscillating through an output terminal (Vout); And

And a fifth MOS connected to a common node of each of the sources of the first and fourth MOSs and regulating the first and fourth MOSs,

A control voltage Vctrl of a predetermined magnitude is applied to the gate terminal of the fifth MOS, a body voltage Vbody is applied to the body, and a voltage applied to the gate terminal and the body is controlled, There is a feature to control.

Here, the fifth MOS is a drain connected to a common node of each of the sources of the first and fourth MOSs, and the source is connected to a power source (Vdd).

At this time, PMOS may be used as the first, fourth, and fifth MOSs.

The first MOS may further include a second MOS, and the fourth MOS may further include a third MOS.

At this time, the drain of the second MOS is connected to the drain of the first MOS, and the source of the second MOS is connected to the power supply (Vdd).

Further, the drain of the third MOS is connected to the drain of the fourth MOS, and the source of the third MOS is connected to the power supply (Vdd).

At this time, PMOS may be used as the second and third MOSs.

According to the present invention, a voltage is applied to the gate and the body of the fifth MOS controlling the first and fourth MOSs for controlling the oscillation frequency in the delay cell, and the two voltages are simultaneously adjusted to obtain the Kvco (VCO's gain) The PLL system performance and the phase noise characteristic can be improved.

1 schematically shows a configuration of a general LO frequency signal generator;
2 is a schematic configuration diagram of a conventional ring-shaped voltage-controlled oscillator.
FIG. 3 is an internal circuit diagram of a delay cell of the ring-shaped voltage-controlled oscillator of FIG. 2;
4 is a graph showing a frequency change with respect to a control voltage variation amount according to the gate bias control of PM5 in the delay cell circuit of FIG.
5 is a view showing a configuration of a delay cell of a ring-shaped voltage-controlled oscillator according to an embodiment of the present invention.
6 is a graph showing a change in frequency due to the gate and body voltage control of PM5 in the delay cell circuit of FIG.

The terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms and the inventor can properly define the concept of the term to describe its invention in the best way Should be construed in accordance with the principles and meanings and concepts consistent with the technical idea of the present invention.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise. Also, the terms " part, "" module, "and" device " Lt; / RTI >

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a diagram illustrating a configuration of a delay cell of a ring-shaped voltage-controlled oscillator according to an embodiment of the present invention.

Referring to FIG. 5, a ring-shaped voltage controlled oscillator (VCO) according to the present invention basically has a structure (see FIG. 2) in which a plurality of delay cells 510 are connected in a chain form.

The delay cell 510 includes first and fourth MOS transistors PM1 and PM4 for adjusting the oscillation frequency oscillated through the output terminal Vout and first and fourth MOS transistors PM1 and PM4 for controlling the sources of the first and fourth MOS transistors PM1 and PM4 And a fifth MOS (PM5) connected to the common node for regulating the first and fourth MOSs (PM1, PM4).

A control voltage Vctrl of a predetermined magnitude is applied to the gate terminal of the fifth MOS transistor PM5 and a body voltage Vbody is applied to the body of the fifth MOS transistor PM5. Respectively, to adjust the oscillation frequency.

As described above, in the ring-shaped voltage-controlled oscillator of the present invention, by applying a voltage to both the gate and the body of the fifth MOS (PM5) of the delay cell 510 to simultaneously adjust the two voltages, It is possible to solve the problem that the output frequency is largely changed even when the bias voltage Vctrl applied to the ring-shaped VCO is adjusted. Therefore, it is possible to improve the Kvco (VCO's gain), and as a result, improve the performance and the phase noise characteristic of the PLL system (receiving the output of the ring-shaped VCO of the present invention as input).

The drain of the fifth MOS transistor PM5 is connected to a common node of the sources of the first and fourth MOS transistors PM1 and PM4 and the source thereof is connected to the power source Vdd do.

The first, fourth, and fifth MOS transistors PM1, PM4, and PM5 may be PMOS transistors.

The first MOS transistor PM1 may further include a second MOS transistor PM2 and the fourth MOS transistor PM4 may further include a third MOS transistor PM3.

At this time, the drain of the second MOS transistor PM2 is connected to the drain of the first MOS transistor PM1, and the source of the second MOS transistor PM2 is connected to the power source Vdd. Similarly, the drain of the third MOS transistor PM3 is connected to the drain of the fourth MOS transistor PM4, and the source of the third MOS transistor PM3 is connected to the power source Vdd.

At this time, PMOS may be used as the second and third MOSs PM2 and PM3.

In the ring-shaped voltage-controlled oscillator of the present invention, a drain is connected to a common node to which the drains of the first and second MOS transistors PM1 and PM2 are connected, and a source is connected to a sixth MOS (NM1) And a seventh MOS (NM2) having a drain connected to a common node to which the drains of the third and fourth MOS transistors PM3 and PM4 are connected, and a source connected to the ground. At this time, NMOS may be used as the sixth and seventh MOSs NM1 and NM2.

On the other hand, in the ring-shaped voltage-controlled oscillator according to the present invention having the above-

Figure pat00001
) Can be expressed by the following equation.

Figure pat00002

In the above formula

Figure pat00003
,
Figure pat00004
The transmission conductance of each corresponding device,
Figure pat00005
The load conductance,
Figure pat00006
Represents the load capacitance, respectively.

In order for the ring-shaped VCO to oscillate, the delay cells must be connected in a chain form as shown in FIG. Therefore, in order to increase the oscillation frequency, the load capacitance must be reduced.

The ring-type VCO of the present invention is a structure for linearly adjusting the Kvco value of the ring-type VCO. The ring-type VCO is a common source of the first MOS (PM1) and the fourth MOS (PM4) 6, Vctrl, which is a constant voltage, is applied to the gate node of the fifth MOS PM5 connected to the fifth MOS PM5, and Vbody is applied to the body node of the fifth MOS PM5, It is possible to obtain the effect that the Kvco (VCO's gain) characteristic is linear rather than the structure and the rate of change is lowered.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but many variations and modifications may be made without departing from the spirit and scope of the invention. Be clear to the technician. Accordingly, the true scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of the same should be construed as being included in the scope of the present invention.

110 ... voltage controlled oscillator 120 ... buffer
130 ... frequency divider 200 ... ring-shaped voltage-controlled oscillator
210,510 ... delay cell

Claims (7)

A ring-shaped voltage-controlled oscillator in which a plurality of delay cells are connected in a chain,
The delay cell includes:
First and fourth MOSs for adjusting an oscillation frequency oscillating through an output terminal (Vout); And
And a fifth MOS connected to a common node of each of the sources of the first and fourth MOSs and regulating the first and fourth MOSs,
A control voltage Vctrl of a predetermined magnitude is applied to the gate terminal of the fifth MOS, a body voltage Vbody is applied to the body, and a voltage applied to the gate terminal and the body is controlled, Controlled ring oscillator.
The method according to claim 1,
Wherein the fifth MOS is a drain connected to a common node of each of the sources of the first and fourth MOSs, and the source is connected to a power supply (Vdd).
The method according to claim 1,
Wherein the first, fourth, and fifth MOSs are PMOSs.
The method according to claim 1,
Wherein the first MOS is further provided with a second MOS, and the fourth MOS further comprises a third MOS.
5. The method of claim 4,
The drain of the second MOS is connected to the drain of the first MOS, and the source of the second MOS is connected to the power supply (Vdd).
5. The method of claim 4,
A drain of the third MOS is connected to a drain of the fourth MOS, and a source of the third MOS is connected to a power supply (Vdd).
5. The method of claim 4,
And the second and third MOSs are PMOSs.
KR1020130032917A 2013-03-27 2013-03-27 Ring-type Voltage Controlled Oscillator KR20140117938A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160087557A (en) 2015-01-14 2016-07-22 한양대학교 산학협력단 Voltage controlled oscillator for realizing multi-phase
US10340929B2 (en) 2015-12-10 2019-07-02 Yonsei University Industry-Academic Cooperation Foundation Voltage controlled oscillator and phase locked loop comprising the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160087557A (en) 2015-01-14 2016-07-22 한양대학교 산학협력단 Voltage controlled oscillator for realizing multi-phase
US10340929B2 (en) 2015-12-10 2019-07-02 Yonsei University Industry-Academic Cooperation Foundation Voltage controlled oscillator and phase locked loop comprising the same

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