KR20140091399A

KR20140091399A - Liquid crystal display device and driving circuit thereof

Info

Publication number: KR20140091399A
Application number: KR1020130003620A
Authority: KR
Inventors: 장세현
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-01-11
Filing date: 2013-01-11
Publication date: 2014-07-21
Also published as: KR102051389B1

Abstract

The present invention discloses a driving circuit of a liquid crystal display device. In particular, the present invention relates to a driving circuit for reducing the number of terminals of a power management IC (PM-IC) for supplying power for driving a liquid crystal display device, To a liquid crystal display device.
A liquid crystal display according to an embodiment of the present invention includes a liquid crystal panel, a gate, a data driver, and a timing controller. The first and second pull-down thin film transistors are supplied with a driving voltage interface signal from the timing controller, And a PM-IC section for generating first and second driving voltages which are alternately driven. Accordingly, by generating two driving voltages in accordance with one driving voltage interface signal, the input / output terminals of the PM-IC can be reduced to lower the production cost of the IC and replace with other additional terminals.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a driving circuit thereof,

The present invention relates to a driving circuit of a liquid crystal display, and more particularly to a driving circuit for a liquid crystal display, which reduces the number of terminals of a PM-IC (power management IC) for supplying power for driving a liquid crystal display, And a liquid crystal display device including the same.

2. Description of the Related Art [0002] With the development of information devices such as potable devices such as mobile phones and notebook computers and high-resolution and high-quality images such as HDTVs, flat panel displays Display Device) is increasing. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

In particular, an active matrix type liquid crystal display device in which a thin film transistor (TFT) is used as a switching element is suitable for displaying dynamic images.

FIG. 1 schematically shows a part of a conventional liquid crystal display device. The conventional liquid crystal display device includes a liquid crystal panel 10 in which a plurality of pixels (not shown) are defined and displays an image, And a gate driver 20 for supplying a gate output signal to the pixels through a plurality of gate lines GL formed in the direction of the gate lines GL.

The gate driver 20 includes a plurality of stages, and each stage sequentially supplies a gate output signal VG for each pixel on the same horizontal line through the gate line GL corresponding to various gate control signals. This stage ST includes at least one flip-flop 12, a pull-up transistor TPU and pull-down transistors TPD_o and TPD_e.

In particular, at least two pull-down transistors TPD_O and TPD_E for applying the ground voltage VSS are provided in the pull-up transistor TPU for applying the high-level clock signal CLK, And prevents the deterioration of the transistor due to the high voltage continuously applied by driving.

In detail, each stage ST always outputs the gate-low voltage VGL except for one horizontal period (1H) for one frame, so that the Qb output has a high level for turning on the pull- The voltage is applied continuously. This causes the pull-down transistor to deteriorate to change the threshold voltage characteristic, resulting in malfunction of the gate driver.

In order to solve such a problem, a plurality of Qb outputs (Qb_o, Qb_e) are formed, and pull-down transistors TPD_o and TPD_e are provided, , TPD_e) to minimize the deterioration of the device.

However, in order to control the two pull-down transistors TPD_o and TPD_e, two driving voltages VDD_o and VDD_e having inverted waveforms are required. This driving voltage is generated by receiving two driving voltage interface signals from a timing controller (not shown), which generates various signals for driving the liquid crystal display device. Here, the two driving voltages VDD_o and VDD_e should be generated such that the waveforms are not completely inverted but have a delay period in which both the voltages become low levels at the time of the voltage level change. Therefore, It is not possible to generate two driving voltages VDD_o and VDD_e in the form of inverting using a circuit.

Accordingly, the PM-IC unit (not shown) is implemented in such a manner that two input terminals are allocated to receive a driving voltage interface signal and two output terminals to output two driving voltages VDD_o and VDD_e.

However, in accordance with the miniaturization trend of the liquid crystal display device and its driving circuit, the driving circuit of the liquid crystal display device should be designed so as to reduce the size of the driving IC by reducing the number of input / output terminals of the driving IC. Therefore, the liquid crystal display apparatus of the alternate driving type of the gate driving unit and its driving circuit have a limitation that it is difficult to reflect this tendency.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce input / output terminals of a driving circuit of a liquid crystal display device having at least two pull-down transistors and alternately driven.

In order to achieve the above object, a liquid crystal display device according to a preferred embodiment of the present invention includes: a liquid crystal panel defining a plurality of pixels by forming a plurality of gate wirings and data wirings; A gate driver connected to the gate line and supplying a gate output signal to the pixel, the gate driver including at least one pull-up thin film transistor, first and second pull-down thin film transistors; A data driver connected to the data line and supplying a data voltage to the pixel; A timing controller for generating control signals for the gate driver and the data driver; And a PM-IC unit for receiving the driving voltage interface signal from the timing control unit and generating first and second driving voltages for alternately driving the first and second pull-down thin film transistors, respectively.

Wherein the driving voltage interface signal is a signal in which a delay period in which the first and second driving voltages are simultaneously in a low level state is defined.

The first and second driving voltages are inverted voltages except for the delay period.

The PM-IC unit includes: a flip-flop for outputting first and second output signals inverted from each other corresponding to the driving voltage interface signal; A delay circuit for delaying the first and second output signals for a predetermined time; And an AND gate circuit for outputting the first and second driving voltages by ANDing the first and second output delay signals output from the delay circuit and the driving voltage interface signal, respectively.

The flip-flop is a negative-edge triggered flip-flop which inverts the first and second output signals when the driving voltage interface signal is a polling edge.

Wherein the gate driver comprises: a first thin film transistor for charging a Q node at a normal driving voltage level according to a front stage or a start signal; A second thin film transistor for receiving the gate output signal from the rear stage and discharging the Q node; A third I thin film transistor for discharging the Q node according to the charging of the Qb_o node; A third-e thin film transistor for discharging the Q node according to charging of the Qb_e node; A fourth I thin film transistor connected to the diode to charge the first driving voltage to the Qb_o node; A fourth-e thin film transistor connected to the diode to charge the second driving voltage (VDD_e) to the Qb_e node; A fifth transistor for discharging the Qb_o node according to the charging of the Q node; And a fifth transistor for discharging the Qb_e node according to the charging of the Q node.

The pull-up thin film transistor outputs the gate output signal corresponding to the voltage level of the clock signal according to the charging of the Q node, and the first pull-down thin film transistor has a ground voltage level And the second pull-down thin film transistor outputs the gate output signal of the ground voltage level according to the charging of the Qb_e node.

The first and second pull-down thin film transistors are alternately driven by 2 to 3 frames.

In order to achieve the above object, a driving circuit of a liquid crystal display according to a preferred embodiment of the present invention includes a flip-flop for outputting first and second output signals inverted from each other corresponding to a driving voltage interface signal applied from a timing controller, Flop; A delay circuit for delaying the first and second output signals for a predetermined time; The first and second output delay signals output from the delay circuit and the driving voltage interface signal are respectively multiplied together by a logical AND to obtain first and second driving voltages for driving the first and second pull- And an AND gate circuit for outputting the output signal.

According to the embodiment of the present invention, by generating one driving voltage interface signal having a low level interval corresponding to the delay period and generating two driving voltages inverted using an edge triggered element, the PM-IC It is possible to reduce the production cost of the IC and replace it with other additional terminals.

FIG. 1 is a schematic view showing a part of a conventional liquid crystal display device.
2 is a view showing the entire structure of a liquid crystal display device according to an embodiment of the present invention.
3 is an equivalent circuit diagram for a logic circuit for generating the first and second driving voltages included in the PM-IC part of the liquid crystal display device according to the embodiment of the present invention.
4 is a diagram showing signal waveforms input and output by the PM-IC unit.
5 is a view showing a connection of some terminals of a driving circuit of a liquid crystal display according to an embodiment of the present invention.
6 is an equivalent circuit diagram of one stage of a gate driver of a liquid crystal display according to an embodiment of the present invention.

Hereinafter, a liquid crystal display device and a driving circuit thereof according to preferred embodiments of the present invention will be described with reference to the drawings.

2 is a view showing the entire structure of a liquid crystal display device according to an embodiment of the present invention.

The liquid crystal display device of the present invention includes a liquid crystal panel 100 for displaying an image, a timing controller 110 for controlling the respective drivers 120 and 130, A gate driver 120 for applying a gate output signal VG to the gate line GL, a data driver 130 for applying a data signal VDATA to each pixel, and a plurality And a PM-IC unit 150 for supplying the gate driving unit 120 with the first and second gate driving voltages GVDD_o and GVDD_e for alternate driving.

In the liquid crystal panel 100, a plurality of gate lines GL and a plurality of data lines DL are intersected in a matrix form on a substrate using a glass, and a plurality of pixels PX are defined at intersections.

A plurality of pixels PX corresponding to the three primary colors of R, G, and B are formed in a matrix on the display region of the liquid crystal panel 100. At least one thin film transistor (serving as a switching element) T and a liquid crystal capacitor LC composed of upper and lower electrodes with a liquid crystal layer interposed therebetween to display an image.

In the above-described thin film transistor T, the gate electrode is connected to the gate wiring GL and the source electrode is connected to the data wiring DL. Further, the drain electrode is connected to the pixel electrode facing the common electrode. Amorphous silicon and polysilicon may be used as the material of the active layer of the thin film transistor T. However, as the liquid crystal display device is becoming larger and higher in quality, , There is a limitation in a conventional amorphous silicon thin film transistor having a mobility of 0.5 cm ² / Vs level, and oxide silicon may be used therefor.

In particular, since the oxide silicon thin film transistor has a higher mobility than an amorphous silicon thin film transistor, it has not only a switching element in the liquid crystal panel 100 provided in the liquid crystal display, but also a gate driver 120 for controlling the switching element It is advantageous to implement.

The timing controller 110 receives timing signals such as a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync and a data enable signal DE transmitted from an external system and supplies the timing signals to the gate driver 120 And a data driver 130. The data driver 130 generates a control signal. In addition, a digital image signal (RGB) to be transmitted is converted into a form that can be processed by the data driver 130 and supplied to the data driver 130.

Particularly, the timing controller 110 generates a drive voltage interface signal EO and a clock interface signal ICLK, which serve as a reference for generating a voltage and a clock signal for driving the gate driver 120, . Here, the driving voltage interface signal EO is a signal supplied to the PM-IC unit 150 through one signal line, and defines the delay period of the first and second gate driving voltages GVDD_o and GVDD_e.

The gate driver 120 is a shift register composed of a plurality of thin film transistors formed in a non-display region except one pixel region of the liquid crystal panel 100. [ Since the gate driver 120 is simultaneously formed in the same process as the thin film transistor on the pixel region of the liquid crystal panel 100, the gate driver 120 has the same semiconductor layer as the thin film transistor in the pixel region.

In particular, the gate driver 120 responds to a gate control signal GCS input from the timing controller 110, and performs a gate drive of a high level every horizontal period 1H through a gate line GL formed in the liquid crystal panel 100 And sequentially outputs the voltage VG. In addition, the gate line GL in which the current gate driving voltage VG is not outputted outputs a gate driving voltage VG at a low level. One stage is assigned to one gate line GL and a gate drive voltage VLG at a low level is applied to the other gate line GL except for the gate line GL which is currently high level among the stages of the gate driver 120 VG) is applied.

Accordingly, the thin film transistor T connected to the high level gate line GL is turned on, and at the same time, the data driver 130 supplies the data signal VDATA of the analog waveform to the data line DL to the liquid crystal capacitors LC connected to the thin film transistor T. [

In particular, the gate driving unit 120 has a structure in which the built-in thin film transistors are alternately driven by using one of the first and second gate driving voltages GVDD_o and GVDD_e.

For example, the gate driving unit 120 may be driven using the first gate driving voltage GVDD_o for the first three frames and may be driven using the second gate driving voltage GVDD_e during the next three frames .

Accordingly, the pull-down thin film transistors provided in two stages are alternately driven to minimize deterioration of the thin film transistor due to the stress.

The data driver 130 converts the video signal RGB of the aligned digital format input corresponding to the data control signal DCS input from the timing controller 110 into an analog data signal VDATA according to the reference voltage do. The data signal VDATA is latched in one horizontal line unit and output to the liquid crystal panel 100 simultaneously through all the data lines DL every one horizontal period (1H).

The PM-IC unit 150 receives the system power supply voltage VCC and supplies the power supply voltage VDD, the ground voltage VSS and the common power supply voltage VDC for driving the liquid crystal panel 100, the gate and data drivers 120 and 130, Voltage Vcom, and the like.

In addition, the PM-IC unit 150 receives one driving voltage interface signal EO and a plurality of clock interface signals ICLK n from the timing control unit 110 and controls the gate driving unit 120 Generates a first and a second gate driving voltages GVDD_o and GVDD_e for alternate driving and a plurality of clock signals CLK n and supplies them to the gate driver 120. [ To this end, the PM-IC unit 150 outputs a logic circuit that outputs a voltage of a low level or an inverted level in response to a falling edge and a rising edge of the driving voltage interface signal EO .

Hereinafter, a structure of a driving circuit of a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

3 is an equivalent circuit diagram for a logic circuit for generating first and second driving voltages included in a PM-IC part of a liquid crystal display device according to an embodiment of the present invention. Fig.

3 and 4, the present invention is characterized in that the first input terminal I is connected to the inverted output terminal

And the second input terminal C receives the driving voltage interface signal EO to receive the non-inverting output terminal

) And an inverting output stage

A flip-flop 152 for outputting signals inverted from each other in a non-inverting output stage

) And an inverting output stage

And a delay circuit 155 for holding the output signal of the first output delay signal DS1 and the second output delay signal DS2 by the logical product of the output signals of the first output delay signal DS1 and the second output delay signal DS2 and the drive voltage interface signal EO And an AND gate circuit 157 for outputting the first gate driving voltage GVDD_o and the second gate driving voltage GVDD_e.

The flip-flop 152 has a first input terminal I connected to an inverting output terminal

And the second input terminal C is connected to the timing control unit 110 of FIG. 2 to receive the driving voltage interface signal EO, and outputs two inverted signals in response to the driving voltage interface signal EO . Here, when the driving voltage interface signal EO is at the high level, the non-inverting output terminal (

), A high-level output signal is output, and an inverting output terminal

), A low-level output signal is output. When the driving voltage interface signal EO transits from a high level to a low level, that is, when a falling edge occurs in a signal applied to the second input terminal C, a non-

) And an inverting output stage

Are inverted from each other in the current state.

Here, the driving voltage interface signal EO is a reference signal for generating the first gate driving voltage GVDD_o and the second gate driving voltage GVDD_e, and specifically defines a delay period between the two voltages GVDD_o and GVDD_e Signal. The first and second gate driving voltages GVDD_o and GVDD_e do not completely coincide with signals having inverted waveforms and a delay period in which both of the voltages GVDD_o and GVDD_e become low levels at the time of voltage level change Should be set.

Therefore, the driving voltage interface signal EO is not fixed to one voltage level continuously for the first period when driving the liquid crystal display device, but includes a low level period corresponding to the delay period, and accordingly, the two voltages GVDD_o , GVDD_e) is delayed by a predetermined time to a high level.

In the embodiment of the present invention, the structure of the flip-flop 152 that changes the voltage level of the two gate driving voltages VDD_o and VDD_e at the time of the voltage level change based on the falling edge of the driving voltage interface signal EO Respectively. The flip-flop 152 receives the drive voltage interface signal EO in the form of an inverted clock waveform,

A negative edge triggered F / F may be used to feed back a second output signal of the first input terminal I to the first input terminal I.

The delay circuit 155 is composed of a first delay 1551 and a second delay 1552, and a non-inverting output terminal

) And an inverting output stage

) To the end gate circuit 157 so that the voltage level of the first and second output signals is inverted at the same time as the driving voltage interface signal EO and the voltage levels of the first and second output signals are simultaneously inverted Thereby preventing the error of the logical multiplication.

The AND gate circuit 157 outputs the first and second output delay signals DS1 and DS2 delayed by the first and second delay lines 1551 and 1552 and the drive voltage interface signal EO to the logical product And a first AND gate 1571 and a second AND gate 1572 for determining the delay period.

In detail, the flip-flop 152 outputs a non-inverting output terminal (

) And an inverting output stage

The output signal voltage level of the output signal of the output terminal is varied, and at least one output signal is outputted as a high level as only the inverted signal is always outputted. That is, when the first output delay signal DS1 is at the low level, the second output delay signal DS2 becomes the high level. When the drive voltage interface signal EO transits to the low level, the first end gate 1571 receives the low level drive voltage interface signal EO and the first output delay signal DS1, The first gate driving voltage GVDD_o is outputted. At the same time, a low-level driving voltage interface signal EO and a high-level second output delay signal DS2 are applied to the second AND gate 1572 to output a low-level second gate driving voltage GVDD_e, The interval begins.

Thereafter, the delay period ends as the driving voltage interface signal EO transitions to the high level, and since the flip-flop 152 is of the negative edge type, the non-inverting output stage (

) And an inverting output stage

Of the output signal voltage level of the output signal of the output terminal is not generated. However, a high level driving voltage interface signal EO and a high level second output delay signal B are applied to the second AND gate 1572 to output a high level second gate driving voltage GVDD_e .

5 is a view showing a connection of some terminals of a driving circuit of a liquid crystal display according to an embodiment of the present invention.

As shown in the figure, the PM-IC unit 150, which is a driving circuit of the liquid crystal display of the present invention, operates by receiving the system power supply voltage VCC, and has SCL and SDA terminals for I2C data communication as input terminals, A clock reset signal ICLK_RESET terminal and a drive voltage interface signal EO which are used to generate clock signals CLK1 to CLK4, And an input terminal. A plurality of clock signals CLK1 to CLK4 output terminals controlled by a resistor R and first and second gate driving voltages GVDD_o and GVDD_e output terminals as output terminals.

Although not shown, the driving voltage interface signal EO input terminal and the first and second gate driving voltages GVDD_o and GVDD_e are connected to the circuit of FIG.

According to this structure, according to the PM-IC unit 150 of the present invention, by reducing the number of the input terminals of the driving voltage interface signal EO compared to the conventional one, it is possible to lower the production cost of the IC, Terminal.

Hereinafter, an example of a gate driver of a liquid crystal display driven by the first and second gate driving voltages GVDD_o and GVDD_e supplied from the PM-IC unit according to the embodiment of the present invention will be described with reference to the drawings.

6 is an equivalent circuit diagram of one stage of a gate driver of a liquid crystal display according to an embodiment of the present invention.

The gate driver includes a plurality of stages st, and one stage st comprises a plurality of thin film transistors. The figure shows an example of a shift register in which Qb_e node Qb_e and Qb_o node Qb_o are alternately charged and discharged in units of a predetermined frame.

Referring to FIG. 6, the gate driver of the present invention includes a first thin film transistor (TFT) for receiving a gate output signal (VG n-1) or a start signal from the front stage and charging the Q node A second thin film transistor T2 for receiving the gate output signal VG n + 1 from the rear stage and discharging the Q node Q; a second thin film transistor T2 for discharging the Q node Qb_o according to the charging of the Qb_o node Qb_o; A third-e thin film transistor T3_e for discharging the Q-node Q in response to the charging of the Qb_e node Qb_e, and a third driving transistor T3_e for diode- A fourth-e thin film transistor T4_o for charging the second driving voltage VDD_e to the Qb_e node Qb_o and a fourth-e thin film transistor T4_e for charging the second driving voltage VDD_e to the Qb_e node Qb_e; A fifth transistor (T5_o) for discharging the Qb_o node (Qb_o) according to the charging of the node (Q), and a fifth transistor A fifth-e transistor T5_e for discharging the Qb_e node Qb_e and a pull-up thin film VG for outputting a gate output signal VG corresponding to the voltage level of the clock signal CLK n in response to the charging of the Q node Q, A first full-down thin film transistor TPD_o for outputting a gate output signal VG at the ground voltage level in accordance with the charging of the Qb_o node Qb_o and a second pull- And a second pull-down thin film transistor TPD_o for outputting a gate output signal VG of a voltage level.

The operation of the gate driver according to the present invention according to this structure will be described. First, the first thin film transistor T1 is turned on according to the gate output signal VG n-1 of the front stage in any two to three frames, And the pull-up thin film transistor is turned on to output the high-level clock signal CLK to the gate output signal VG n. This gate output signal VG n is held for one horizontal period.

Thereafter, when the high level first gate driving voltage GVDD_o transitions to the high level, the fourth_o thin film transistor T4_o is turned on to charge the Qb_o node Qb_o, and accordingly the third_o thin film transistor T3_o is turned on, And discharges the voltage charged in the Q node Q. At the same time, the second thin film transistor T2 is also turned on so that the discharge of the Q node Q progresses rapidly. As a result, the pull-up transistor TPU is turned off.

Then, when the charging of the Qb_o node Qb_o is completed, the first pull-down thin film transistor TPD_o is turned on to output the gate output signal VG n of the ground voltage level.

As the first gate driving voltage GVDD_o transitions to the low level and the second gate driving voltage GVDD_e transitions to the high level during the next two to three frames, the Qb_e node Qb_e are charged, the second pull-down thin film transistor TPD_e is turned on through the above-described process to output the gate output signal VG n having the ground voltage level.

While a number of embodiments have been described in detail above, it should be construed as being illustrative of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100: liquid crystal panel 110: timing controller
120: Gate driver 130: Data driver
150: PM-IC part GL: Gate wiring
DL: Data wiring PX: Pixel
T: thin film transistor LC: liquid crystal capacitor
EO: drive voltage interface signal CLK: clock signal
R, G, B: data signal Hsync: horizontal synchronization signal
Vsync: Vertical synchronization signal DE: Enable signal
GCS: Gate control signal DCS: Data control signal
VCC: system power supply voltage VDD: general drive voltage
VSS: ground voltage Vcom: common voltage
ICLK: clock interface signal GVDD_o: first driving voltage
GVDD_e: the second driving voltage

Claims

A liquid crystal panel in which a plurality of gate wirings and data wirings are formed to define a plurality of pixels;
A gate driver connected to the gate line and supplying a gate output signal to the pixel, the gate driver including at least one pull-up thin film transistor, first and second pull-down thin film transistors;
A data driver connected to the data line and supplying a data voltage to the pixel;
A timing controller for generating control signals for the gate driver and the data driver; And
And a PM-IC portion for generating first and second driving voltages for alternately driving the first and second pull-down thin film transistors by receiving one driving voltage interface signal from the timing control portion,
And the liquid crystal display device.

The method according to claim 1,
Wherein the drive voltage interface signal comprises:
Wherein a delay period in which the first and second driving voltages are simultaneously in a low level state is defined.

3. The method of claim 2,
The first and second driving voltages are
Wherein the voltage is inverted from each other except for the delay period.

The method according to any one of claims 1 and 2,
The PM-
A flip-flop for outputting first and second output signals inverted from each other corresponding to the driving voltage interface signal;
A delay circuit for delaying the first and second output signals for a predetermined time; And
And an AND gate circuit which outputs the first and second driving voltages by multiplying the first and second output delay signals output from the delay circuit by the driving voltage interface signal,
And the liquid crystal display device.

5. The method of claim 4,
The flip-
Wherein the negative edge triggered flip-flop is a negative edge triggered flip-flop which inverts the first and second output signals when the driving voltage interface signal is a polling edge.

The method according to claim 1,
Wherein the gate driver comprises:
A first thin film transistor for charging the Q node with a normal driving voltage level according to a front stage or a start signal;
A second thin film transistor (T2) receiving a gate output signal from the rear stage and discharging the Q node;
A third I thin film transistor for discharging the Q node according to the charging of the Qb_o node;
A third-e thin film transistor for discharging the Q node according to charging of the Qb_e node;
A fourth I thin film transistor connected to the diode to charge the first driving voltage to the Qb_o node;
A fourth-e thin film transistor connected to the diode to charge the second driving voltage (VDD_e) to the Qb_e node;
A fifth transistor for discharging the Qb_o node according to the charging of the Q node; And
And a fifth transistor for discharging the Qb_e node according to the charging of the Q node.

The method according to claim 6,
The pull-up thin film transistor outputs the gate output signal corresponding to the voltage level of the clock signal in response to charging of the Q node,
The first pull-down thin film transistor outputs the gate output signal of the ground voltage level according to the charging of the Qb_o node,
The second pull-down thin film transistor may be configured to output the gate output signal of the ground voltage level in accordance with the charging of the Qb_e node
And the liquid crystal display device.

The method according to claim 1,
Wherein the first and second pull-down thin film transistors are alternately driven by 2 to 3 frames.

A flip-flop for outputting first and second output signals inverted from each other corresponding to a driving voltage interface signal applied from a timing control unit;
A delay circuit for delaying the first and second output signals for a predetermined time; And
The first and second output delay signals output from the delay circuit and the driving voltage interface signal are respectively multiplied together by a logical AND to obtain first and second driving voltages for driving the first and second pull- An AND gate circuit for outputting
And a driving circuit for driving the liquid crystal display device.

10. The method of claim 9,
Wherein the drive voltage interface signal comprises:
Wherein a delay period in which the first and second driving voltages are simultaneously in a low level state is defined in the driving circuit of the liquid crystal display device.

11. The method of claim 10,
Wherein the first and second driving voltages comprise:
Wherein the voltage is inverted from each other except for the delay period.

10. The method of claim 9,
The flip-
And a negative edge triggered flip flop for inverting and outputting the first and second output signals when the driving voltage interface signal is a polling edge.