KR20140088929A - Semiconductor substrate - Google Patents

Semiconductor substrate Download PDF

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Publication number
KR20140088929A
KR20140088929A KR1020120146204A KR20120146204A KR20140088929A KR 20140088929 A KR20140088929 A KR 20140088929A KR 1020120146204 A KR1020120146204 A KR 1020120146204A KR 20120146204 A KR20120146204 A KR 20120146204A KR 20140088929 A KR20140088929 A KR 20140088929A
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South Korea
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region
layer
regions
seed layer
content
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KR1020120146204A
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Korean (ko)
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이계진
이동건
음정현
김태홍
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주식회사 엘지실트론
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Publication of KR20140088929A publication Critical patent/KR20140088929A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The semiconductor substrate includes a seed layer disposed on a growth substrate, a buffer layer disposed on the seed layer, and a conductive semiconductor layer disposed on the buffer layer. The buffer layer includes a plurality of regions, and the plurality of regions include a first region in contact with the seed layer, a second region adjacent to the first region, and regions other than the first and second regions. The seed layer and the plurality of regions include Al. The Al content difference between the seed layer and the first region is 30% to 60%.

Description

[0001]

An embodiment relates to a semiconductor substrate.

Various electronic devices using compound semiconductor materials have been developed.

As the electronic device, a solar cell, a photodetector, or a light emitting device can be used.

Such an electronic device may have various defects due to a lattice constant, a thermal expansion coefficient or a strain difference between a growth substrate and a compound semiconductor layer formed thereon.

Differences in lattice constant and thermal expansion coefficient between the growth substrate and the compound semiconductor layer cause stress. That is, the balance between the compressive strain at the time of growth of compound semiconductors and the tensile strain at the time of cooling to room temperature after the growth becomes inadequate, resulting in cracks in the compound semiconductor layer, The substrate breaks.

As described above, since the cracks are generated in the compound semiconductor layer, there is a limit in that the thickness of the conductive type semiconductor layer that has a substantial function as a solar cell, a photodetector, or a light emitting element is increased.

The embodiment provides a semiconductor substrate that can control stress to prevent crack defects in the conductive type semiconductor layer.

According to an embodiment, a semiconductor substrate includes a growth substrate; A seed layer disposed on the growth substrate; A buffer layer disposed on the seed layer; And a conductive semiconductor layer disposed on the buffer layer. Wherein the buffer layer includes a plurality of regions, the plurality of regions including a first region in contact with the seed layer, a second region adjacent to the first region, and regions remaining except for the first and second regions, The seed layer and the plurality of regions include Al. The difference in Al content between the seed layer and the first region is 30% to 60%.

According to an embodiment, a semiconductor substrate includes a growth substrate; A seed layer disposed on the growth substrate; A buffer layer disposed on the seed layer; And a conductive semiconductor layer disposed on the buffer layer. The buffer layer includes a plurality of regions, and the plurality of regions include a first region in contact with the seed layer, a second region adjacent to the first region, and regions other than the first and second regions. The seed layer is Al x1 Ga (1-x1) include N, and wherein the first region comprises Al x2 Ga (1-x2) N, and the second area Al x3 Ga (1-x3) N . The difference between x2 and x1 is 0.3 to 0.6.

The semiconductor substrate according to the embodiment has a buffer layer including a plurality of step regions having different Al contents, and the Al content of the step region of the lowermost region of the buffer layer in contact with the seed layer is at least 30% smaller than the Al content of the seed layer So that the shrinkable stress can be maximized and a thick, crack-free conductive semiconductor layer can be grown.

1 is a cross-sectional view showing a semiconductor substrate according to an embodiment.
Fig. 2 is a view showing Al content in each step region of the buffer layer of Fig. 1; Fig.
3 is a graph showing a stress state according to the difference in Al content between the seed layer and the first step region.
4 is a graph showing a stress state according to a difference in Al content between the second step region and the third step region.
5 is a view showing a stress state according to the number of step regions.
6A to 6C are diagrams showing the surface state of the semiconductor substrate according to the number of step regions.
7 is a view showing a stress state according to the thickness of the step region.
8A and 8B are diagrams showing the surface state of the semiconductor substrate according to the thickness of the step region.
9 is a diagram showing the thickness of the conductive semiconductor of the semiconductor substrate according to the embodiment.

In describing an embodiment according to the invention, in the case of being described as being formed "above" or "below" each element, the upper (upper) or lower (lower) Directly contacted or formed such that one or more other components are disposed between the two components. Also, in the case of "upper (upper) or lower (lower)", it may include not only an upward direction but also a downward direction based on one component.

1 is a cross-sectional view showing a semiconductor substrate according to an embodiment.

1, a semiconductor substrate according to an embodiment includes a growth substrate 1, a seed layer 3, a buffer layer 20, a nitride semiconductor layer 30, a stress control layer 40, and a conductive semiconductor layer 50 ).

The semiconductor substrate according to the embodiment can serve as a base substrate for manufacturing an electronic device, that is, a solar cell, a photodetector or a light emitting device, but the present invention is not limited thereto.

The seed layer 3, the buffer layer 20, the nitride semiconductor layer 30, the stress control layer 40 and the conductive semiconductor layer 50 are formed of a Group II-VI and / or Group III-V compound semiconductor But it is not limited thereto.

The growth substrate 1 may be formed of at least one selected from the group consisting of sapphire (Al 2 O 3), SiC, Si, GaAs, GaN, ZnO, GaP, InP and Ge. Preferably, the growth substrate 1 may comprise Si, but is not limited thereto.

The seed layer 3 can easily form an epitaxial layer formed on the growth substrate 1, that is, the buffer layer 20, the nitride semiconductor layer 30, the stress control layer 40 and the conductive semiconductor layer 50 And can serve as a seed for forming the seed layer.

The seed layer 3 may be Al x Ga (1-x1) N, but is not limited thereto. X1 may be from 0.7 to 1, but is not limited thereto.

The seed layer 3 can be grown at a high temperature, for example, from 1050 캜 to 1100 캜, but is not limited thereto. That is, the seed layer 3 may be grown at a low temperature, for example, 900 占 폚. The film quality of the seed layer 3 comes close to the amorphous state and is less influenced by the crystal structure of the growth substrate 1 when grown at a low temperature so that lattice mismatching between the growth substrate 1 and the seed layer 3 lattice mismatch) may be less likely to occur.

A stress due to a dislocation or a lattice constant and a thermal expansion coefficient due to a lattice constant may be generated between the growth substrate 1 and the epi layer. This stress can contribute to generation of cracks in the conductive semiconductor layer 50 directly or indirectly.

In order to alleviate such defects, for example, a buffer layer 20 may be grown between the seed layer 3 and the conductive semiconductor layer 50

The difference in lattice constant between the growth substrate 1 and the conductive type semiconductor layer 50 can be alleviated by the buffer layer 20 and the potential generated in the conductive type semiconductor layer 50 can be suppressed.

The buffer layer 20 can be grown at, for example, 1050 캜 to 1100 캜, but is not limited thereto. Preferably, the buffer layer 20 can be grown at 1070 캜, but it is not limited thereto.

The nitride semiconductor layer 30 may be grown on the buffer layer 20. The nitride semiconductor layer 30 may be GaN, but the present invention is not limited thereto.

The nitride semiconductor layer 30 may have tensile strain that may be generated in the seed layer 3 due to a difference in lattice constant and thermal expansion coefficient from the growth substrate 1 to a compressive strain ), But the present invention is not limited thereto.

After the conductive semiconductor layer 50 is grown, a cooling process to a normal temperature is performed. By this cooling process, the semiconductor substrate according to the embodiment is subjected to tensile stress. Therefore, when the epitaxial layer is grown on the growth substrate 1, it is necessary to increase the shrinkable stress beforehand so that the shrinkable stress cancels the tensile stress generated in the cooling process to the room temperature and ultimately maintains the equilibrium of the stress So that cracks are not generated in the conductive semiconductor layer 50 and the growth substrate 1 is not broken.

The nitride semiconductor layer 30 may be an undoped semiconductor layer containing no dopant, but the present invention is not limited thereto. That is, the nitride semiconductor layer 30 may be a conductive semiconductor layer 50 including a dopant.

The stress control layer 40 may be grown on the nitride semiconductor layer 30. The stress control layer 40 may further increase the shrinkage stress caused by the nitride semiconductor layer 30 in order to maintain an equilibrium state of the stress at a later cooling time.

The stress control layer 40 may be grown at a low temperature, for example, 850 캜 to 950 캜, but is not limited thereto. That is, the stress control layer 40 may be grown at a high temperature, for example, 1050 to 1100 占 폚.

The stress control layer 40 may be AlN, but it is not limited thereto.

The lattice constant of the stress control layer 40 including AlN is smaller than the lattice constant of the nitride semiconductor layer 30 including GaN, so that the shrinkable stress can be larger.

The stress control layer 40 may have a multilayer structure of AlGaN / AlN / AlGaN, but it is not limited thereto. In this case, the Al content of AlGaN can be varied linearly or stepwise, but not limited thereto.

The stress control layer 40 may have a multilayer structure in which a period including AlGaN / AlN / AlGaN is repeated, but the present invention is not limited thereto.

The stress control layer 40 may have a multilayer structure in which AlGaN and AlN are alternately formed, but the present invention is not limited thereto.

The conductive semiconductor layer 50 may be grown on the stress control layer 40. The conductive semiconductor layer 50 may include an n-type dopant, but the present invention is not limited thereto. That is, the conductive semiconductor layer 50 may include a p-type dopant. As the n-type dopant, Si, Ge, Sn, or the like may be used, but the present invention is not limited thereto. As the p-type dopant, Mg, Zn, Ca, Sr, and Ba may be used, but the present invention is not limited thereto.

The conductive semiconductor layer 50 may serve as a substantial function for realizing a solar cell, a photodetector, or a light emitting device.

For example, another conductive semiconductor layer may be grown on the conductive semiconductor layer 50 to realize the functions of a photodetector and a solar cell, but the present invention is not limited thereto.

For example, the active layer may be grown on the conductive semiconductor layer 50, and another conductive semiconductor layer may be grown on the active layer to realize the function of the light emitting device. However, the present invention is not limited thereto.

The conductive semiconductor layer 50 and the another conductive semiconductor layer may include dopants of opposite types. For example, when the conductive semiconductor layer 50 includes an n-type dopant, the another conductive semiconductor layer may include a p-type dopant, but the present invention is not limited thereto.

According to the semiconductor substrate according to the embodiment, the shrinkable stress can be increased as much as possible, and a crack-free and thick conductive semiconductor layer 50 can be grown.

For this, the buffer layer 20 may include a plurality of step regions 5, 7, 9, 11, 13, 15, 17 having different Al contents.

For example, as shown in FIG. 1, the buffer layer 20 may include first through seventh step regions 5, 7, 9, 11, 13, 15, 17, but it is not limited thereto.

The lowest region of the buffer layer 20 contacting the top surface of the seed layer 3 is the first step region 5 and the top region of the buffer layer 20 contacting the back surface of the nitride semiconductor layer 30 is the seventh May be the step region 17.

The first to seventh step regions 5, 7, 9, 11, 13, 15, and 17 may include Al x Ga (1-x) N. At this time, x may be different from each other in the first to seventh step regions 5, 7, 9, 11, 13, 15,

Therefore, the first step region 5 includes Al x Ga (1-x2) N, the second step region 7 includes Al x Ga (1-x3) N, The region 9 includes Al x Ga (1-x4) N, and the fourth step region 11 may include Al x5Ga (1-x5) N. The fifth step region 13 includes Al x Ga (1-x6) N, the sixth step region 15 includes Al x 7 Ga (1-x7) N, Region 17 may comprise Al x 8 Ga (1- x 9 ) N.

X2 of the first step region 5 may be smaller than x1 of the seed layer 3 by 0.3 to 0.6, but the present invention is not limited thereto.

If x1 is 1, that is, the seed layer 3 contains AlN, x2 of the first step region 5 may be 0.4 to 0.7.

The experimental data are shown in Table 1.

The seed layer (x1) The first step region (x2) ΔV1 Curvature Comparative Example 1 One 0.9 0.1 -78.3 Example 1 One 0.7 0.3 -92.8 Example 2 One 0.5 0.5 -97.5

In Comparative Example 1, the Al content difference between the seed layer and the first step region was 0.1, and in Example 1, the Al content difference (x2-x1) between the seed layer 3 and the first step region 5 was 0.3 In Example 2, the Al content difference (x2-x1) between the seed layer 3 and the first step region 5 is 0.5.

Referring to Table 1 and FIG. 3, in Comparative Example 1, the shrinkable stress is 78.3. In contrast, in Example 1, the shrinking stress was 92.8, and in Example 3, the shrinking stress was 97.5.

From this, it is confirmed that the difference in Al content between the seed layer 3 and the first step region 5 has a maximum shrinkage stress at 0.3 to 0.6.

The x3 of the second step region 7 may be smaller than the x2 of the first step region 5 by 0.2 to 0.4, but is not limited thereto.

The experimental data are shown in Table 2.

The first step region (x2) The second step region (x3) ? V2 Curvature Comparative Example 2 0.5 0.425 0.075 -64.0 Example 3 0.7 0.425 0.275 -81.8

In Comparative Example 2, the Al content difference (x3-x2) between the first step region and the second step region was 0.075, and in Example 3, the Al content between the first step region 5 and the second step region 7 The difference (x3-x2) is 0.275.

Referring to Table 2 and FIG. 4, in Comparative Example 2, the shrinking stress is -64, whereas in Example 3, the shrinking stress is -81.8.

It can be seen from this that the difference in Al content (x3-x2) between the first step region 5 and the second step region 7 can increase the shrinkage stress at 0.2 to 0.4.

The Al contents of the third to seventh step regions 9, 11, 13, 15, and 17 may be linearly or non-linearly reduced, but the present invention is not limited thereto.

For example, the Al contents of the third to seventh step regions 9, 11, 13, 15 and 17 are 0.5, 0.4, 0.3, 0.3 and 0.1, DELTA V5, DELTA V6, DELTA V7) can be uniformly equal to 0.1.

For example, the Al contents of the third to seventh step regions 9, 11, 13, 15 and 17 are 0.5, 0.3, 0.2, 0.1 and 0.05, ,? V5,? V6,? V7) may not be constant. The Al content difference DELTA V4 between the third and fourth step regions 9 and 11 is 0.2 while the Al content difference DELTA V5 between the fourth and fifth step regions 11 and 13 may be 0.1 .

The semiconductor substrate according to the embodiment has a buffer layer 20 including a plurality of step regions 5, 7, 9, 11, 13, 15 and 17 having different Al contents, The Al content of the step region 5 in the lowermost region of the buffer layer 20 is made to be at least 30% smaller than the Al content of the seed layer 3 to maximize the shrinkable stress, Lt; / RTI >

The number of the step regions 5, 7, 9, 11, 13, 15, and 17 included in the buffer layer 20 may be 5 to 10, but the present invention is not limited thereto.

5, 7, 9, 11, 13, and 15 show the case where the number of the step areas is 3, the number of the step areas is 5, , 17) is seven.

As shown in FIG. 5, the shrinking stress of 4 is larger than that of Comparative Example 3, and the shrinking stress of Example 4 is larger than that of Comparative Example 4.

6A shows the state of the semiconductor substrate in Comparative Example 3 in FIG. 5, that is, the state of the conductive type semiconductor layer, and FIG. 6B shows the surface state of the conductive type semiconductor layer in Comparative Example 4 in FIG. 5 , And FIG. 6C shows the state of the conductive type semiconductor layer in the fourth embodiment of FIG.

As shown in Fig. 6A, when the number of step regions was three (Comparative Example 3), cracks were severe.

As shown in Fig. 6B, when the number of step regions is 5 (Comparative Example 4), cracks are reduced.

As shown in Fig. 6C, when the number of the step areas 5, 7, 9, 11, 13, 15, 17 was 7 (Example 4), cracks did not occur in most cases.

Therefore, as the number of the step regions 5, 7, 9, 11, 13, 15, and 17 increases, the shrinkable stress increases and the increase in the shrinkable stress increases the conductivity type semiconductor layer 50 of the semiconductor substrate It was confirmed that the cracks did not decrease or occur.

From this, it was confirmed that when the number of steps of the buffer layer 20 was 5 to 10, there was almost no crack. When the number of step regions is 10 or more, there is a problem that the thickness of the buffer layer increases while cracks are removed.

Thicknesses of the step regions 5, 7, 9, 11, 13, 15, and 17 included in the buffer layer 20 may be different from each other or may be equal to each other.

Thicknesses of the step regions 5, 7, 9, 11, 13, 15, and 17 included in the buffer layer 20 may be 100 nm to 150 nm, but the thickness is not limited thereto. Preferably, the thickness of the step regions 5, 7, 9, 11, 13, 15, 17 included in the buffer layer 20 may be 130 nm, but the thickness is not limited thereto.

In Fig. 7, the thickness of each step region in Comparative Example 5 is 91 nm, and the thickness of each step region in Comparative Example 6 is 149.5 nm. Embodiment 5 is a case where the thickness of each step region 5, 7, 9, 11, 13, 15, 17 is 130 nm.

FIG. 8A shows the state of the conductive type semiconductor layer in Comparative Example 5 in FIG. 7, and FIG. 8B shows the state of the conductive type semiconductor layer in Embodiment 5.

When the thickness of each step region was smaller than that of Example 5 (Comparative Example 5), a large amount of cracks were generated in the conductivity type semiconductor layer as shown in FIG. 8A.

As shown in Fig. 8B, in the conductive type semiconductor layer 50 of Example 5, almost no crack occurred.

Although not shown, when the thickness of each step region is larger than that of the fifth embodiment (comparative example 6), the growth substrate of the semiconductor substrate according to the embodiment is broken. This is because in Comparative Example 6 of Fig. 7, since the shrinkable stress becomes too large, the shrinkable stress is gradually getting more tensile stress in order to become an equilibrium state (stress = 0) It can be seen that the growth substrate can not withstand the stress and breaks down before the state becomes.

Therefore, the thickness of each step region 5, 7, 9, 11, 13, 15, 17 of the buffer layer 20 may be 100 nm to 150 nm.

9, the Al content of each step region 5, 7, 9, 11, 13, 15, 17 included in the buffer layer 20 is adjusted and each step region 5, 7, 9, 11 , 13, 15 and 17 are optimized, the thickness of the conductive type semiconductor layer 50 can be increased to 2.84 μm.

1: growth substrate
3: Seed layer
5, 7, 9, 11, 13, 15, 17: step area
20: buffer layer
30: a nitride semiconductor layer
40: Stress control layer
50: conductive type semiconductor layer

Claims (22)

Growth substrate;
A seed layer disposed on the growth substrate;
A buffer layer disposed on the seed layer; And
And a conductive type semiconductor layer disposed on the buffer layer,
Wherein the buffer layer comprises a plurality of regions,
Wherein the plurality of regions include a first region in contact with the seed layer, a second region adjacent to the first region, and regions remaining except for the first and second regions,
Wherein the seed layer and the plurality of regions comprise Al,
And the Al content difference between the seed layer and the first region is 30% to 60%. The method according to claim 1,
Wherein an Al content of the seed layer is 70% to 100%. 3. The method of claim 2,
And the Al content of the seed layer is 100%, the Al content of the first region is 40% to 70%. The method according to claim 1,
Wherein an Al content of the first region is smaller than an Al content of the seed layer. 5. The method of claim 4,
And the Al content difference between the second region and the first region is 20% to 40%. 6. The method of claim 5,
Wherein an Al content of the second region is smaller than an Al content of the first region. The method according to claim 6,
Wherein the Al content difference between the second region and the first region is smaller than the Al content difference between the first region and the seed layer. 6. The method of claim 5,
And the Al contents in each of the remaining regions are equal to each other. 9. The method of claim 8,
And the Al contents in each of the remaining regions are different from each other. 10. The method of claim 9,
Wherein an Al content in each of the remaining regions is linearly variable. 10. The method of claim 9,
Wherein the Al content in each of the remaining regions is non-linearly variable. The method according to any one of claims 1 to 11,
Wherein the seed layer and the plurality of regions each comprise Al x Ga (1-x) N. The method according to any one of claims 1 to 11,
Wherein each of the plurality of regions has a thickness of 100 nm to 150 nm. The method according to any one of claims 1 to 11,
Wherein the number of the plurality of regions is 5 to 10. The method according to any one of claims 1 to 11,
And the thickness of the conductive type semiconductor layer is 2.84 占 퐉. 12. The method according to any one of claims 1 to 11,
A nitride semiconductor layer disposed on the buffer layer; And
And a stress control layer disposed between the nitride semiconductor layer and the conductive semiconductor layer. 17. The method of claim 16,
Wherein the stress control layer comprises AlN. 17. The method of claim 16,
Wherein the stress control layer has a multilayer structure of AlGaN / AlN / AlGaN. 17. The method of claim 16,
Wherein the stress control layer has a multi-layer structure in which a period including AlGaN / AlN / AlGaN is repeated. 17. The method of claim 16,
Wherein the stress control layer has a multilayer structure in which AlGaN and AlN are alternately arranged. Growth substrate;
A seed layer disposed on the growth substrate;
A buffer layer disposed on the seed layer; And
And a conductive type semiconductor layer disposed on the buffer layer,
Wherein the buffer layer comprises a plurality of regions,
Wherein the plurality of regions include a first region in contact with the seed layer, a second region adjacent to the first region, and regions remaining except for the first and second regions,
Wherein the seed layer comprises Al x Ga (1-x 1) N,
Wherein the first region comprises Al x Ga (1-x2) N,
The second region comprises Al x 3 Ga (1-x 3) N,
and a difference between x2 and x1 is 0.3 to 0.6. 22. The method of claim 21,
and a difference between x3 and x2 is 0.2 to 0.4.
KR1020120146204A 2012-12-14 2012-12-14 Semiconductor substrate KR20140088929A (en)

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