KR20140083363A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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KR20140083363A
KR20140083363A KR1020120153030A KR20120153030A KR20140083363A KR 20140083363 A KR20140083363 A KR 20140083363A KR 1020120153030 A KR1020120153030 A KR 1020120153030A KR 20120153030 A KR20120153030 A KR 20120153030A KR 20140083363 A KR20140083363 A KR 20140083363A
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local
line
pair
local line
line pair
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KR1020120153030A
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KR102034614B1 (en
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김성호
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에스케이하이닉스 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

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Abstract

A semiconductor memory device comprising: a bit line sense amplifying part for sensing and amplifying bit line pair data; a sense amplifier power supply part for supplying a source voltage and a sinking voltage to a bit line sense amplifier part; A column operation unit for transmitting bit line pair data in a pair of segment lines in response to a column selection signal; and a column operation unit for receiving a sourcing voltage or a sinking voltage from the sense amplification power supply unit and driving the data of the segment line pair into a local line pair And a local line driver for driving the semiconductor memory device.

Figure P1020120153030

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

TECHNICAL FIELD The present invention relates to a semiconductor design technique, and more specifically, to a semiconductor memory device that improves the data read operation speed.

2. Description of the Related Art Generally, a semiconductor memory device is a device for storing data in a plurality of memory cells or for reading stored data. The semiconductor memory device includes a plurality of bit lines, a plurality of word lines, A circuit for selecting a bit line and a word line, and peripheral circuits such as a plurality of sense amplifiers.

In particular, in order to select a cell of a semiconductor memory device, a row decoder which decodes a row address to generate a word line select signal XS for selecting a word line, And a column decoder for generating a column selection signal YS for selecting a bit line by decoding a column address.

1 is a circuit diagram showing a configuration of a read path in a semiconductor memory device according to the related art.

1, a conventional semiconductor memory device includes a bit line sense amplifier unit 10, a sense amplification power supply unit 20, a column operation unit 30, a local line driver unit 40, A local line sense amplification section 50, and a segment line operation control section 60.

The bit line sense amplification unit 10 senses and amplifies data on the bit line pair BL and BLB. Specifically, when the semiconductor memory device starts the read operation and the active command is input, the word line corresponding to the row address is activated in response thereto, and the bit line pair (BL, BLB) connected to the activated word line is activated The bit line sense amplification unit 10 detects data stored in the bit line pair BL and BLB, which are inevitably required to have a very small voltage difference because they are stored in the cell. And amplifies it to the set level. At this time, the sourecing voltage and the sinking voltage of the sense amplification supplied to the bit line sense amplifier unit 10 are determined by a core voltage (VCORE) which is frequently used as a data decision voltage of a cell in a general semiconductor memory device, ) And ground voltage (VSS), and other voltages may be used at the designer's discretion. The core voltage VCORE and the ground voltage VSS supplied to the bit line sense amplification unit 10 are supplied by the sense amplification power supply unit 20. In the following description, the sourcing voltage and the sinking voltage are set to be the core voltage VCORE and the ground voltage VSS, respectively.

The sense amplification power supply unit 20 supplies the core voltage VCORE and the ground voltage VSS to the bit line sense amplifier unit 10 in response to the sense amplifier control signals SAP, SAN and SADRV PCG, Thereby supplying the charge voltage VBLP.

The column operation section 30 outputs data stored in the bit line pair BL and BLB to the column select signal YI corresponding to the column command and the column address after the sense amplification is completed by the bit line sense amplifier section 10, To the segment line pair (SIO, SIOB).

The local line driver 40 drives the data of the segment line pair (SIO, SIOB) by the local line pair (LIO, LIOB). The reason why the same configuration as that of the local line driver 40 is necessary will be described again with reference to FIG.

The local line sense amplifying unit 50 senses and amplifies data stored in the local line pair LIO and LIOB and transfers the amplified data to the global input / output line GIO.

The segment line operation control unit 60 precharges the segment line pair SIO and SIOB to the precharge voltage VBLP in response to the segment line operation control signals SIOEQ and SIOPCGB.

2 is a block diagram showing a cell array configuration of a conventional semiconductor memory device.

Referring to FIG. 2, a cell array of a conventional semiconductor memory device includes a plurality of cell mats MAT [1: 4], ..., MAT [N-3: N] N-3: N], BLB [N-3: N], and BLB [1] : SIO [M-1: M], SIOB [M-1: M], and SIO [1: 2] Are connected in common to the segment line pair SIO [1: 2], SIOB [1: 2], ..., SIO [M-1: M], SIOB [M- The local line pair (LIO, LIOB) and the local line pair (LIO, LIOB) to which data contained in the SIOB [1: 2], SIOB [1: 2], ..., SIO [M- And a local line sense amplification unit 50 for sensing and amplifying data stored in the data lines LIO and LIOB.

Here, the local line pair LIO and LIOB are commonly connected to a plurality of cell mats MAT [1: 4], ..., and MAT [N-3: N] To the local line sense amplification unit 50, the data in the SIOB [1: 2], ..., SIO [M-1: M], and SIOB [M-1: M]. Thus, a significant amount of loading is applied to the local line pair LIO, LIOB, which causes the segment line pair SIO [1: 2], SIOB [1: 2], ..., SIO [M- M], and SIOB [M-1: M] to the local line sense amplification unit 50 is slow.

In order to solve such a problem, a local line driver 40 is added between the segment line pair (SIO, SIOB) and the local line pair (LIO, LIOB) as shown in FIG.

Referring to FIG. 1 again, the structure of the local line driver 40 as shown in FIG. 1 will be described in detail. As shown in FIG. 1, four NMOS transistors (4 NMOS series, N [1: 4] And one NMOS transistor (+ 1 NMOS sink, N5).

The reason why the local line driver 40 exists is that the segment line pair SIO [1: 2], SIOB [1: 2], ..., SIO [M-1: M], SIOB [ -1: M] to the local line sense amplification unit 50 is prevented from being slowed down. Therefore, it is known that the size of the transistors N [1: 5] included in the local line driver 40 is a factor affecting the slop of data held in the local line pair LIO and LIOB soon . That is, the larger the size of the transistors N [1: 5] included in the local line driver 40, the higher the slope of the data held in the local line pair LIO and LIOB, The smaller the size, the lower the slope of the data in the local line pair (LIO, LIOB) will be.

In addition, a slop of data held in the local line pair (LIO, LIOB) determines the operation timing of the local line sense amplification unit 50. For example, if the minimum local line pair (LIO, LIOB) sensing voltage required for the local line sense amplifier 50 to operate is 100 mV, a slop of data carried in the local line pair (LIO, LIOB) The higher the higher the local line pair (LIO, LIOB) sensing voltage will reach 100 mV at a faster rate. The minimum sense voltage of the local line pair (LIO, LIOB) required for the operation of the local line sense amplification part 50 is 100 mV means that the positive local line LIO of the local line pair LIO, And the local line LIOB have a voltage difference of at least 100 mV, the local line sense amplifier 50 can sense this and perform an amplifying operation.

The operation timing of the local line sense amplification part 50 is changed depending on how much the local line driver 40 makes the slop of the data in the local line pair LIO and LIOB. It means that the time consumed in the read operation can be changed. That is, in order to increase the speed of the read operation, it is essential to improve the slope of the local line pair (LIO, LIOB).

On the other hand, the easiest way to improve the slop of data in the local line pair (LIO, LIOB) in the structure of the local line driver 40 according to the prior art as shown in Fig. 1 By increasing the size of the transistors N [1: 5] included in the local line driver 40, it is possible to increase the slop of data held in the local line pair LIO and LIOB.

However, the increase in the size of the local line driver 40 means that the area occupies a large area, so that the size of the semiconductor memory device increases, resulting in a decrease in productivity due to a decrease in net die.

In order to increase the slop of data held in the local line pair LIO and LIOB while suppressing the overall size increase of the local line driver 40, A method of increasing the size of the four NMOS transistors (NMOS Series, N [1: 4]) and removing one NMOS transistor (+ 1 NMOS Sink, N5) for the sinking operation may be used.

However, if one NMOS transistor (+ 1 NMOS Sink, N5) for sinking operation among the components of the local line driver 40 is removed, the standby operation period of the semiconductor memory device, that is, There is a problem that the off current greatly increases in the section where the precharge is performed. Specifically, the segment line pair (SIO, SIOB) maintains the precharge voltage (VBLP) level in the section in which the segment line pair (SIO, SIOB) is precharged, All of the NMOS transistors N3 and N4 corresponding to the pair (SIO, SIOB) are turned on. This causes a problem that the off current greatly increases in the NMOS transistors N1 and N2 corresponding to the local line drive enable signal LSAEN.

Due to such a problem, there is a problem that the amount of current consumed in the stand-by operation period of the semiconductor memory device greatly increases the consumed current in the states of IDD2 and IDD6 which directly affect the size thereof.

A semiconductor memory device capable of improving data read operation speed while suppressing an increase in area is provided.

According to an aspect of the present invention, there is provided a bit line sense amplifier for sensing and amplifying bit line pair data. A sense amplification power supply for supplying a sourcing voltage and a sinking voltage to the bit line sense amplifier; A column operation unit for transmitting bit line pair data in a pair of segment lines in response to a column select signal; And a local line driver for receiving the sourcing voltage or the sinking voltage from the sense amplifier power supply unit and driving the data of the segment line pair into a local line pair.

The present invention described above may be used to share a sinking voltage source of a local line driver with a sinking voltage source of a bit line sense amplifier circuit or to source a sourcing voltage source of a local line driver to a source of a bit line sense amplifier circuit sharing with the sourcing voltage source, the data lead operation speed can be maintained at an optimum state while reducing the area occupied by the local line driver.

1 is a circuit diagram showing a configuration of a read path in a semiconductor memory device according to the related art.
2 is a block diagram showing a cell array configuration of a semiconductor memory device according to the related art;
3 is a circuit diagram showing a structure of a read path in a semiconductor memory device according to an embodiment of the present invention;
FIG. 4 is a timing diagram illustrating a read operation of the semiconductor memory device according to the embodiment of the present invention shown in FIG. 3; FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that the present invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, Is provided to fully inform the user.

3 is a circuit diagram showing a structure of a read path in a semiconductor memory device according to an embodiment of the present invention.

3, a semiconductor memory device according to an embodiment of the present invention includes a bit line sense amplifier 310, a sense amplifier power supply 320, a column driver 330, a local line driver 340, A local line sense amplification unit 350, and a segment line operation control unit 360. Here, the local line driver 340 includes a first local line driver 342, a second local line driver 344, a first transfer control unit 346, and a second transfer control unit 348. The sense amplification power supply unit 320 includes a sense amplification pullup supply unit 322, a sense amplification pull down supply unit 324, and a precharge voltage supply unit 326.

The bit line sense amplification unit 310 senses and amplifies data on the bit line pair BL and BLB. Specifically, when the semiconductor memory device starts the read operation and the active command is input, the word line corresponding to the row address is activated in response thereto, and the bit line pair (BL, BLB) connected to the activated word line is activated The bit line sense amplification unit 310 detects data stored in the bit line pair BL and BLB which are inevitably required to have a very small voltage difference because they are stored in the cell. And amplifies it to the set level. At this time, the sourecing voltage and the sinking voltage of the sense amplification supplied to the bit line sense amplifier 310 are set to a core voltage (VCORE) which is frequently used as a data decision voltage of a cell in a general semiconductor memory device, ) And ground voltage (VSS), and other voltages may be used at the designer's discretion. The core voltage VCORE and the ground voltage VSS supplied to the bit line sense amplification unit 310 are supplied by the sense amplification power supply unit 320. In the following description, the sourcing voltage and the sinking voltage are set to be the core voltage VCORE and the ground voltage VSS, respectively.

The sense amplification power supply unit 320 supplies the core voltage VCORE and the ground voltage VSS to the bit line sense amplification unit 310 in response to the sense amplifier control signals SAP, SAN and SADRV PCG, Thereby supplying the charge voltage VBLP. That is, the sense amplification power supply unit 320 supplies the core voltage VCORE and the ground voltage VSS to the bit line sense amplification unit 310 in the sense amplification operation period, the data stored in the cell can be used to amplify the data to the core voltage VCORE or the ground voltage VSS after sensing the bit line pair BL and BLB. The sense amplification power supply unit 320 simultaneously supplies the bit line precharge voltage VBLP to the bit line pair BL and BLB in the precharge operation period to equalize the bit line pair BL and BLB To be charged.

The sense amplification pull-up supply unit 322 of the sensing amplification power supply unit 320 responds to the sense amplification pull-up control signal SAP to output the core voltage VCORE, which is a sourcing voltage, To the sense amplification pull-up node PS of FIG. Therefore, the bit line sense amplifier 310 senses the data stored in the cell during the sense amplification operation period through the bit line pair BL and BLB and then outputs the bit line pair BL, And amplifies the bit line detected at a high level to the core voltage VCORE of the sense amplifier up-up node PS.

The sensing amplification pull down supply part 324 among the components of the sensing amplification power supply part 320 senses the ground voltage VSS which is the sinking voltage in response to the sense amplification pull down control signal SAN to the bit line sense amplification part 310 And supplies it to the amplification pull-down node NS. Therefore, the bit line sense amplifier 310 senses the data stored in the cell during the sense amplification operation period through the bit line pair BL and BLB and then outputs the bit line pair BL, Amplifies the bit line sensed at the low level to the ground voltage VSS of the sense amplification pull-down node NS.

The precharge voltage supply unit 326 of the components of the sense amplification power supply unit 320 supplies the bit line precharge voltage VBLP to the bit line sense amplifier unit 310 in response to the precharge control signal SADRV PCG To the amplification pull-up node PS and the sense amplification pull-down node NS simultaneously. Accordingly, the bit line sense amplification unit 310 equalizes the bit line pair BL and BLB to the bit line precharge voltage VBLP level during the precharge operation period.

The column operation unit 330 outputs data stored in the bit line pair BL and BLB to the column select signal YI corresponding to the column command and the column address after the sense amplification is completed by the bit line sense amplifier unit 310, To the segment line pair (SIO, SIOB). The transfer of the data in the bit line pair BL and BLB to the segment line pair SIO and SIOB means that the bit line pair BL and BLB are divided into the core voltage VCORE and the ground voltage VSS (SIO, SIOB) as it is. For example, when the core voltage VCORE is loaded on the positive bit line BL and the ground voltage VSS is applied to the sub bit line BLB among the pair of bit lines BL and BLB as a result of the sensing and amplifying operation of the bit line sense amplifier 310, The core voltage VCORE placed on the positive bit line BL is transferred to the positive segment line SIO as it is in the period in which the column selection signal YI is activated and the positive segment line SIO is transferred to the positive segment line SIO, Means that the voltage VCORE is applied and the ground voltage VSS placed on the sub bit line BLB is directly transferred to the sub segment line SIOB and the ground voltage VSS is loaded on the sub segment line SIOB do. That is, the column operation unit 330 transfers the voltage level of the bit line pair (BL, BLB) to the segment line pair (SIO, SIOB) through charge transfer.

The local line driver 340 drives the data of the segment line pair (SIO, SIOB) by the local line pair (LIO, LIOB). That is, the local line driver 340 generates the local line pair (LIO, LIOB) in response to the data of the segment line pair (SIO, SIOB) so that the local line pair (LIO, LIOB) .

The local line driver 340 according to the embodiment of the present invention drives any one of the local line pairs LIO and LIOB to the ground voltage VSS which is the sinking voltage and does not drive the other, So that the line pair (LIO, LIOB) can have more than the voltage level difference set between them. Since the local line driver 340 receives the ground voltage VSS as the sinking voltage from the sense amplification power supply unit 320, the local line driver 340 needs a component for receiving the ground voltage VSS in the local line driver 340 not.

That is, the local line driver 340 according to the embodiment of the present invention detects and amplifies any one of the local lines (LIO, LIOB) according to the logic level of the data stored in the segment line pair (SIO, SIOB) Pull-down drive to the ground voltage VSS supplied from the pull-down node NS. For example, if the core voltage VCORE is placed in the positive segment line SIO and the ground voltage VSS is placed in the sub-segment line SIOB of the segment line pair SIO, SIOB, the local line pair LIO, The sub local line LIOB corresponding to the middle segment line SIO is pulled down to the ground voltage VSS supplied from the sense amplification pull down node NS and the positive local line LIO corresponding to the sub segment line SIO Is not driven. Conversely, if the ground voltage VSS is placed in the positive segment line SIO and the core voltage VCORE is placed in the sub-segment line SIOB of the segment line pair SIO and SIOB, the local line pair LIO, LIOB, The local line LIO corresponding to the sub segment line SIO is not driven and the positive local line LIO corresponding to the sub segment line SIO is connected to the ground voltage VSS supplied from the sense amplifier pull- ).

The first local line driver 342 among the components of the local line driver 340 receives the data supplied via the sensing amplification pull down node in response to the data stored in the positive segment line SIO among the segment line pairs SIO and SIOB, And drives the secondary local line LIOB among the local line pairs LIO and LIOB with the voltage VSS. That is, the first local line driver 342 selects one of the local line pairs (LIO, LIOB) connected to the drain in response to the positive segment line SIO among the segment line pairs (SIO, SIOB) And an NMOS transistor N4 for controlling the current flowing from the sense amplifier pull-down node NS connected to the source to the sense amplifier pull-down node NS.

The second local line driver 344 among the components of the local line driver 340 receives the data supplied via the sense amplification pull-down node in response to the data stored in the sub segment line SIOB among the segment line pairs SIO, And drives the positive local line LIO of the local line pair LIO and LIOB with the voltage VSS. In other words, the second local line driver 344 selects one of the local line pairs (LIO, LIOB) connected to the drain in response to the sub-segment line (SIOB) among the segment line pairs (SIO, SIOB) And an NMOS transistor N3 for controlling the current flowing from the sense amplifier pull-down node NS connected to the source to the sense amplifier pull-down node NS.

The first transmission control unit 346 among the components of the local line driver 340 turns on the connection between the first local line driver 342 and the secondary local line LIOB in response to the local sense amplification enable signal LSAEN / OFF control. That is, in response to the local sense amplifier enable signal LSAEN applied to the gate, the first transfer control unit 346 connects the source line LIOB to the source of the local line pair LIO, LIOB connected to the drain And an NMOS transistor N2 for controlling the current flow to the drain of the NMOS transistor N4 of the first local line driver 342.

The second transfer control unit 348 among the components of the local line driver 340 turns on the connection between the second local line driver 344 and the local line LIO in response to the local sense amplification enable signal LSAEN / OFF control. The second transmission control unit 348 controls the second transmission control unit 348 in response to the local sense amplification enable signal LSAEN applied to the gate of the local transmission line LIO, And an NMOS transistor N1 for controlling the current flow to the drain of the NMOS transistor N3 of the local line driver 344. [

In the embodiment of the present invention described above, the local line driver 340 drives one of the local line pairs LIO and LIOB to the ground voltage VSS, which is the sinking voltage, and does not drive the other one, The local line pair (LIO, LIOB) can have more than the voltage level difference set between them.

However, the local line driver 340 drives one of the local line pairs LIO and LIOB to the power supply voltage VDD, which is the sourcing voltage, and the other one, so that the local line pair LIO and LIOB Can have more than the voltage level difference set between them. The local line driver 340 receives the power supply voltage VDD as a sourcing voltage from the sense amplification power supply unit 320 so that the power supply voltage VDD is supplied to the local line driver 340 No components are required.

Therefore, although not shown directly in the figure, the local line driver 340 receives either one of the local line pairs LIO and LIOB from the sense amplification pull-up node PS of the bit line sense amplification unit 310 The following description will be made on the basis of driving with a power supply voltage (VDD) which is a sourcing voltage.

First, if the core voltage VCORE is loaded in the positive segment line SIO and the ground voltage VSS is loaded in the sub-segment line SIOB of the segment line pair SIO and SIOB, The local local line LIO corresponding to the sub segment line SIOB without driving the sub local line LIOB corresponding to the positive segment line SIO in the local line pair LIO and LIOB is connected to the sense amplification pull- Up drive to the power supply voltage VDD supplied from the power supply PS. Conversely, if the ground voltage VSS is placed in the positive segment line SIO and the core voltage VCORE is placed in the sub-segment line SIOB of the segment line pair SIO and SIOB, the local line pair LIO, LIOB, The sub-local line LIOB corresponding to the middle segment line SIO is driven by the power supply voltage VDD supplied from the pull-up node PS and the positive local line LIO corresponding to the sub- Do not drive.

The first local line driver 342 among the components of the local line driver 340 responds to the data stored in the positive segment line SIO among the segment line pairs SIO and SIOB to output the sense amplification pull- And drives the secondary local line LIOB among the local line pairs LIO and LIOB with the power supply voltage VDD supplied thereto. That is, the first local line driver 342 is connected to the drain from the sense amplification pull-up node PS source-connected in response to the positive segment line SIO among the segment line pair (SIO, SIOB) And a PMOS transistor for controlling the current flowing in the local line LIOB among the local line pair LIO and LIOB.

The second local line driver 344 among the components of the local line driver 340 responds to the data stored in the sub segment line SIOB among the segment line pairs SIO and SIOB to connect the sense amplifier pull- And drives the positive local line LIO among the local line pair LIO and LIOB with the power supply voltage VDD supplied thereto. That is, the second local line driver 344 is connected to the drain from the sense amplification pull-up node PS source-connected in response to the sub-segment line SIOB among the segment line pair SIO, SIOB connected to the gate And a PMOS transistor for controlling the current flowing in the local line LIO among the local line pair LIO and LIOB.

The first transmission control unit 346 among the components of the local line driver 340 turns on the connection between the first local line driver 342 and the secondary local line LIOB in response to the local sense amplification enable signal LSAEN / OFF control. That is, in response to the local sense amplifier enable signal LSAEN applied to the gate, the first transfer control unit 346 controls the transfer of the local sense amplifier enable signal LSAEN to the drain of the first local line driver 342 connected to the source, And a PMOS transistor for controlling the flow of a current to the sub-local line LIOB among the pair of lines LIO and LIOB.

The second transfer control unit 348 among the components of the local line driver 340 turns on the connection between the second local line driver 344 and the local line LIO in response to the local sense amplification enable signal LSAEN / OFF control. The second transfer control unit 348 is responsive to the local sense amplification enable signal LSAEN applied to the gate and to the local line pair connected to the drain of the PMOS transistor of the second local line driver 344 connected to the source And a PMOS transistor for controlling the flow of a current to the positive local line LIO in the LIO, LIOB.

The local line sense amplification unit 350 senses and amplifies data stored in the local line pair LIO and LIOB and transfers the amplified data to the global input / output line GIO.

The segment line operation control unit 360 precharges the segment line pair SIO and SIOB to the precharge voltage VBLP in response to the segment line operation control signals SIOEQ and SIOPCGB.

FIG. 4 is a timing diagram illustrating the read operation of the semiconductor memory device according to the embodiment of the present invention shown in FIG.

Referring to FIG. 4, a semiconductor memory device according to an embodiment of the present invention includes a word line SWL < 0 > in response to an active command and a row address from logic 'low' (1), the operation is started.

When the operation starts, the bit line sense amplification unit 310 senses data of a cell and generates an instantaneous sense amplification pull-up control (hereinafter, referred to as &quot; The sense amplification power supply unit 320 provides the core voltage VCORE to the sense amplification pull-up node PS and sense amplification pull-down node NS while the signal SAP and the sense amplification pull-down control signal SAN are activated. When the sense amplification power supply unit 320 provides the core voltage VCORE to the sense amplification pull-up node PS and sense amplification pull-down node NS, the bit line sense amplification unit 310 generates a voltage The bit line pair BL and BLB having the level difference dV is amplified to the core voltage VCORE and the ground voltage VSS.

That is, at the time when the bit line sense amplifier 310 senses the data of the cell and the bit line pair BL and BLB have a difference in voltage level dV set between them, the sense amplifier power supply unit 320 operates Up node PS to the core voltage VCORE and drives the sense amplification pull-down node NS to the ground voltage VSS. Therefore, the bit line sense amplification unit 310 amplifies the bit line pair BL and BLB to the ground voltage VSS of the sense amplification pull-down node NS and the core voltage VCORE of the sense amplification pull-up node PS. .

When the bit line sense amplifier 310 senses the data of the cell and the bit line pair BL and BLB have a difference in voltage level dV between them, the sense amplifier power supply unit 320 operates Driving the sense amplification pull-down node NS to the ground voltage VSS means that the ground voltage VSS is also supplied to the local line driver 340. [ That is, since the local sense amplification enable signal LSAEN is not activated, the operation of the local line driver 340 is not started. However, before the operation of the local line driver 340 starts, the local line driver 340 It is possible to drive the local line pair LIO and LIOB to the ground voltage VSS very quickly at the start of the operation of the local line driver 340 because the ground voltage VSS is supplied to the local line driver 340. [ In other words, at the time of driving the local line pair (LIO, LIOB) to the ground voltage (VSS) according to the data of the segment line pair (SIO, SIOB) in the local line driver 340, the sense amplification pull- The local line driver 340 can drive the local line pair LIO and LIOB to the ground voltage VSS very quickly because the local line driver 340 has been lowered to the ground voltage VSS.

On the other hand, in the bit line sense amplifier unit 310, the bit line pair BL and BLB is sufficiently connected to the core voltage VCORE of the sense amplification pull-up node PS and the ground voltage VSS of the sense amplification pull- The column select signal YI corresponding to the column command and the column address is activated at a logic high level for a predetermined time and the column select signal YI is at a logic high level High), data of the bit line pair BL and BLB is transferred to the segment line pair SIO and SIOB. That is, since the positive bit line BL among the bit line pairs BL and BLB is the core voltage VCORE, the positive segment line SIO of the segment line pair SIO and SIOB has the core voltage VCORE level. Similarly, since the sub bit line BLB of the bit line pair BL and BLB is at the ground voltage VSS, the sub segment line SIOB of the segment line pair SIO and SIOB has the ground voltage VSS level.

Thus, when the data of the pair of bit lines BL and BLB is stored in the segment line pair SIO and SIOB, the local sense amplification enable signal LSAEN is activated to a logic 'high' And the local line driver 340 starts the operation (3).

As the local line driver 340 starts operating, it can be seen that the local line pair (LIO, LIOB) begins to have a voltage level difference with respect to each other. That is, since the core voltage VCORE is loaded in the positive segment line SIO of the segment line pair SIO and SIOB, the level of the sub-local line LIOB of the local line pair LIO and LIOB becomes the ground voltage VSS level Direction. Conversely, since the ground voltage VSS is placed on the sub segment line SIOB of the segment line pair SIO and SIOB, the level of the local line LIO in the local line pair LIO and LIOB is set to the core voltage VCORE level .

At this time, it can be seen that the voltage level of the secondary local line LIOB according to the embodiment of the present invention falls more close to the ground voltage VSS level at a higher rate than the voltage level of the secondary local line LIOB according to the related art. . In the embodiment of the present invention, the local line driver 340 receives the ground voltage VSS from the pull-down node NS of the sense amplifier power supply 320, And the transistor N5 for supplying the ground voltage VSS is separately provided.

Since the size of the transistor N5 can not be increased to some extent due to the area problem in the configuration in which the transistor N5 for supplying the ground voltage VSS is separately provided in the local line driver 40 in the prior art, The driving force also can not have a certain size or more.

However, in the present invention, the sense amplification power supply unit 320 supplies the ground voltage VSS to the pull-down node NS to supply the ground voltage VSS used for the operation of the bit line sense amplifier unit 310, The driving force is very large. Thus, in embodiments of the present invention in which the ground voltage VSS is supplied to the local line driver 340 with the ability to drive the ground voltage VSS at the sense amplification power supply 320, It is possible to drive the line.

Since the sensing amplification pull-down node NS is sufficiently lowered to the ground voltage VSS before the local sensing amplification enable signal LSAEN is activated to a logic high level, the local line driver 340 It is possible to drive the local line pair LIO, LIOB to the ground voltage VSS very quickly.

In summary, in the embodiment of the present invention, after the sensing amplification power supply unit 320 has completed its operation and sufficiently lowered to the target level of the ground voltage VSS, the local line driver 340 starts to operate, Since the supply unit 320 has a relatively large size, it is possible to drive the local line at a much higher speed in the local line driver 340. Therefore, assuming that the local line sense amplifier unit 350 starts operation when the local line pair LIO and LIOB have a voltage level difference of 100 mV from each other, as shown in the figure, The line sense amplification unit 350 can start to operate. In this way, the fact that the local line sense amplification unit 350 starts to operate more quickly means that the data read operation speed can be quickly taken.

Meanwhile, in the above-described embodiment, the local line driver 340 receives the ground voltage VSS through the sensing amplification power supply unit 320, and the operation has been described. However, the embodiment of the present invention also includes the case where the local line driver 340 receives the power supply voltage VDD through the sense amplification power supply unit 320. Accordingly, although not shown directly in the drawing, the local line driver 340 may operate in a manner such that any one of the local lines of the local line pairs LIO and LIOB rises to the power supply voltage VDD according to the embodiment of the present invention It is possible to increase the speed of the data read operation faster than that of the conventional technology.

As described above, according to an embodiment of the present invention, the sinking voltage supply source of the local line driver 340 can be shared with the sinking voltage supply source of the bit line sense amplifier 310, The data read operation speed is reduced while minimizing or minimizing the area occupied by the local line driver 340 by sharing the sourcing voltage supply source of the bit line sense amplifier unit 340 with the source voltage of the sourcing voltage of the bit line sense amplifier unit 310 It can be maintained in an optimum state.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. Will be apparent to those of ordinary skill in the art.

For example, the logic gates and transistors illustrated in the above embodiments should be implemented in different positions and types according to the polarity of input signals.

10, 310: Bit line sense amplifier section
20, 320: sense amplification power supply
30, 330: Column operation part
40, 340: local line driver
50, 350: local line sense amplifier section
60, 360: segment line operation control section

Claims (12)

A bit line sense amplification unit for sensing and amplifying bit line pair data;
A sense amplification power supply for supplying a sourcing voltage and a sinking voltage to the bit line sense amplifier;
A column operation unit for transmitting bit line pair data in a pair of segment lines in response to a column select signal;
A local line driver for receiving the sourcing voltage or the sinking voltage from the sense amplifier power supply and driving the data of the segment line pair into a local line pair,
And the semiconductor memory device.
The method according to claim 1,
The sensing amplification power supply unit includes:
A sense amplification pull-up supply section for supplying the sourcing voltage to the sense amplification pull-up node of the bit line sense amplification section in response to a sense amplification pull-up control signal; And
A sense amplification pull-down supply section for supplying the sinking voltage to the sense amplification pull-down node of the bit line sense amplification section in response to a sense amplification pull-
And the semiconductor memory device. 3. The method of claim 2,
Wherein the local line driver comprises:
Wherein one of the local lines in the local line pair is pulldowned to the sinking voltage supplied from the sense amplification pull-down node according to the logic level of the data in the segment line pair.
The method of claim 3,
Wherein the local line driver comprises:
A first local line driver for pulling down the sub-local line of the local line pair with the sinking voltage supplied through the sense amplification pull-down node in response to data on the positive segment line of the segment line pair; And
And a second local line driver for pulling down the positive local line of the local line pair to the sinking voltage supplied through the sense amplification pull-down node in response to data on the sub-segment line of the segment line pair. Device.
3. The method of claim 2,
Wherein the local line driver comprises:
And pull-up drives any one of the local lines of the pair of local lines to the sourcing voltage supplied from the sense amplifier pull-up node according to a logic level of data stored in the segment line pair.
The method according to claim 6,
Wherein the local line driver comprises:
A first local line driver for pulling up the sub-local line of the local line pair with the sourcing voltage supplied through the sense amplification pull-up node in response to data on the positive segment line of the segment line pair; And
And a second local line driver for pulling up the positive local line of the pair of local lines by the sourcing voltage supplied through the sense amplification pull-up node in response to data on the sub-segment line of the segment line pair Semiconductor memory device.
The method according to claim 4 or 6,
Wherein the local line driver comprises:
A first transmission control unit for on / off-controlling the connection between the first local line driver and the sub-local line in response to a local sense amplification enable signal; And
And a second transfer control section for on / off-controlling the connection of the second local line driver and the positive local line in response to the local sense amplification enable signal.
Supplying a sourcing voltage to the sense amplification pull-up node, and supplying a sinking voltage to the sense amplification pull-down node;
Sensing and amplifying bit line pair data using the source voltage supplied through the sense amplification pull-up node and the sinking voltage supplied through the sense amplification pull-down node as a sense amplification power supply;
Transmitting data of the bit-line pair sensed and amplified in a pair of segment lines in response to a column selection signal; And
And a data driver for receiving data of the segment line pair in response to a local line drive enable signal, wherein the data of the segment line pair is supplied to the sense amplification pull- Step of driving in a line pair
Wherein the semiconductor memory device is a semiconductor memory device.
9. The method of claim 8,
Wherein the step of driving with the local line pair comprises:
And connecting the segment line pair and the local line pair in an active period of the local line drive enable signal so that any one of the local lines in the pair of local lines is connected to the sense amplifier Pulling down the sinking voltage supplied from the pull-down node; And
Disconnecting the segment line pair and the local line pair in an inactive period of the local line drive enable signal
Wherein the semiconductor memory device is a semiconductor memory device.
10. The method of claim 9,
Wherein the pulling-down driving with the sinking voltage comprises:
Pulling down the sub-local line of the local line pair with the sinking voltage supplied through the sense amplification pull-down node in response to data on the positive segment line of the segment line pair; And
And pulling down the positive local line of the local line pair with the sinking voltage supplied through the sense amplification pull-down node in response to data on the sub-segment line of the segment line pair.
9. The method of claim 8,
Wherein the step of driving with the local line pair comprises:
And connecting the segment line pair and the local line pair in an active period of the local line drive enable signal so that any one of the local lines in the pair of local lines is connected to the sense amplifier Up driving with the sourcing voltage supplied from the pull-up node; And
Disconnecting the segment line pair and the local line pair in an inactive period of the local line drive enable signal
Wherein the semiconductor memory device is a semiconductor memory device.
12. The method of claim 11,
Wherein the step of pull-up driving with the sinking voltage comprises:
Up-driving the sub-local line of the local line pair with the sourcing voltage supplied through the sense amplification pull-up node in response to data on the positive segment line of the segment line pair; And
And pulling up the positive local line of the pair of local lines by the sourcing voltage supplied through the sense amplification pull-up node in response to data on the sub-segment line of the segment line pair. Way.
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KR20170102112A (en) * 2016-02-29 2017-09-07 에스케이하이닉스 주식회사 Sense amplifier and input/output circuit of semiconductor apparatus including the same
KR20190054468A (en) * 2017-11-13 2019-05-22 삼성전자주식회사 Memory device having global line groups which data input and output units are different from each other

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KR20110054773A (en) * 2009-11-18 2011-05-25 삼성전자주식회사 Semiconductor memory device for improving bit line disturbance
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KR20110024207A (en) * 2009-09-01 2011-03-09 주식회사 하이닉스반도체 Semiconductor memory device
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