KR20140071642A - Data Output Circuit - Google Patents

Data Output Circuit Download PDF

Info

Publication number
KR20140071642A
KR20140071642A KR1020120139446A KR20120139446A KR20140071642A KR 20140071642 A KR20140071642 A KR 20140071642A KR 1020120139446 A KR1020120139446 A KR 1020120139446A KR 20120139446 A KR20120139446 A KR 20120139446A KR 20140071642 A KR20140071642 A KR 20140071642A
Authority
KR
South Korea
Prior art keywords
signal
delay
clock
polling
rising
Prior art date
Application number
KR1020120139446A
Other languages
Korean (ko)
Other versions
KR102006239B1 (en
Inventor
차진엽
김재일
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120139446A priority Critical patent/KR102006239B1/en
Publication of KR20140071642A publication Critical patent/KR20140071642A/en
Application granted granted Critical
Publication of KR102006239B1 publication Critical patent/KR102006239B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

A data output circuit is disclosed.
The data output circuit according to an embodiment of the present invention includes a delay signal generation block that generates a rising delay signal and a falling delay signal reflecting the impedance calibration result in response to an impedance adjustment command, a reset signal, and a test signal, A first delay block for correcting the duty ratio of the rising clock according to the control and outputting a corrected rising clock, and a second delay circuit for outputting a corrected polling clock by correcting the duty ratio of the polling clock according to the control of the polling delay signal. Block.

Figure P1020120139446

Description

Data output circuit [0001]

The present invention relates to a data output circuit, and more particularly, to a data output circuit for generating a data output clock for improving a data window width.

Among the synchronous memory devices, DDR memory consecutively processes two bits of data for one clock period in synchronization with a rising edge and a falling edge of an externally input clock.

Meanwhile, such DDR SDRAM is synchronized with a data output clock, that is, a signal of a data strobe signal (DQS) in communication with a chip set, and mutually transmits and receives data.

Specifically, at the time of data reading, data is outputted to the outside according to the rising edge and the falling edge of DQS in the SDRAM. On the other hand, at the time of data writing, data synchronized with the DQS signal from the chip set is strobed )do.

As described above, DQS as a reference signal for data output plays an important role in high-speed operation of semiconductor memory devices and applications using semiconductor memory devices.

The slew rate, duty, etc. of the DQS are thus very important to determine the overall timing related specification of the semiconductor memory device.

However, when the skew difference occurs due to the difference between the rising clock and polling clock of the DQS and the PMOS or NMOS characteristic of the transistor itself, the duty ratio of the DQS may be distorted.

As is known, it is very important that the duty ratio of the clock is accurately controlled in the semiconductor memory device. If the duty ratio of the clock is not controlled, the margin of the data can not be ensured and the effective data window of the final output can be narrowed. If the window width of the data becomes smaller gradually as the operation speed increases, effective data determination may become difficult.

Embodiments of the present invention provide a data output clock that improves the data window width.

The data output circuit according to an embodiment of the present invention includes a delay signal generation block that generates a rising delay signal and a falling delay signal reflecting the impedance calibration result in response to an impedance adjustment command, a reset signal, and a test signal, A first delay block for correcting the duty ratio of the rising clock according to the control and outputting a corrected rising clock, and a second delay circuit for outputting a corrected polling clock by correcting the duty ratio of the polling clock according to the control of the polling delay signal. Block.

The data output circuit according to another embodiment of the present invention monitors the transistor skew difference due to the PVT variation using the impedance calibration result and adjusts the resultant ratio of the rising clock and the polling clock to the rising delay signal and the polling delay And a delay signal generation block used for generating a signal.

The data output circuit according to an exemplary embodiment of the present invention obtains a pull-up and pull-down calibration code through the impedance calibration result, monitors the transistor skew difference due to the PVT variation using the code value, You can adjust the delay of the polling data clock. By adjusting the delay of these clocks, the duty ratio of the data output clock can be improved. Thereby, the valid window of the data can be stably secured.

1 is a block diagram of a data output circuit according to an embodiment of the present invention;
2 is a block diagram of a delay signal generation block for generating a rising delay signal and a polling delay signal according to FIG.
3 is a more detailed block diagram of the skew judging unit according to Fig. 2, and Fig.
4 is a circuit diagram of a delay clock signal generator according to FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, embodiments of the present invention will be described more specifically with reference to the accompanying drawings.

1 is a configuration diagram of a phase change memory device 100 according to an embodiment of the present invention.

1, the data output circuit includes a first signal generation block 110, a first delay control block 132, a second delay control block 142, a delay block 135, a first driver 150 A second signal generation block 120, a second driver 160, a first tree rejection 170, and a second tree rejection 180.

The first signal generation block 110 receives the rising DLL clock RCLKDLL and the polling DLL clock FCLKDLL in response to the first output control signal ROUTEN to generate the rising clock RCLK.

The delay block unit 135 includes a first delay block 130 and a second delay block 140.

First, the first delay block 130 delays the rising clock RCLK by a predetermined delay under the control of the first delay control block 132.

On the other hand, the first delay control block 132 includes a first NOR gate NR1 and a first inverter IV1.

The first NOR gate NR1 NORs the delay block activation signal TMTAC and the rising delay signal RCLK_DLY.

The first inverter IV1 inverts the output signal of the first NOR gate NR1 and provides it to the first delay block 130.

Thus, the first delay block 130 delays the rising clock RCLK in accordance with the delay block enable signal TMTAC and the rising delay signal RCLK_DLY.

The delay block activation signal TMTAC mentioned here can be understood as an enable signal of a normal delay block.

The first driver 150 drives the output signal of the first delay block 130 to generate a rising data clock RCLK_DO.

The second signal generating block 120 receives the rising DLL clock RCLKDLL and the polling DLL clock FCLKDLL in response to the second output control signal FOUTEN and generates a polling clock FCLK.

The second delay block 140 delays the polling clock FCLK by a predetermined time under the control of the second delay control block 142.

The second delay control block 142 includes a second NOR gate NR2 and a second inverter IV2.

The second NOR gate NR2 combines the delay block activation signal TMTAC and the polling delay signal FCLK_DLY in a NOR operation.

The second inverter IV2 inverts the output signal of the second NOR gate NR2 and provides it to the second delay block 140.

Thus, the second delay block 140 can adjust the delay of the polling clock FCLK according to the delay block activation signal TMTAC and the polling delay signal FCLK_DLY.

As described above, the delay block activation signal TMTAC can be understood as an enable signal of a normal delay block.

The second driver 160 drives the output signal of the second delay block 140 to generate a polling data clock FCLK_DO.

The generated rising data clock RCLK_DO and the polling data clock FCLK_DO are supplied to the first and second tree rejections 170 and 180 after passing through the predetermined repeater RPT to generate the rising data RDO and the polling data FDO And is provided as a data output clock DQS.

Here, the first signal generation block 110, the second signal generation block 120, the first driver 150, the second driver 160, the first tree rejection 170, the second tree rejection 180, The operating principle and scheme are all the same as in the prior art.

Therefore, the prior art is a technique known to those skilled in the art, so a detailed description thereof will be omitted for brevity.

That is, the first signal generation block 110 generates a rising clock RCLK in response to a first output control signal ROUTEN, which is a control signal for a rising clock having information of CL (CAS Latency) and BL (Burst Length) . Similarly, the second signal generating block 120 generates a polling clock FCLK in response to a second output control signal FOUTEN, which is a polling clock control signal having information of CL (CAS Latency) and BL (Burst Length) .

Thus, in the first and second delay blocks 130 and 140, a delay control signal having delay information according to an exemplary embodiment of the present invention, namely, a rising delay signal RCLK_DLY and a falling delay signal FCLK_DLY, The delay of the rising clock (RCLK) and the polling clock (FCLK) can be controlled according to the level.

That is, according to an embodiment of the present invention, a rising delay signal RCLK_DLY and a polling delay signal FCLK_DLY are generated using the impedance calibration result. The duty ratio of the rising clock RCLK and the polling clock FCLK are respectively controlled according to a high level or a low level of the rising delay signal RCLK_DLY and the falling delay signal FCLK_DLY.

For example, according to the level of the rising delay signal RCLK_DLY, it is possible to control whether the PMOS or NMOS receiving the rising delay signal RCLK_DLY in the first delay block 130 is turned on. Thus, the duty cycle of the rising clock (RCLK) can be improved by adjusting the high period of the rising clock (RCLK). Here, the 6-bit calibration code is described as an example, but the present invention is not limited thereto.

Or whether the PMOS or NMOS receiving the rising delay signal FCLK_DLY in the second delay block 140 is turned on or off according to the level of the polling delay signal FCLK_DLY. Thus, the duty ratio of the polling clock FCLK can be improved while the high period of the polling clock FCLK is adjusted.

To this end, in the present invention, a delay signal generation block 500, which will be described later, is provided, and a rising delay signal RCLK_DLY and a falling delay signal FCLK_DLY reflecting the process characteristics of the PMOS and NMOS transistors in response to the impedance calibration adjustment result, . A detailed description thereof will be given later with reference to Fig.

Next, the first driver and the second drivers 150 and 160 will be described. Driving the rising clock and the polling clock with the duty ratio corrected drives the rising data clock RCLK_DO and the polling data clock FCLK_DO.

As described above, the generated rising data clock RCLK_DO and the polling data clock FCLK_DO are respectively supplied to the rising data RDO by the first and second tree rejects 170 and 180 after passing through the predetermined repeater RPT, And the polling data FDO as a data output clock DQS.

As described above, according to the embodiment of the present invention, the impedance calibration is performed and the rising delay signal RCLK_DLY reflecting the result of monitoring the characteristic difference of the transistor or the skew according to the process variation of the PMOS transistor and the NMOS transistor, The duty ratio of the rising clock RCLK and the polling clock FCLK can be further improved by generating the delay signal FCLK_DLY. As a result, the duty ratio can be improved and corrected, and it can be stable in securing the data valid window width of the data output clock DQS as the final output clock. Thus, a high efficiency circuit Can be implemented.

2 is a block diagram of a delay signal generation block 500 for generating a rising delay signal RCLK_DLY and a falling delay signal FCLK_DLY according to FIG.

Referring to FIG. 2, the delay signal generation block 500 includes an impedance calibration unit 200, a skew determination unit 300, and a delayed clock signal generation unit 400.

The impedance calibration unit 200 is a conventional impedance calibration circuit unit, and can be understood by those skilled in the art.

The impedance calibration unit 200 reflects the characteristics of the PMOS transistor and the NMOS transistor of the resistance varying according to the PVT (Process, Voltage, Temperature) condition, which is performed in the ZQ node as a node for calibration Pull up calibration codes (PCODE <5: 0>) and pull down calibration codes (NCODE <5: 0>). The resistance value of the on-die termination device is adjusted using the code generated as a result of the impedance calibration, and the termination resistance value of the DQ pad is adjusted in the case of the semiconductor memory device. These pull up calibration codes (PCODE <5: 0>) and pull down calibration codes (NCODE <5: 0>) are indicators of the process corner conditions of the PMOS and NMOS transistors. Thus, in the present invention, this code can be used to generate the rising delay signal RCLK_DLY and the falling delay signal FCLK_DLY for the data output clock. That is, the duty ratio of the rising clock RCLK and the polling clock FCLK can be adjusted by using a calibration code serving as an index indicating the characteristics of the process corner conditions.

The skew determining unit 300 receives the pull-up calibration codes PCODE <5: 0> and pull-down calibration codes NCODE <5: 0> and provides skew determination results of the PMOS transistor and the NMOS transistor in the current state.

Thus, the skew determining unit 300 determines whether the normal PMOS signal which is the first through sixth skew determination result signals according to the results of the pull-up calibration codes PCODE <5: 0> and the pull down calibration codes NCODE <5: 0> (P-TYP), a fast PMOS signal P-FAST, a slow PMOS signal P-SLOW, a normal NMOS signal N-TYP, a fast NMOS signal N-FAST, Lt; / RTI &gt;

The normal PMOS signal (P-TYP), the fast PMOS signal (P-FAST), and the slow PMOS signal (P-SLOW), which are the first to third skew determination result signals, indicate whether the PMOS transistor has a typical PMOS characteristic or a fast characteristic , And slow characteristics.

The normal NMOS signal (N-TYP), the fast NMOS signal (N-FAST), and the slow NMOS signal (N-SLOW) as the fourth to sixth skew determination result signals are typical NMOS characteristics, fast characteristics, Lt; / RTI &gt;

The delay clock signal generation section 400 generates a delay PMOS signal P-TYP in response to the impedance adjustment command signal ZQ CMD, a test mode enable signal TM and a reset signal RSTB, The delay NMOS signal N-FAST and the slow NMOS signal N-SLOW are set in accordance with the levels of the PMOS signal P-FAST, the slow PMOS signal P-SLOW, the normal NMOS signal N-TYP, A rising delay signal RCLK_DLY, and a polling delay signal FCLK_DLY for controlling the delay adjustment of the delay circuit. That is, the delayed clock signal generator 400 may determine whether to adjust the delay of the rising clock RCLK and the polling clock FCLK according to the levels of the first through sixth skew determination result signals.

This will be described in more detail with reference to FIG. 3 and FIG.

3 is a circuit diagram of the skew determining unit 300 according to FIG.

The skew determining unit 300 includes a subtracting unit 310 and a comparing unit 330.

The subtraction unit 310 includes a first subtraction block 314 and a second subtraction block 318. [

The first subtraction block 314 includes a first subtractor 312 and a second subtractor 313.

The first subtraction block 314 receives the pull-up calibration code PCODE <5: 0> and outputs two comparison control signals: the normal PMOS control signal P-TYP-EN and the slow PMOS control signal P- Lt; / RTI &gt; For convenience of explanation, the normal PMOS control signal P-TYP-EN and the slow PMOS control signal P-SLOW_EN are referred to as first and second comparison control signals.

The second subtraction block 318 includes a third subtractor 316 and a fourth subtractor 317.

The second subtraction block 318 receives the pull down calibration code NCODE <5: 0> and outputs two comparison control signals: the normal NMOS control signal N-TYP-EN and the slow NMOS control signal N-SLOW_EN ). For convenience of explanation, the normal NMOS control signal (N-TYP-EN) and the slow NMOS control signal (N-SLOW_EN) are referred to as third and fourth comparison control signals.

Next, the comparison unit 330 will be described. The comparison unit 330 includes a first comparison block 335 and a second comparison block 339.

The first comparison block 335 includes first through third comparators 331-333.

The second comparison block 339 includes fourth to sixth comparators 336-338.

The first comparison block 335 receives the normal PMOS control signal P-TYP-EN and the slow PMOS control signal P-SLOW_EN which are the first and second comparison control signals and outputs the normal PMOS signal P- A fast PMOS signal (P-FAST), and a slow PMOS signal (P-SLOW).

The first through third comparators 331-333 in the first comparison block 335 are configured as follows.

The first comparator 331 includes a first NOR gate NR1, a first inverter, and a second inverter IV1 and IV2.

The second comparator 332 includes a first NAND gate ND1 and a third inverter IV3.

The third comparator 333 includes a fourth inverter and a fifth inverter IV4 and IV5.

Each comparator 331-333 receives the normal PMOS control signal P-TYP-EN and the slow PMOS control signal P-SLOW_EN and provides the combined result as an output signal.

The second comparison block 339 receives the third and fourth comparison control signals, that is, the normal NMOS control signal N-TYP-EN and the slow NMOS control signal N-SLOW_EN, , A fast NMOS signal (N-FAST), and a slow NMOS signal (N-SLOW).

The fourth to sixth comparators 336-338 in the second comparison block 339 are configured as follows.

The fourth comparator 336 includes a second NOR gate NR2, a sixth inverter and a seventh inverter IV6 and IV7.

The fifth comparator 337 includes a second NAND gate ND2 and an eighth inverter IV8.

The sixth comparator 338 includes a ninth inverter and a tenth inverter IV9, IV10.

Each comparator 336-338 receives the normal NMOS control signal (N-TYP-EN) and the slow NMOS control signal (N-SLOW_EN) and provides the combined result as an output signal.

More specifically, the skew determining unit 300 will be described.

First, a pull-up calibration code PCODE <5: 0> and a pull-down calibration code NCODE <5: 0> generated through an impedance calibration unit (see 200 in FIG. 2) are input to an impedance calibration unit ) Of the PMOS transistor and the NMOS transistor.

It is necessary to determine whether the pull-up calibration codes PCODE <5: 0> and pull-down calibration codes NCODE <5: 0> generated in this way are PMOS and NMOS transistors of the normal condition, .

Therefore, the skew decision signal can be provided so that the skew can be determined based on the result obtained by subtracting the specific code value through the subtractors 312, 313, 316, and 317 provided in the subtraction unit 310. [

More specifically, the first and second subtractors 312 and 313 commonly receive the pull-up calibration codes PCODE < 5: 0 >, and subtract each specific code value.

For example, the first subtractor 312 provides the result of subtracting the specific code value 010101 from the pull-up calibration code PCODE <5: 0> as the normal PMOS control signal P-TYP-EN.

The second subtractor 313 provides the result of subtracting the specific code value 101010 from the pull-up calibration code PCODE <5: 0> as the slow PMOS control signal P-SLOW_EN.

It is needless to say that the specific code values 010101 and 101010 set herein may be variously changed according to the intention of the circuit designer because they are code values that can represent the range of process characteristics of the PMOS transistor through simulation .

For example, if the result obtained by subtracting the specific code value (010101, 101010) from the pull-up calibration code PCODE <5: 0> is higher than the predetermined target value and lower than the normal PMOS control signal P -TYP-EN) and a slow PMOS control signal (P-SLOW_EN).

From this result, it is possible to derive the three PMOS signals (P-TYP), the fast PMOS signal (P-FAST) and the slow PMOS signal (P-SLOW), which are three skew judgment result signals indicating the current state of the PMOS transistor .

That is, when the normal PMOS control signal P-TYP-EN is at the low level and the slow PMOS control signal P-SLOW_EN is at the high level, the output of the first comparator 331 is at the low level of the fast PMOS signal P -FAST).

At this time, the output of the second comparator 332 provides the low level normal PMOS signal (P-TYP) and the output of the third comparator 333 provides the high level of the slow PMOS signal (P-SLOW).

In other words, according to one embodiment of the present invention, the process conditions of the current PMOS transistor can be sensed according to the result of the pull-up calibration code (PCODE <5: 0>) through impedance calibration, It can be seen that it has a slow corner condition.

In a similar principle, the third and fourth subtractors 316 and 317 receive the pull down calibration codes NCODE < 5: 0 > in common and subtract each specific code value.

Thus, the third subtractor 316 provides the result of subtracting the specific code value 010101 from the pull-down calibration code NCODE <5: 0> as the normal NMOS control signal N-TYP-EN.

Then, the fourth subtractor 317 provides the result of subtracting the specific code value 101010 from the pull-down calibration code NCODE <5: 0> as the slow NMOS control signal N-SLOW_EN.

For example, if the result of subtracting the specific code values (010101, 101010) from the pull-down calibration code (NCODE <5: 0>) is a high level, N-TYP-EN) and a slow NMOS control signal (N-SLOW_EN), the three NMOS transistors N-TYP, N-TYP, It is possible to derive the fast PMOS signal (N-FAST) and the slow PMOS signal (N-SLOW).

That is, when the normal NMOS control signal N-TYP-EN is high level and the slow NMOS control signal N-SLOW_EN is low level, the output of the third comparator 336 is the low-level fast NMOS signal N -FAST).

At this time, the output of the fourth comparator 337 provides a low level normal NMOS signal (N-TYP), and the output of the fifth comparator 338 provides a high level slow NMOS signal (N-SLOW).

In other words, according to one embodiment of the present invention, the process condition of the current NMOS transistor can be sensed according to the result of the pull-down calibration code NCODE <5: 0> through impedance calibration, Is in the slow corner condition.

In this case, how the delay of the rising clock and the polling clock can be adjusted substantially will be described in detail with reference to the following drawings.

4 is a circuit diagram of the delayed clock signal generator 400 shown in FIG.

The delayed clock signal generator 400 includes a duty control signal generator 420, a rising clock delay unit 440, and a polling clock delay unit 460.

The duty control signal generating section 420 can generate the duty control signal DUTY-EN in response to the impedance adjustment command ZQ CMD, the reset signal RSTB and the test signal TM.

The duty control signal generating unit 420 includes a latch unit 422 having an SR latch structure and a first NAND gate ND1 and second and third inverters I2 and I3.

The latch unit 422 is configured to respond to the impedance adjustment command ZQ CMD and the reset signal RSTB.

Thus, the duty control signal generator 420 generates the duty control signal DUTY_EN activated in response to the level activated to the impedance adjustment command ZQ CMD or the reset signal RSTB when the test signal TM is activated to provide.

The rising clock delay unit 440 receives the slow PMOS signal P-SLOW, the fast NMOS signal N-FAST, the fast PMOS signal P-FAST, the fast NMOS signal N-FAST and the duty control signal DUTY- EN) to provide a rising delay signal RCLK_DLY.

The rising clock delay unit 440 includes a plurality of NAND gates ND11, ND12 and ND13 and a plurality of inverters I11, I12, I13 and I14 and a NOR gate NR1.

The rising clock delay unit 440 outputs the result of the AND operation of the slow PMOS signal P-SLOW and the fast NMOS signal N-FAST in response to the activated duty control signal DUTY-EN, -FAST) and a fast NMOS signal (N-FAST).

The polling clock delay unit 460 receives the fast PMOS signal P-FAST, the slow NMOS signal N-SLOW, the slow PMOS signal P-SLOW, the slow NMOS signal N-SLOW and the duty control signal DUTY- EN) to provide a polling delay signal FCLK_DLY.

The polling clock delay unit 460 includes a plurality of NAND gates ND22, ND23 and ND24 and a plurality of inverters I21, I22, I23 and I24 and a NOR gate NR2.

The polling clock delay unit 460 outputs the result of the AND operation of the fast PMOS signal P-FAST and the slow NMOS signal N-SLOW or the result of the AND operation of the slow PMOS signal P (N-SLOW) in response to the activated duty control signal DUTY- -SLOW) and the slow NMOS signal (N-SLOW), and provides the polling delay signal FCLK_DLY.

When the slow PMOS signal (P-SLOW) and the slow NMOS signal (N-SLOW) are all at a high level, the circuit of the polling clock delay unit (460) The signal FCLK_DLY will be activated.

As described above, according to the embodiment of the present invention, it is possible to detect the process corner condition of the PMOS transistor and the NMOS transistor through the impedance calibration, and to monitor the skew occurrence.

Referring again to FIG. 1, the rising clock RCLK of the first delay block 130 and the falling clock RCLK of the second delay block 140 and the polling clock RCLK of the second delay block 140 are controlled according to the activated rising delay signal RCLK_DLY and the falling delay signal FCLK_DLY, (FCLK), thereby adjusting the rising edge timing of the rising data clock RCLK_DO and the falling data clock FCLK_DO. Finally, the data output clock DQS is defined by the rising edge interval of the rising data clock RCLK_DO and the falling data clock FCLK_DO, whereby the window width of the DQS can be stably secured.

As described above, according to one embodiment of the present invention, it is possible to generate a more stable data output clock by monitoring the skew difference of the transistor according to the PVT variation and adjusting the delay of the rising clock and the polling clock.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

110: first signal generation block
120: second signal generation block
130: first delay block
132: first delay block control section
140: second delay block
142: second delay block control section
150: First driver
160: second driver
170: 1st tree rejection
180: second tree reject

Claims (12)

A delay signal generation block for generating a rising delay signal and a polling delay signal reflecting the impedance calibration result in response to the impedance adjustment command, the reset signal, and the test signal;
A first delay block for correcting the duty ratio of the rising clock according to the control of the rising delay signal and outputting the corrected rising clock; And
And a second delay block for outputting a corrected polling clock by correcting the duty ratio of the polling clock according to the control of the polling delay signal. The method according to claim 1,
The delay signal generation block includes:
An impedance calibration unit for generating a pull-up calibration code and a pull-down calibration code reflecting the characteristics of the PMOS transistor and the NMOS transistor through impedance calibration;
A skew judging unit receiving the pull-up calibration code and the pull-down calibration code and providing a skew judgment result signal of the PMOS transistor and the NMOS transistor; And
And a delayed clock signal generator for providing the rising delay signal and the polling delay signal in response to the skew determination result signal. 3. The method of claim 2,
Wherein the skew determining unit
A subtracter for subtracting the pull-up calibration code and the pull-down calibration code from a preset code value to generate a comparison control signal; And
And a comparison unit for receiving and providing the comparison control signal to provide the skew determination result signal. The method of claim 3,
Wherein,
A first subtraction block responsive to the pullup calibration code for providing first and second comparison control signals that are basis for comparing the PMOS transistor process characteristics; And
And a second subtraction block responsive to the pulldown calibration code for providing third and fourth comparison control signals that are basis for comparing the NMOS transistor process characteristics. 5. The method of claim 4,
Wherein,
A first comparison block which receives and combines the first and second comparison control signals to provide first to third skew determination result signals in which process characteristics of the PMOS transistor are determined; And
And a second comparison block for receiving and combining the third and fourth comparison control signals to provide fourth to sixth skew determination result signals in which process characteristics of the NMOS transistors are determined. 3. The method of claim 2,
The delayed clock signal generator includes:
A duty control signal generator for generating a duty control signal in response to the impedance adjustment command, the reset signal, and the test signal;
A rising clock delay unit controlled by the duty control signal to provide the rising delay signal according to a level of the skew determination result signal; And
And a polling clock delay unit controlled by the duty control signal to provide the polling delay signal according to a level of the skew determination result signal. And a delay signal generation block used for monitoring the transistor skew difference due to the PVT variation using the result of performing the impedance calibration and for using the result to generate the rising delay signal and the polling delay signal so as to adjust the duty ratio of the rising clock and the polling clock Data output circuit. 8. The method of claim 7,
The delay signal generation block includes:
An impedance calibration unit for generating a pull-up calibration code and a pull-down calibration code reflecting the characteristics of the PMOS transistor and the NMOS transistor through the impedance calibration;
A skew judging unit receiving the pull-up calibration code and the pull-down calibration code and providing a skew judgment result signal of the PMOS transistor and the NMOS transistor; And
And a delayed clock signal generator for providing the rising delay signal and the polling delay signal in response to the skew determination result signal. 9. The method of claim 8,
Wherein the skew determining unit
A subtracter for subtracting the pull-up calibration code and the pull-down calibration code from a preset code value to generate a comparison control signal; And
And a comparison unit for receiving and providing the comparison control signal to provide the skew determination result signal. 10. The method of claim 9,
Wherein,
A first subtraction block responsive to the pullup calibration code for providing first and second comparison control signals that are basis for comparing the PMOS transistor process characteristics; And
And a second subtraction block responsive to the pulldown calibration code for providing third and fourth comparison control signals that are basis for comparing the NMOS transistor process characteristics. 5. The method of claim 4,
Wherein,
A first comparison block which receives and combines the first and second comparison control signals to provide first to third skew determination result signals in which process characteristics of the PMOS transistor are determined; And
And a second comparison block for receiving and combining the third and fourth comparison control signals to provide fourth to sixth skew determination result signals in which process characteristics of the NMOS transistors are determined. 9. The method of claim 8,
The delayed clock signal generator includes:
A duty control signal generator for generating a duty control signal in response to an impedance adjustment command, a reset signal, and a test signal;
A rising clock delay unit for activating the duty control signal to provide the rising delay signal according to a level of the skew determination result signal; And
And a polling clock delay unit for activating the duty control signal to provide the polling delay signal according to a level of the skew determination result signal.
KR1020120139446A 2012-12-04 2012-12-04 Data Output Circuit KR102006239B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120139446A KR102006239B1 (en) 2012-12-04 2012-12-04 Data Output Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120139446A KR102006239B1 (en) 2012-12-04 2012-12-04 Data Output Circuit

Publications (2)

Publication Number Publication Date
KR20140071642A true KR20140071642A (en) 2014-06-12
KR102006239B1 KR102006239B1 (en) 2019-08-01

Family

ID=51125902

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120139446A KR102006239B1 (en) 2012-12-04 2012-12-04 Data Output Circuit

Country Status (1)

Country Link
KR (1) KR102006239B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170024910A (en) * 2015-08-26 2017-03-08 에스케이하이닉스 주식회사 Semiconductor Apparatus and System
KR20190120952A (en) * 2018-04-17 2019-10-25 에스케이하이닉스 주식회사 Semiconductor device and operating method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090146700A1 (en) * 2007-12-07 2009-06-11 Hynix Semiconductor, Inc. Duty ratio correction circuit
KR20100073620A (en) * 2008-12-23 2010-07-01 주식회사 하이닉스반도체 Synchronization circuit of semiconductor memory apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090146700A1 (en) * 2007-12-07 2009-06-11 Hynix Semiconductor, Inc. Duty ratio correction circuit
KR20090059676A (en) * 2007-12-07 2009-06-11 주식회사 하이닉스반도체 Duty ratio corrector circuit
KR20100073620A (en) * 2008-12-23 2010-07-01 주식회사 하이닉스반도체 Synchronization circuit of semiconductor memory apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170024910A (en) * 2015-08-26 2017-03-08 에스케이하이닉스 주식회사 Semiconductor Apparatus and System
KR20190120952A (en) * 2018-04-17 2019-10-25 에스케이하이닉스 주식회사 Semiconductor device and operating method thereof

Also Published As

Publication number Publication date
KR102006239B1 (en) 2019-08-01

Similar Documents

Publication Publication Date Title
US7663946B2 (en) Semiconductor memory device having on-die-termination device and operation method thereof
JP4868359B2 (en) On-die termination control device
US9025410B2 (en) Semiconductor memory devices and semiconductor system having parameters, and methods of testing the same
KR101040242B1 (en) Data Strobe Signal Generating Device and Semiconductor Memory Apparatus using the same
CN111279416B (en) Internal write trimming for memory devices
US20140098621A1 (en) Semiconductor memory device and driving method thereof
JP2009093778A (en) Semiconductor storage device
JP2007134029A (en) Clock circuit for semiconductor memory
CN111418019B (en) System and method for improving input signal quality in a memory device
US8334706B2 (en) Impedance calibration mode control circuit
KR20140026179A (en) Domain crossing circuit of semiconductor apparatus
US8923077B2 (en) Semiconductor device operates on external and internal power supply voltages and data processing system including the same
US8823433B2 (en) Data output circuit
US7773709B2 (en) Semiconductor memory device and method for operating the same
KR102006239B1 (en) Data Output Circuit
US8503251B2 (en) Semiconductor memory device having pipe latch circuit for storing output data during read operation and method for operating the same
CN111418017A (en) System and method for saving power in signal quality operation of memory devices
US8436657B2 (en) Semiconductor device having output driver
US20190259440A1 (en) Systems and methods for generating stagger delays in memory devices
US20160162300A1 (en) Semiconductor device and method for driving the same
US8929173B1 (en) Data strobe control device
US8248863B2 (en) Data buffer control circuit and semiconductor memory apparatus including the same
KR100980402B1 (en) Sense Amplifier Overdrive Signal Generating Circuit and Semiconductor Memory Apparatus Including the Same
KR100930413B1 (en) Light driver control circuit, semiconductor integrated circuit comprising same and method for generating light driver control signal
KR100851990B1 (en) Command Buffer for Semiconductor Memory Apparatus

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right