KR20140064017A - Charge pump circuit and internal voltage generation circuit including the same - Google Patents

Charge pump circuit and internal voltage generation circuit including the same

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Publication number
KR20140064017A
KR20140064017A KR1020120130865A KR20120130865A KR20140064017A KR 20140064017 A KR20140064017 A KR 20140064017A KR 1020120130865 A KR1020120130865 A KR 1020120130865A KR 20120130865 A KR20120130865 A KR 20120130865A KR 20140064017 A KR20140064017 A KR 20140064017A
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KR
South Korea
Prior art keywords
node
control signal
capacitor
response
voltage
Prior art date
Application number
KR1020120130865A
Other languages
Korean (ko)
Inventor
신진욱
김지환
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120130865A priority Critical patent/KR20140064017A/en
Publication of KR20140064017A publication Critical patent/KR20140064017A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

According to the present technology, a charge pump circuit comprises: a first switch group connected according to a first pumping control signal; a second switch group connected according to a second pumping control signal; a first current pass to charge power to a first capacitor and a second capacitor when the first switch group is connected and the second switch group is disconnected; and a second current pass to output the internal power by connecting the first and the second capacitor in parallel and adding power to the power charged in the first and the second capacitor when the second switch group is connected and the first switch group is disconnected.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a charge pump circuit and an internal voltage generating circuit including the charge pump circuit.

The present invention relates to a semiconductor device, and more particularly, to a charge pump circuit of a semiconductor memory device and an internal voltage generating circuit including the same.

The semiconductor memory device generates internal power supplies having various levels of voltage with an external power supply, and the internal power supply is used for internal operation of the semiconductor memory device according to its purpose.

There are two main ways of generating internal power by external power. One of them is a method of generating an internal power by down-converting an external power supply to a low potential and the other is a method of pumping an external power supply using a charge pump so as to be higher than the potential of the external power supply, And generates an internal power supply lower than the ground potential.

Generally, the internal power generated by down-converting is to reduce power consumption, and the internal power generated by charge pump is for special purposes

Among the internal power generated by the charge pump, the most commonly used are the high voltage VPP and the back bias voltage VBB.

The high voltage VPP is generated so as to have a potential higher than the power supply voltage VCC, which is an external voltage, so that there is no loss of cell data in the gate (or the word line) of the cell transistor in order to access the cell.

The back bias voltage VBB is used to make a potential lower than the ground voltage VSS, which is an external voltage, in the bulk of the cell transistor in order to prevent loss of data stored in the cell.

The charge pump according to the related art increases the voltage level of the internal power source by integrating the power source voltage VCC. Therefore, the charge pump according to the related art has a problem of outputting internal power beyond the voltage necessary for internal operation of the semiconductor memory device and increasing power consumption of the semiconductor memory device.

A problem to be solved by the present invention is to provide a charge pump circuit that generates a stable internal voltage by using a power supply voltage.

Another object of the present invention is to provide an internal voltage generating circuit for generating an internal voltage required for a semiconductor device using a power supply voltage.

A charge pump circuit according to an embodiment of the present invention includes a first switch group connected in accordance with a first pumping control signal; A second switch group connected in accordance with a second pumping control signal; A first current path for charging the first capacitor and the second capacitor connected in series when the first switch group is conductive and the second switch group is disconnected; And when the second switch group is turned on and the first switch group is cut off, the first and second capacitors are connected in parallel and the power supply voltage is added to the charged voltage of the first and second capacitors to output the voltage as an internal voltage And a second current path.

According to another aspect of the present invention, there is provided an internal voltage generation circuit comprising: a sensing unit for generating a sensing signal by comparing a reference voltage and an internal voltage; An oscillator for generating a periodic signal in response to the sensing signal; And a pump unit for serially connecting a first capacitor and a second capacitor in a charging interval in response to the oscillator signal or outputting the pumped internal voltage by connecting the first and second capacitors in parallel in an output interval.

According to the present invention, the voltage level of the boosted internal voltage is low to reduce the current consumption of the semiconductor device, and the power efficiency of the semiconductor device can be improved by generating an internal voltage having various voltage levels.

1 is a block diagram of an internal voltage generating circuit including a charge pump circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of the oscillator of FIG. 1;
Fig. 3 is a circuit diagram of the pump control unit of Fig. 1,
4 is a specific circuit diagram of a charge pump circuit according to an embodiment of the present invention,
5A to 5B are circuit diagrams showing the operation of the charge pump circuit of FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

1 is a block diagram of an internal voltage generating circuit 1 including a charge pump circuit 32 according to an embodiment of the present invention.

The internal voltage generating circuit 1 includes a sensing unit 10, an oscillator 20, and a pump unit 30. The pump section 30 includes a pump control section 31 and a charge pump circuit 32.

The sensing unit 10 compares the reference voltage VREF with the internal voltage VINT and outputs a sensing signal EN. When the voltage level of the internal voltage (VINT) is lower than the reference voltage (VREF), the sensing section (10) enables the sensing signal (EN) to logic-high output. On the other hand, when the voltage level of the internal voltage VINT is higher than the reference voltage VREF, the sensing unit 10 disables the sensing signal EN to be outputted in a logic low manner.

The oscillator 20 outputs the period signal OSC in response to the sense signal EN. The oscillator 20 operates when an enabled sensing signal EN is input, and outputs a period signal OSC.

The pump control section 31 generates a plurality of pumping control signals P1 and P2 for controlling the charge pump circuit 32 in accordance with the period signal OSC.

The charge pump circuit 32 charges the power supply voltage VCC in accordance with the pumping control signals P1 and P2 to output the internal voltage VINT.

2 is a circuit diagram of the oscillator 20 of Fig.

The oscillator 20 includes a NAND gate ND and first to fifth inverters IV1 to IV5. The oscillator 20 includes a NAND gate ND for logically combining the sense signal EN and the output signal of the sixth inverter IV6, a first inverter IV1 for inverting the output signal of the NAND gate ND, A second inverter IV2 for inverting the output signal of the inverter IV1, a third inverter IV3 for inverting the output signal of the second inverter IV2 and outputting the inverted signal as the period signal OSC, A fifth inverter IV5 for inverting the output signal of the fourth inverter IV4 and a sixth inverter IV6 for inverting the output signal of the fifth inverter IV5. .

The oscillator 20 operates the enabled sense signal EN to output the period signal OSC.

The sensing unit 10 and the oscillator 20 according to the embodiment of the present invention may have a known configuration.

3 is a circuit diagram of the pump control unit 31 of FIG.

The pump control unit 31 includes a first pump control signal generation unit 311 and a second pump control signal generation unit 312.

The first pump control signal generator 311 includes a seventh inverter IV7 and an eighth inverter IV8. The seventh inverter IV7 inverts and outputs the period signal OSC and the eighth inverter IV8 inverts the output signal of the seventh inverter IV7 to output the first pump control signal P1.

The second pump control signal generator 312 includes a ninth inverter IV9. The ninth inverter IV9 inverts the period signal OSC and outputs a second pump control signal P2.

The first pump control signal P1 output from the pump control unit 31 is in phase with the period signal OSC and the second pump control signal P2 is in phase with the first pump control signal P1 and the periodic signal OSC, (OSC) and the cycle are the same and the phase is opposite. At this time, it is preferable that the first pump control signal P1 and the second pump control signal P2 output from the pump control unit 31 are designed so that the enable period does not overlap within one cycle.

4 is a specific circuit diagram of the charge pump circuit 32 according to the embodiment of the present invention.

The charge pump circuit 32 includes a plurality of switches SW1 to SW7 and a plurality of capacitors C1 and C2. The plurality of switches SW1 to SW7 are connected to the first switch group SW1 to SW3 responsive to the first pump control signal P1 and the second switch group SW4 to SW7 responsive to the second pump control signal P2, .

The plurality of switches SW1 to SW7 are turned on or off by the first and second pump control signals P1 and P2 which are opposite in phase to each other.

The first switch SW1 turns on or off the input node IN and the first node N1 in response to the first pump control signal P1. The second switch SW2 turns on or off the second node N2 and the third node N3 in response to the first pump control signal P1. The third switch SW3 turns on or off the fourth node N4 and the ground voltage VSS in response to the first pump control signal P1. The fourth switch SW4 turns on or off the input node IN and the second node N2 in response to the second pump control signal P2. The fifth switch SW5 connects or disconnects the input node IN and the fourth node N4. The sixth switch SW6 conducts or interrupts the first node N1 and the output node OUT. The seventh switch SW7 conducts or interrupts the third node N3 and the output node OUT. The first capacitor C1 is connected between the first node N1 and the second node N2 and the second capacitor C2 is connected between the third node N3 and the fourth node N4.

The charge pump circuit 32 receives the power supply voltage VCC to the input node IN and outputs the internal voltage VINT to the output node OUT. Here, the first capacitor C1 and the second capacitor C2 may be capacitors having the same capacitance.

5A to 5B are circuit diagrams showing the operation of the charge pump circuit 32 in accordance with the first and second pump control signals P1 and P2.

The operation of the charge pump circuit 32 according to the embodiment of the present invention will now be described with reference to FIGS. 4 to 5B.

5A, when the first pump control signal P1 is enabled to logic high and the second pump control signal P2 is disabled to logic low, the first to third switches SW1 to SW3 are turned on, The fourth to seventh switches SW4 to SW7 are cut off.

A state in which the first pump control signal P1 input to the charge pump circuit 32 is enabled and the second pump control signal P2 is disabled is referred to as a charge section.

When the first switch group SW1 to SW3 are turned on and the second switch group SW4 to SW7 are turned off, the charge pump circuit 32 turns on the first capacitor C1 and the second capacitor C2 ).

That is, when the first switch groups SW1 to SW3 are turned on and the second switch groups SW4 to SW7 are shut off, the input node IN and the first node N1, the second node N2, The third node N3, the fourth node N4, and the ground voltage VSS are connected to each other to form the first current path PT1

At this time, the first capacitor C1 and the second capacitor C2 are connected in series. The first capacitor C1 and the second capacitor C2 connected in series are connected and charged between the power supply voltage VCC and the ground voltage VSS. The voltage difference between the first node N1 and the fourth node N4 becomes the power supply voltage VCC level.

As described above, the first capacitor C1 and the second capacitor C2 are the same capacitor. Therefore, each of the first and second capacitors C1 and C2 is charged to the voltage level of 1/2 * the supply voltage VCC.

5B, when the first pump control signal P1 is logically disabled and the second pump control signal P2 is enabled to logic high, the first to third switches SW1 to SW3 are shut off, The fourth to seventh switches SW4 to SW7 are turned on.

A state in which the first pump control signal P1 input to the charge pump circuit 32 is disabled and the second pump control signal P2 is enabled is referred to as an output period.

When the first switch groups SW1 to SW3 are shut off and the second switch group SW4 to SW7 are turned on, the charge pump circuit 32 outputs the internal voltage VINT at the output node OUT.

When the first switch group SW1 to SW3 is shut off and the second switch group SW4 to SW7 are turned on, the input node IN and the second node N2, the input node IN and the fourth node N4, The first node N1 and the output node OUT and the third node N3 and the output node OUT are connected to form a second current path PT2

The first capacitor C1 and the second capacitor C2 are connected in parallel between the power supply voltage VCC and the output node OUT. The voltages already charged in the first capacitor C1 and the second capacitor C2 and the voltage level of the power source voltage VCC are added and transferred to the output node OUT. At this time, the voltage levels of the charged capacitors C1 and C2 are 1/2 power supply voltage (VCC). Therefore, the voltage level of the output node OUT becomes the power supply voltage VCC + 1/2 * the power supply voltage VCC. That is, the voltage level of the internal voltage VINT output from the output node OUT becomes 1.5 * the power supply voltage VCC.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

1: internal voltage generating circuit 10:
20: oscillator 30: pump section
31: pump control unit 32: charge pump circuit

Claims (20)

A first switch group connected in accordance with a first pumping control signal;
A second switch group connected in accordance with a second pumping control signal;
A first current path for charging the first capacitor and the second capacitor connected in series when the first switch group is conductive and the second switch group is disconnected; And
Wherein when the second switch group is turned on and the first switch group is cut off, the first and second capacitors are connected in parallel and the power supply voltage is added to the charged voltage of the first and second capacitors, A charge pump circuit comprising two current paths.
The method according to claim 1,
Wherein the first capacitor and the second capacitor are capacitors having the same capacitance.
3. The method of claim 2,
Wherein the first pumping control signal and the second pumping control signal have the same period and are opposite in phase.
The method of claim 3,
Wherein the first current path receives the power supply voltage to an input node,
A first switch for selectively connecting the input node and the first node in response to the first pumping control signal;
A second switch for selectively connecting a second node and a third node in response to the first pumping control signal;
A third switch for selectively connecting between a fourth node and a ground voltage in response to the first pumping control signal;
The first capacitor coupled between the first node and the second node; And
And the second capacitor coupled between the third node and the fourth node.
5. The method of claim 4,
The first current path
Wherein when the first pump control signal is enabled, both ends of the first capacitor and the second capacitor connected in series are charged to the power supply voltage level.
6. The method of claim 5,
Wherein the second current path is supplied with the power supply voltage to the input node,
A fourth switch for selectively connecting the input node and the second node in response to the second pumping control signal;
A fifth switch for selectively connecting the input node and the fourth node in response to the second pumping control signal;
A sixth switch for selectively connecting the first node and the output node in response to the second pumping control signal;
A seventh switch for selectively connecting the third node and the output node in response to the second pumping control signal; And
The first capacitor coupled between the first node and the second node; And
And the second capacitor coupled between the third node and the fourth node.
The method according to claim 6,
The second current path
Wherein when the second pump control signal is enabled, the first capacitor and the second capacitor are connected in parallel, and the power supply voltage is supplied to one end of the first capacitor and the internal voltage is output to the output node.
8. The method of claim 7,
The internal voltage
Wherein the power supply voltage is 1.5 times the power supply voltage.
A sensing unit for comparing a reference voltage with an internal voltage to generate a sensing signal;
An oscillator for generating a periodic signal in response to the sensing signal; And
And a pump unit for serially connecting a first capacitor and a second capacitor in a charging interval in response to the oscillator signal or for connecting the first and second capacitors in parallel in an output interval to output the pumped internal voltage, Circuit.
10. The method of claim 9,
Wherein the first capacitor and the second capacitor are capacitors having the same capacitance.
11. The method of claim 10,
The sensing unit
And enables the sense signal if the voltage level of the internal voltage is lower than the reference voltage, and disables the sense signal if the voltage level of the internal voltage is higher than the reference voltage.
12. The method of claim 11,
The oscillator
And generates a periodic signal by operating when the sense signal is enabled.
13. The method of claim 12,
The pump unit
A pump controller for generating first and second pump control signals in response to the periodic signal; And
Wherein the first and second capacitors are serially connected in the charge section in response to the first and second pump control signals, and the first and second capacitors are connected in parallel in the output section, Voltage generating circuit including a charge pump circuit for outputting an output voltage.
14. The method of claim 13,
The pump control unit
And outputs the first pump control signal having the same cycle and phase as the periodic signal and the second pump control signal having the same cycle and the opposite phase to the first pump control signal.
15. The method of claim 14,
The charge pump circuit
A first switch group which is turned on or off in response to the first pump control signal;
A second switch group which is turned on or off in response to the second pump control signal;
A first current path for charging the first capacitor and the second capacitor connected in series with the power supply voltage when the first switch group is conductive and the second switch group is blocked; And
Wherein when the second switch group is turned on and the first switch group is cut off, the first and second capacitors are connected in parallel and the power supply voltage is added to the charged voltage of the first and second capacitors, Internal voltage generating circuit comprising two current paths.
16. The method of claim 15,
Wherein the first current path is supplied with the power supply voltage to an input node,
A first switch for selectively connecting the input node and the first node in response to the first pumping control signal;
A second switch for selectively connecting a second node and a third node in response to the first pumping control signal;
A third switch for selectively connecting between a fourth node and a ground voltage in response to the first pumping control signal;
The first capacitor coupled between the first node and the second node; And
And the second capacitor connected between the third node and the fourth node.
17. The method of claim 16,
The first current path
Wherein when the first pump control signal is enabled, both ends of the first capacitor and the second capacitor connected in series are charged to the power supply voltage level.
18. The method of claim 17,
Wherein the second current path is supplied with the power supply voltage to the input node,
A fourth switch for selectively connecting the input node and the second node in response to the second pumping control signal;
A fifth switch for selectively connecting the input node and the fourth node in response to the second pumping control signal;
A sixth switch for selectively connecting the first node and the output node in response to the second pumping control signal;
A seventh switch for selectively connecting the third node and the output node in response to the second pumping control signal; And
The first capacitor coupled between the first node and the second node; And
And the second capacitor connected between the third node and the fourth node.
19. The method of claim 18,
The second current path
Wherein when the second pump control signal is enabled, the first capacitor and the second capacitor charged are connected in parallel and the power supply voltage is supplied to one end to output the internal voltage to the output node. .
20. The method of claim 19,
The internal voltage
Wherein the power supply voltage is 1.5 times the power supply voltage.
KR1020120130865A 2012-11-19 2012-11-19 Charge pump circuit and internal voltage generation circuit including the same KR20140064017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120130865A KR20140064017A (en) 2012-11-19 2012-11-19 Charge pump circuit and internal voltage generation circuit including the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120130865A KR20140064017A (en) 2012-11-19 2012-11-19 Charge pump circuit and internal voltage generation circuit including the same

Publications (1)

Publication Number Publication Date
KR20140064017A true KR20140064017A (en) 2014-05-28

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Family Applications (1)

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Country Status (1)

Country Link
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