KR20140049448A - Dram storing randomized data and operating method of the same - Google Patents

Dram storing randomized data and operating method of the same Download PDF

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Publication number
KR20140049448A
KR20140049448A KR1020130028272A KR20130028272A KR20140049448A KR 20140049448 A KR20140049448 A KR 20140049448A KR 1020130028272 A KR1020130028272 A KR 1020130028272A KR 20130028272 A KR20130028272 A KR 20130028272A KR 20140049448 A KR20140049448 A KR 20140049448A
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South Korea
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data
input
output
randomization
sub
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KR1020130028272A
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Korean (ko)
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배승준
손영수
곽진석
이정배
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삼성전자주식회사
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Priority to US14/053,660 priority Critical patent/US20140108716A1/en
Publication of KR20140049448A publication Critical patent/KR20140049448A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

A DRAM according to an embodiment of the present invention includes a memory cell array, a data input / output circuit, and a data randomizer for randomizing data to be stored in the memory cell array. The data randomization apparatus encodes input data received from a data input / output circuit according to a randomization code to generate write data and output the write data to a memory cell array, and decodes read data received from the memory cell array according to a randomization code. To generate output data and output the data to a data input / output circuit.

Description

DDR STORING RANDOMIZED DATA AND OPERATING METHOD OF THE SAME

The present invention relates to a DRAM and a method of operating the same.

Dynamic random access memory (DRAM) stores data in a memory cell array consisting of a plurality of memory cells. Each memory cell includes a transistor acting as a switch and a capacitor connected in series with the transistor. The same plate voltage VP is applied to one end of each capacitor.

When the memory cell is active or data is written to the memory cell, noise may be generated in the plate voltage due to a parasitic capacitor. The noise increases as the degree to which the ratio of 0 and 1 of the data stored in the memory cells deviates from 50% is large. The noise reduces the sensing margin of the memory cell.

The technical problem to be achieved by the present invention is to provide a DRAM and a method of operating the same to reduce the reduction of the sensing margin due to noise.

A dynamic random access memory (DRAM) according to an embodiment of the present invention includes a memory cell array, a data input / output circuit, and a data randomizer for randomizing data to be stored in the memory cell array. The data randomization apparatus encodes input data received from the data input / output circuit according to a randomization code to generate write data and output the write data to the memory cell array, and randomizes read data received from the memory cell array. And a decoder for generating output data by decoding according to a speech code and outputting the output data to the data input / output circuit.

The data randomization apparatus may further include a random number generator for generating and outputting the randomization code based on an address corresponding to the input data or the read data.

The address is a column address or a row address, and the DRAM relates to the column address and the row address according to a column address strobe (/ CAS) signal and a row address strobe (/ RAS) signal. Information can be received at different times.

The encoder performs a logical operation on the bits corresponding to each of the randomization code and the input data and outputs them to the memory cell array, and the decoder performs a logical operation on the bits corresponding to each of the randomization code and the read data. The data may be output to the input / output circuit.

The data input / output circuit may receive data having a burst length of 2 or more from each of the plurality of input / output terminals of the DRAM, and generate and output the input data by parallelizing the received data for each burst.

The randomization code may include a plurality of sub-randomization codes corresponding to each of the plurality of input / output terminals of the DRAM, and the plurality of sub-randomization codes may be identical to or different from each other.

The plurality of sub-randomization codes include a first sub-randomization code and a second sub-randomization code having an inversion relationship with the first sub-randomization code. The first sub-randomization code may correspond to an odd-numbered input / output terminal among the plurality of input / output terminals, and the second sub-randomization code may correspond to an even-numbered input / output terminal among the plurality of input / output terminals.

The random number generator may include at least one lookup table that stores a plurality of pseudo random binary sequences (PRBSs), and a plurality of bits included in the address, according to at least one lookup table. At least one selection circuit for selecting and outputting at least one pseudo random binary sequence from a corresponding lookup table may be included.

Each of the plurality of sub-randomization codes may be a plurality of bits included in the address.

Each of the plurality of sub-randomization codes may be generated by performing a logical operation on a plurality of bits included in the address with a pseudo random binary sequence.

The random number generator may include at least one linear feedback shift register (LFSR) using a plurality of bits included in the address as a reset signal.

According to another exemplary embodiment of the present invention, a method of operating a DRAM including a memory cell array and a data input / output circuit may include: encoding input data received from the data input / output circuit according to a randomization code and outputting the random data to the memory cell array; And decoding the read data received from the memory cell array according to the randomization code and outputting the read data to the data input / output circuit.

The operation method of the DRAM may further include generating the randomization code based on an address corresponding to the input data or the read data.

The address is a column address or a row address, and the DRAM relates to the column address and the row address according to a column address strobe (/ CAS) signal and a row address strobe (/ RAS) signal. Information can be received at different times.

The randomization code may include a plurality of sub-randomization codes corresponding to each of the plurality of input / output terminals of the DRAM, and the plurality of sub-randomization codes may be identical to or different from each other.

According to an exemplary embodiment of the present invention, since the data stored in the memory cells may be randomized to adjust the ratio of 0 and 1 to approximately 50%, the sensing margin due to noise of the plate voltage may be reduced.

1 is a block diagram of a DRAM in accordance with embodiments of the present invention.
FIG. 2 is a block diagram illustrating the data randomization apparatus of FIG. 1 in more detail.
3 is a circuit diagram illustrating the encoder of FIG. 2 in more detail.
4 is a diagram illustrating an operating principle of the encoder and the decoder of FIG. 2.
FIG. 5 is a circuit diagram illustrating an embodiment of the random number generator of FIG. 2.
FIG. 6 is a diagram illustrating a part of the random number generator of FIG. 5 in more detail.
FIG. 7 is a circuit diagram illustrating an embodiment of the selection circuit of FIG. 5.
FIG. 8 is a table illustrating write data randomized according to the random number generator of FIGS. 5 to 7.
FIG. 9 is a diagram schematically illustrating a memory cell array and a peripheral portion thereof in which randomized data of FIG. 8 is stored.
FIG. 10 is a circuit diagram illustrating another embodiment of the random number generator of FIG. 2.
FIG. 11 is a table illustrating write data randomized according to the random number generator of FIG. 10.
12 is a block diagram illustrating still another embodiment of the random number generator of FIG. 2.
FIG. 13 is a block diagram illustrating in detail the random number generator of FIG. 12.
14 is a circuit diagram of the linear feedback feedback register of FIG.
FIG. 15 is a circuit diagram illustrating still another embodiment of the random number generator of FIG. 2.
FIG. 16 is a circuit diagram illustrating still another embodiment of the random number generator of FIG. 2.
17 is a flowchart illustrating a method of operating a DRAM according to example embodiments.
FIG. 18 illustrates an embodiment of a computer system including the DRAM illustrated in FIG. 1.
FIG. 19 illustrates another embodiment of a computer system including the DRAM illustrated in FIG. 1.
20 illustrates another embodiment of a computer system including the DRAM illustrated in FIG. 1.
FIG. 21 illustrates another embodiment of a computer system including the DRAM shown in FIG. 1.

Specific structural and functional descriptions of the embodiments of the present invention disclosed herein are for illustrative purposes only and are not to be construed as limitations of the scope of the present invention. And should not be construed as limited to the embodiments set forth herein or in the application.

The embodiments according to the present invention are susceptible to various changes and may take various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It is to be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "comprises ", or" having ", or the like, specify that there is a stated feature, number, step, operation, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 is a block diagram of a DRAM in accordance with embodiments of the present invention.

The DRAM 100 includes a memory cell array 110, a row decoder 120, a sense amplifier and a write driver 130, a column decoder 140, a control circuit 145, a data randomizer 150, a command decoder ( 160, an MRS / EMRS circuit 170, an address buffer 180, and a data input / output circuit 190.

A schematic operation of the DRAM 100 is as follows.

The memory cell array 110 may include a plurality of word lines (or rows, not shown), a plurality of bit lines (or columns, not shown), and a plurality of memory cells (not shown) for storing data. Include.

The row decoder 120 decodes the row address RA output from the address buffer 180 and selects one row (or word line) among the plurality of rows (or word lines) according to the decoding result. .

The sense amplifier and the write driver 130 may write data randomized by the data randomizer 150 to the memory cell array 110 based on the address signal ADD. The sense amplifier and write driver 130 may sense and amplify the randomized data from the memory cell array 110.

The column decoder 140 decodes the column address CA output from the address buffer 180 and selects a plurality of columns according to the decoding result.

The control circuit 145 controls the operation of the DRAM 100 in response to a command output from the command decoder 160.

The data randomization apparatus 150 encodes, ie, randomizes the data Din input through the data input / output circuit 190 and outputs the data Din to the memory cell array 110 through the sense amplifier and the write driver 130. Meanwhile, the data randomization apparatus 150 decodes the data read from the memory cell array 110 to generate output data Dout.

The command decoder 160 may include a command signal applied from the outside, for example, a chip select (/ CS) signal, a row address strobe (/ RAS) signal, and a column address strobe (/ CAS). A signal or the like is received, and the signals are decoded to internally generate a decoded command signal.

The MRS / EMRS circuit 170 sets an internal mode register (not shown) in response to an MRS / EMRS command and an address signal ADD for specifying an operation mode of the DRAM 100.

The address buffer 180 temporarily receives and receives an address signal ADD for designating a memory cell into which data is to be written or read. The address signal ADD includes information about the column address CA and the row address RA. The address buffer 180 receives information regarding the column address CA and the row address RA at different times according to the / CAS signal and the / RAS signal.

The data input / output circuit 190 receives input data Din through the plurality of input / output terminals DQ of the DRAM, and transmits output data Dout.

The plurality of input / output terminals DQ may receive data having two or more burst lengths from the outside. The data input / output circuit 190 may parallelize and output the input data Din received by the plurality of input / output terminals DQ for each input / output terminal DQ.

For example, the data input / output circuit 190 may include a parallelization buffer (not shown). The parallelization buffer (not shown) may store each burst sequentially received by each input / output terminal DQ, output the same in parallel. In this case, the number of the plurality of input / output terminals DQ is m (m is an integer of 2 or more), the burst length is n (n is an integer of 2 or more), and the number of output bits of the data input / output circuit 190 is x (x Is an integer of 2 or more), x = m * n.

However, the scope of the present invention is not limited thereto, and according to an embodiment, the data randomization apparatus 150 may perform data parallelization. According to another exemplary embodiment, the data input / output circuit 190 and the data randomization device 150 may perform parallelization of data.

The data input / output circuit 190 may serialize the output data Dout according to the number of the plurality of input / output terminals DQ. For example, the data input / output circuit 190 may sequentially select x-bit output data Dout and output the m-output terminals DQ.

Although not shown in FIG. 1, the DRAM 100 may include a clock circuit (not shown) for generating a clock signal, a power circuit (not shown) for receiving or supplying a power voltage applied from the outside to generate or distribute an internal voltage. It may be further provided.

FIG. 2 is a block diagram illustrating the data randomization apparatus of FIG. 1 in more detail.

1 and 2, the data randomization apparatus 150 may include a random number generator 151, an encoder 153, and a decoder 155.

The random number generator 151 generates and outputs a randomization code RN based on the address CAp corresponding to the input data Din or the read data RD_Data.

The address CAp may be a column address CA or a row address RA, or may be a plurality of bits included in the column address CA or the row address RA. Hereinafter, it is assumed that the address CAp is y (y is an integer of 2 or more) bits included in the column address CA, and the randomization code RN is x (x is an integer of 2 or more) bits. In addition, the address CAp will be referred to as a sub address.

The encoder 153 receives x bits of input data Din from the data input / output circuit 190. The data input / output circuit 190 receives input data Din having n (n is an integer of 2 or more) burst lengths from m (m is an integer of 2 or more) input / output terminals, and receives the received input data for each input / output terminal. In parallel, x-bit input data Din may be generated and output to the encoder 153. In this case, x = m * n, and hereinafter, it is assumed that x = m * n. However, the scope of the present invention is not limited thereto, and the value of x may vary when parallelization of each burst of data is not performed in the data input / output circuit 190.

The encoder 153 encodes the input data Din according to the randomization code RN to generate the write data WR_Data, and outputs the write data WR_Data to the memory cell array 110 through the sense amplifier / write driver 130.

The decoder 155 decodes the x-bit read data RD_Data received from the memory cell array 110 according to the randomization code RN to generate output data Dout, and output the output data Dout to the data input / output circuit 190. .

The randomization code RN, the input data Din, the output data Dout, the write data WR_Data, and the read data RD_Data are all x-bit data. Accordingly, the encoder 153 may logically operate on bits corresponding to each of the randomization code RN and the input data Din. The decoder 155 may logically operate on bits corresponding to each of the randomization code RN and the read data RD_Data. The logical operation may be an exclusive OR (XOR) operation, but the scope of the present invention is not limited thereto. For example, the logical operation may be an exclusive NOR (XNOR) operation.

In the following description, the randomization code RN means that all bits included in the randomization code RN are included, that is, RN [1] [1] to RN [m] [n]. When called RN [m], it means containing RN [m] [1]-RN [m] [n]. The same is true for other data.

3 is a circuit diagram illustrating the encoder of FIG. 2 in more detail.

1 and 3, the encoder 153 may include x sub-encoders 1531-1 to 1531 -x.

The input data Din is x bit data and may include data bits of Din [1] [1] to Din [m] [n]. At this time, the Din [m] [n] bits are data of the nth burst received from the mth input / output terminal DQ of the DRAM 100.

The encoder 153 performs an XOR operation on bits corresponding to each of the randomization code RN and the input data Din, for example, Din [m] [n] and RN [m] [n] bits, thereby writing the write data WR_DATA. Corresponding bits WR_DATA [m] [n].

The decoder 155 may also be implemented in the same manner, and thus the description of the decoder 155 will be omitted.

4 is a diagram illustrating an operating principle of the encoder and the decoder of FIG. 2.

As one of the worst cases in which noise occurs in the plate voltage VP, it is assumed that each bit of the input data Din is all zero. In this case, when the input data Din is written to the memory cell array as it is, the sensing margin of the memory cell is reduced by the noise of the plate voltage. Therefore, the input data Din must be randomized to reduce the noise.

2 and 4, the encoder 153 generates the write data WR_DATA by performing an XOR operation on the input data Din and the randomization code RN. Each bit of the write data WR_DATA has a value of 0 if the input data Din and a corresponding bit of the randomization code RN are the same, and 1 if they are different. Since the input data Din and the randomization code RN are unrelated data, the ratio of 0 and 1 of the write data WR_DATA has a value close to 50%. Accordingly, noise of the plate voltage can be reduced by writing the write data WR_DATA to the memory cell array.

It is assumed that the write data WR_DATA is read, that is, the read data RD_Data is the same as the write data WR_DATA. In this case, since the sub address CAp corresponding to the input data Din and the read data WR_DATA are the same, the randomization code RN has the same value at the time of writing and reading. The decoder 155 performs an XOR operation on the read data RD_Data and the randomization code RN to generate and output the same output data Dout as the input data Din.

In FIG. 4, an embodiment of performing encoding and decoding using the same XOR operation has been described. However, according to an embodiment, encoding and decoding may be performed using the same XNOR operation. You can also perform other operations.

In addition, in FIG. 4, the encoding and decoding in the case where each bit of the input data Din is all zero has been described. However, this is only an example for convenience of description, and the encoding and decoding may be performed on any input data Din. Can be done.

FIG. 5 is a circuit diagram illustrating an embodiment of the random number generator of FIG. 2, and FIG. 6 is a diagram illustrating a portion of the random number generator of FIG. 5 in more detail.

1, 2, and 5, the randomization code RN generated by the random number generator 151 includes a plurality of sub-randomization codes corresponding to each of the plurality of input / output terminals DQ of the DRAM 100. RN [1] ~ RN [m]). Each sub-randomization code RN [1] -RN [m] may include n bits. For example, RN [m] may include bits RN [m] [1] through RN [m] [n].

The plurality of sub-randomization codes RN [1] to RN [m] may be generated in various ways. Hereinafter, embodiments of the random number generator 151 for generating sub-randomization codes RN [1] to RN [m] will be described with reference to FIGS. 5 to 16.

Referring back to FIGS. 1, 5, and 6, the random number generator 151a includes a plurality of lookup tables 210-1 to 210-m and a plurality of selection circuits 220-1 to 220-m. It may include. The number of lookup tables 210-1 to 210-m and the selection circuits 220-1 to 220-m may be equal to the number m of input / output terminals DQ.

Each of the lookup tables 210-1 to 210-m may store a plurality of pseudo random binary sequences (PRBSs). The number of PRBSs stored in each lookup table 210-1 to 210-m may be 2 y . For example, the first lookup table 210-1 may store a plurality of PRBSs (PRBS-1 to PRBS-2 y ). Each PRBS may be an n bit code. In this case, y is the number of bits included in the column address CA, that is, the number of bits used by the random number generator 151 among the column addresses CA, and n is the burst length.

Each of the selection circuits 220-1 to 220-m receives a plurality of PRBSs from the corresponding lookup tables 210-1 to 210-m, and selects one of the plurality of PRBSs received according to the sub-address CAp. And n-bit sub-randomization codes RN [1] to RN [m].

For example, the first selection circuit 220-1 receives a plurality of PRBSs (PRBS-1 to PRBS-2 y ), and receives the plurality of PRBSs (PRBS-1 to PRBS−) according to the y-bit subaddress CAp. 2 y ) may be selected and output as an n-bit sub-randomization code RN [1].

Each of the selection circuits 220-1 to 220-m may be implemented by using a plurality of multiplexers (MUXs) or by using a plurality of switches.

The plurality of PRBSs stored in each of the lookup tables 210-1 to 210-m may be the same or different from each other. Accordingly, the plurality of sub-randomization codes RN [1] to RN [m] may be the same or different from each other.

FIG. 7 is a circuit diagram illustrating an embodiment of the selection circuit of FIG. 5.

5 to 7, the selection circuit 220-1a generating the sub randomization code RN [1] may include a plurality of switches.

Hereinafter, m = n = 8, y = 2, all bits of the input data Din are 0, and the plurality of PRBSs stored in the lookup tables 210-1 to 210-m are {P0 to P62, 1}. Assume that it contains bits.

Since y = 2, the first lookup table 210-1 may include four PRBSs (PRBS-1 to PRBS-4). The first PRBS (PRBS-1) includes PRBS bits of {P0, P1, ..., P7}, and the second PRBS (PRBS-2) contains PRBS bits of {P16, P17, ..., P23} The third PRBS (PRBS-3) includes the PRBS bits of {P32, P33, ..., P39}, the fourth PRBS (PRBS-4) is {P48, P49, ..., P55 } Is assumed to contain the PRBS bit.

The selection circuit 220-1a receives four PRBSs PRBS-1 to PRBS-4 from the lookup table 210-1. The four PRBSs (PRBS-1 to PRBS-4) received by the selection circuit 220-1a from the lookup table 210-1 are {P0, P1, ..., P7, P16, P17, ..., P23, P32, P33, ..., P39, P48, P49, ..., P55}.

The selection circuit 220-1a receives the sub address CAp, and the sub address CAp includes the fourth bit CA4 and the third bit CA3 of the column address CA.

According to the sub address CAp, the selection circuit 220-1a selects the PRBS bits belonging to one of the four PRBSs PRBS-1 to PRBS-4 from RN [1] [1] to RN [m] [. n].

For example, when {CA4, CA3} = {0, 0}, the selection circuit 220-1a outputs P0 to RN [1] [1]. When {CA4, CA3} = {0, 1}, the selection circuit 220-1a outputs P16 to RN [1] [1]. When {CA4, CA3} = {1, 0}, the selection circuit 220-1a outputs P32 to RN [1] [1]. When {CA4, CA3} = {1, 1}, the selection circuit 220-1a outputs P48 to RN [1] [1].

The remaining selection circuits 220-2 to 220-m may also be implemented in the same manner to generate and output RN [1] [1] to RN [m] [n] using different PRBSs.

FIG. 8 is a table illustrating write data randomized according to the random number generator of FIGS. 5 to 7.

1, 5 to 8, each table shows a randomization code (RN) according to each value of CAp. The plurality of input / output terminals DQ includes eight input / output terminals, that is, the first input / output terminals DQ0 to the eighth input / output terminals DQ7, and the data received at each input / output terminal DQ0 to DQ7 includes eight bursts, That is, it is assumed that the first burst BL0 to the eighth burst BL7 are included.

Assuming that all bits of the input data Din are zero, the write data WR_DATA is equal to the randomization code RN.

For example, when {CA4, CA3} = {0, 0}, RN [1] [1] and WR_DATA [1] [1] corresponding to the first input / output terminal DQ0 and the first burst BL0 are P0. . RN [1] [8] and WR_DATA [1] [8] corresponding to the first input / output terminal DQ0 and the eighth burst BL7 are P7. RN [8] [1] and WR_DATA [8] [1] corresponding to the eighth input / output terminal DQ7 and the first burst BL0 are P56. RN [8] [8] and WR_DATA [8] [8] corresponding to the eighth input / output terminal DQ7 and the eighth burst BL7 are one.

Each row represents a PRBS pattern (PTN). The PRBS patterns PTN [1] corresponding to DQ0 are {P0 to P7, P16 to P23, P32 to P39, and P48 to P55}. Each PRBS pattern PTN is determined according to the PRBS of the corresponding lookup tables 210-1 to 210-m.

FIG. 9 is a diagram schematically illustrating a memory cell array and a peripheral portion thereof in which randomized data of FIG. 8 is stored.

1, 8, and 9, the DRAM 100a includes a memory cell including a plurality of memory blocks 110-1, 110-2,..., Corresponding to the input / output terminals DQ0-DQ7. The array 110 may include a plurality of row decoders 120-1, 120-2, ..., and a plurality of sense amplifiers and write drivers 130-1, 130-2, ....

In the present embodiment, the memory cell array 110 is divided into a plurality of memory blocks 110-1, 110-2,..., And each memory block 110-1, 110-2,. Corresponding to the input / output terminal DQ, but the scope of the present invention is not limited thereto.

A case of writing data in the memory block 110-1 corresponding to DQ0 will be described.

The row decoder 120-1 may select one word line in the memory block 110-1. The column decoder (not shown) may select the plurality of first columns 1101 having {CA4, CA3} = {0, 0}. The sense amplifier and write driver 130-1 burst the PRBS bits P0 to P7 when DQ0 and {CA4, CA3} = {0, 0} to each column in the plurality of first columns 1101. You can fill in as you like.

The column decoder (not shown) may select the plurality of first columns 1103 having {CA4, CA3} = {0, 1}. The sense amplifier and write driver 130-1 burst the PRBS bits P16 to P23 when DQ0 and {CA4, CA3} = {0, 1} to each column in the plurality of first columns 1103. You can fill in as you like.

As the above process is repeated, 32-bit PRBS patterns PTN in each memory block 110-1, 110-2,... Are identical in the row direction and may appear repeatedly in the column direction.

In order to reduce noise of the plate voltage, it is important to randomize the values of the memory cells that are turned on when one word line is activated. By randomizing data using the column address CA, data of each column in one row may be randomized.

The longer the PRBS pattern PTN, the more effectively the data can be randomized. The length of the PRBS pattern PTN may be increased by increasing the number of bits of the sub address CAp.

FIG. 10 is a circuit diagram illustrating another embodiment of the random number generator of FIG. 2.

Referring to FIG. 10, the random number generator 151b includes a lookup table 310, a selection circuit 320, and an inversion circuit 330.

The lookup table 310 stores a plurality of pseudo random binary sequences PRBS.

The selection circuit 320 may select n of the plurality of PRBSs according to the sub-address CAp and output the n-bit first sub-randomization code RN [1].

The inversion circuit 330 may invert each bit of the first sub-randomization code RN [1] to generate and output the second sub-randomization code RN [2].

The first sub-randomization code RN [1] corresponds to an odd-numbered input / output terminal among the plurality of input / output terminals DQ, and the second sub-randomization code RN [2] of the plurality of input / output terminals DQ. It may correspond to an even input / output terminal. For example, odd sub-randomization codes RN [1], RN [3], RN [5], ... may be set equal to each other. The even-numbered sub-randomization codes RN [2], RN [4], RN [6], ... may be set equal to each other.

FIG. 11 is a table illustrating write data randomized according to the random number generator of FIG. 10. The B mark means the bit is inverted. For example, P0B indicates that the P0 bit is inverted.

10 and 11, data written to each word line in each memory block includes one of two PRBS patterns at '0000 ...', that is, 'P0, P1, P2, ...' (PTN '). [1]) or 'P0B, P1B, P2B, ...' (PTN '[2]). Therefore, it is possible to reduce the noise of the plate voltage by randomizing the data of each column in one row.

The PRBS patterns PTN '[1] and PTN' [2] of each of the odd and even memory blocks are the same. However, the noise of the resulting plate voltage is relatively small. Accordingly, when the structure of FIG. 10 is used, noise may be effectively reduced by using a structure simpler than that of FIG. 5.

12 is a block diagram illustrating still another embodiment of the random number generator of FIG. 2.

Referring to FIG. 12, the random number generator 151c may include a linear feedback shift register (LFSR) random number generator 410 and a parallel processor 420.

The LFSR random number generator 410 includes at least one linear feedback shift register (LFSR). The LFSR random number generator 410 receives the clock signal CLK and the y-bit sub-address CAp to generate and output a z-bit pseudo random number Q. z may be a value of y multiplied by the number of input / output terminals, that is, z = m * y.

The parallel processor 420 converts the z-bit pseudorandom number Q into an x-bit randomization code RN.

FIG. 13 is a block diagram illustrating in detail the random number generator of FIG. 12.

Referring to FIG. 13, the LFSR random number generator 410 includes m LFSRs 411-1 to 411-m. The parallel processor 420 includes m sub-parallel processors 421-1 to 421-m. Each LFSR 411-1 to 411-m and each sub-parallel processing unit 421-1 to 421-m are used to generate each of the plurality of sub-randomization codes RN [1] to RN [m]. .

The first LFSR 411-1 receives the clock signal CLK and the y address sub address CAp, and sets the sub address CAp to a reset signal, that is, an initial bit value (also referred to as seed). To generate the first pseudo random number Q [1].

The first sub-parallel processor 421-1 generates and outputs an n-bit first sub-randomization code RN [1] by parallelizing the first pseudo-random number Q [1] of y bits.

The operations of the other LFSRs 411-2 to 411-m and the sub-parallel processing units 421-2 to 421-m are different from those of the first LFSR 411-1 and the first sub-parallel processing unit 421-1. The same description is omitted.

14 is a circuit diagram of the linear feedback feedback register of FIG.

Referring to FIG. 14, the first LFSR 411-1 may include y D flip-flops 411-1, 4111-2,..., 4111-y, and an operation circuit 4113. The first LFSR 411-1 generates a y-bit pseudo random number Q [1] every clock using the y-bit sub-address CAp as a seed. The construction and operation of the LFSR are well known to those skilled in the art, and thus a detailed description thereof will be omitted.

Each LFSR 411-1 to 411-m may have a different structure. For example, the order of extracting the pseudo random number Q [1] from each of the D flip-flops 4111-1, 4111-2, ..., 4111-y is different, or the function or feedback structure of the operation circuit 4113 is different. can be different. Thus, each pseudorandom number (Q [1], Q [2], ..., Q [m]) and each subrandomization code (RN [1], RN [2], ..., RN [m]) The value of may be set differently.

FIG. 15 is a circuit diagram illustrating still another embodiment of the random number generator of FIG. 2.

2 and 15, the random number generator 151d receives an n-bit sub address CAp and logically operates each bit of the sub address CAp with the PRBS bit to generate a randomization code RN. Can be generated. Each bit of the sub address CAp is referred to as CA [1] to CA [n], and each PRBS bit is referred to as P1 to Px.

Each sub-randomization code RN [1] -RN [m] is each bit CA [1] -CA [n] of the corresponding sub-address and a corresponding PRBS bit (e.g., RN [1], P1). It is set to the value that logically computes ~ Pn).

PRBS bits (P1 to Pn, Pn + 1 to P2n, ...) corresponding to each sub-randomization code (RN [1] to RN [m]) may be set identically to simplify the circuit structure. Alternatively, the data may be set differently to make the data more random.

FIG. 16 is a circuit diagram illustrating still another embodiment of the random number generator of FIG. 2.

2 and 16, the random number generator 151e receives an n-bit sub address CAp, and assigns each bit CA [1] to CA [n] of the sub address CAp to each sub. It can be output as randomization codes RN [1] to RN [m].

17 is a flowchart illustrating a method of operating a DRAM according to example embodiments.

1 and 17, in a write operation, the data randomization apparatus 150 encodes input data received from the data input / output circuit 190 according to a randomization code and outputs the encoded data to the memory cell array 110 ( S501).

In the read operation, the data randomization apparatus 150 decodes read data received from the memory cell array 110 according to a randomization code and outputs the decoded data to the data input / output circuit 190 (S503).

FIG. 18 illustrates an embodiment of a computer system including the DRAM illustrated in FIG. 1.

Referring to FIG. 18, a computer system 600 including the DRAM 100 shown in FIG. 1 may be a cellular phone, a smart phone, a personal digital assistant, or a wireless communication device. Can be implemented.

Computer system 600 includes a DRAM 100 and a memory controller 620 that can control the operation of DRAM 100. The memory controller 620 may control a data access operation of the DRAM 100, for example, a write operation or a read operation, under the control of the host 610.

Data of the DRAM 100 may be displayed through the display 630 under the control of the host 610 and the memory controller 620. The wireless transceiver 640 may receive or receive a wireless signal via the antenna ANT. For example, the wireless transceiver 640 may change the wireless signal received via the antenna ANT to a signal that can be processed at the host 610. [ Thus, host 610 may process the signal output from wireless transceiver 640 and transmit the processed signal to memory controller 620 or display 630. The memory controller 620 may store a signal processed by the host 610 in the DRAM 100.

In addition, the wireless transceiver 640 may convert the signal output from the host 610 into a wireless signal and output the modified wireless signal to an external device through the antenna ANT. The input device 650 is a device capable of inputting a control signal for controlling the operation of the host 610 or data to be processed by the host 610 and includes a touch pad and a computer mouse May be implemented with the same pointing device, keypad, or keyboard.

The host 610 is connected to the display 630 so that data output from the memory controller 620, data output from the wireless transceiver 640, or data output from the input device 650 can be displayed through the display 630. [ Can be controlled.

According to an embodiment, the memory controller 620 that can control the operation of the DRAM 100 may be implemented as part of the host 610, and may be implemented as a chip separate from the host 610.

FIG. 19 illustrates another embodiment of a computer system including the DRAM illustrated in FIG. 1.

Referring to FIG. 19, a computer system 700 including the DRAM 100 illustrated in FIG. 1 may be a personal computer, a network server, a tablet PC, or a net-book. ), an e-reader, a personal digital assistant, a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The computer system 700 includes a host 710, a DRAM 100, and a memory controller 720, a display 730, and an input device 740 that can control data processing operations of the DRAM 100.

The host 710 may display data stored in the DRAM 100 through the display 730 according to the data input through the input device 740. For example, the input device 740 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. The host 710 may control the overall operation of the computer system 700 and may control the operation of the memory controller 720.

According to an exemplary embodiment, the memory controller 720 capable of controlling the operation of the DRAM 100 may be implemented as part of the host 710 and may be implemented as a chip separate from the host 710.

20 illustrates another embodiment of a computer system including the DRAM illustrated in FIG. 1.

Referring to FIG. 20, the computer system 800 including the DRAM 100 illustrated in FIG. 1 may be implemented as an image processing device, such as a digital camera or a mobile phone or a smartphone to which a digital camera is attached. Can be.

Computer system 800 includes a host 810, a memory controller 820 that can control data processing operations, such as write or read operations, of the DRAM 100 and the DRAM 100. In addition, the computer system 800 further includes an image sensor 830 and a display 840.

The image sensor 830 of the computer system 800 converts the optical image into digital signals and the converted digital signals are transmitted to the host 810 or the memory controller 820. Under the control of the host 810, the converted digital signals may be displayed through the display 840 or stored in the DRAM 100 through the memory controller 820.

In addition, the data stored in the DRAM 100 is displayed through the display 840 under the control of the host 810 or the memory controller 820.

According to an embodiment, the memory controller 820 that may control the operation of the DRAM 100 may be implemented as part of the host 810, or may be implemented as a separate chip from the host 810.

FIG. 21 illustrates another embodiment of a computer system including the DRAM shown in FIG. 1.

Referring to FIG. 21, a computer system 900 including the DRAM 100 illustrated in FIG. 1 may be implemented with a host computer 910 and a memory card or a smart card. have. Computer system 900 includes a host computer 910 and a memory card 930.

Host computer 910 includes a host 940 and a host interface 920. The memory card 930 includes a DRAM 100, a memory controller 950, and a card interface 960. The memory controller 950 may control the exchange of data between the DRAM 100 and the card interface 960.

According to an embodiment, the card interface 960 may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but is not limited thereto.

When the memory card 930 is mounted in the host computer 910, the card interface 960 may interface data exchange between the host 940 and the memory controller 950 according to the protocol of the host 940.

According to an embodiment, the card interface 960 may support a universal serial bus (USB) protocol and an inter-chip (IC) -USB protocol. Here, the card interface may mean hardware capable of supporting a protocol used by the host computer 910, software mounted on the hardware, or a signal transmission scheme.

When computer system 900 is connected with host interface 920 of host computer 910, such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, The host interface 920 may perform data communication with the DRAM 100 through the card interface 960 and the memory controller 950 under the control of the host 940.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: DRAM 110: memory cell array
120: low decoder 130: sense amplifier and write driver
140: column decoder 145: control circuit
150: data randomization device 151: random number generator
153: encoder 155: decoder
160: Command decoder 170: MRS / EMRS circuit
180: address buffer 190: data input / output circuit
DQ: I / O Terminal Din: Input Data
Dout: output data WR_Data: write data
RD_Data: Read Data RN: Randomization Code
RA: row address CA: column address
CAp: sub address

Claims (10)

A memory cell array;
Data input / output circuits; And
A data randomization device for randomizing data to be stored in the memory cell array,
The data randomization device
An encoder for encoding the input data received from the data input / output circuit according to a randomization code to generate write data and output the write data to the memory cell array; And
And a decoder configured to decode read data received from the memory cell array according to the randomization code to generate output data and output the output data to the data input / output circuit. The apparatus of claim 1, wherein the data randomization device is
And a random number generator for generating and outputting the randomization code using at least a portion of an address corresponding to the input data or the read data. The method of claim 2, wherein the address is
Column address or row address,
The DRAM
And receiving the column address and the row address at different times according to a column address strobe signal and a row address strobe signal. The method of claim 1, wherein the encoder
Logical operation of bits corresponding to each of the randomization code and the input data is output to the memory cell array,
The decoder
And a logical operation corresponding to each bit of the randomization code and the read data to the data input / output circuit. The method of claim 2, wherein the randomization code is
A plurality of sub-randomization codes corresponding to each of the plurality of input / output terminals of the DRAM,
The plurality of sub-randomization codes
DRAMs that are the same or different from each other. The method of claim 5, wherein the plurality of sub-randomization code
A first sub randomization code; And
A second sub-randomization code having an inversion relationship with the first sub-randomization code,
The first sub randomization code is
Corresponds to an odd-numbered input-output terminal of the plurality of input-output terminals,
The second sub randomization code is
DRAM corresponding to an even input / output terminal of the plurality of input / output terminals. The method of claim 5, wherein the random number generator
At least one lookup table for storing a plurality of pseudo random binary sequences; And
And at least one selection circuit for selecting and outputting at least one pseudo random binary sequence from a corresponding lookup table of the at least one lookup table according to a plurality of bits included in the address. The method of claim 5, wherein each of the plurality of sub-randomization code
DRAM generated by logically operating a plurality of bits included in the address with a pseudo random binary sequence. The method of claim 2, wherein the random number generator
And at least one linear feedback shift register using a plurality of bits included in the address as a reset signal. A method of operating a DRAM including a memory cell array and a data input / output circuit,
Encoding the input data received from the data input / output circuit according to a randomization code and outputting the encoded data to the memory cell array; And
Decoding the read data received from the memory cell array according to the randomization code and outputting the read data to the data input / output circuit.
KR1020130028272A 2012-10-16 2013-03-15 Dram storing randomized data and operating method of the same KR20140049448A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107403645A (en) * 2016-05-12 2017-11-28 三星电子株式会社 Nonvolatile memory device and its reading and copy back method
WO2019050343A1 (en) * 2017-09-08 2019-03-14 국민대학교산학협력단 Method and apparatus for generating random number on basis of block cipher to which white-box cryptography is applied

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107403645A (en) * 2016-05-12 2017-11-28 三星电子株式会社 Nonvolatile memory device and its reading and copy back method
US11362685B2 (en) 2016-05-12 2022-06-14 Samsung Electronics Co., Ltd. Nonvolatile memory device and read and copy-back methods thereof
CN107403645B (en) * 2016-05-12 2023-03-28 三星电子株式会社 Nonvolatile memory device and read and copy back method thereof
WO2019050343A1 (en) * 2017-09-08 2019-03-14 국민대학교산학협력단 Method and apparatus for generating random number on basis of block cipher to which white-box cryptography is applied
KR20190028066A (en) * 2017-09-08 2019-03-18 국민대학교산학협력단 A method of generating random number based on block cipher with whitebox encryption and apparatus thereof

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