KR20140030568A - Voltage trimming circuit of semiconductor apparatus - Google Patents

Voltage trimming circuit of semiconductor apparatus Download PDF

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KR20140030568A
KR20140030568A KR1020120096894A KR20120096894A KR20140030568A KR 20140030568 A KR20140030568 A KR 20140030568A KR 1020120096894 A KR1020120096894 A KR 1020120096894A KR 20120096894 A KR20120096894 A KR 20120096894A KR 20140030568 A KR20140030568 A KR 20140030568A
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voltage
output
signal
unit
response
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KR1020120096894A
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Korean (ko)
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이경연
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에스케이하이닉스 주식회사
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators

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  • Microelectronics & Electronic Packaging (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

The voltage trimming circuit of the semiconductor device according to the present invention compares the oscillation signal passing the enable signal to the oscillator and the external clock, and variably divides the first voltage output from the voltage generator in response to the comparison result. And a voltage level selector for outputting a second voltage.

Figure P1020120096894

Description

Voltage Trimming Circuit Of Semiconductor Apparatus

The present invention relates to a semiconductor integrated circuit, and more particularly, to a voltage trimming circuit of a semiconductor device.

The semiconductor device is composed of many internal circuits, and each internal circuit may have a different required level of voltage for driving. Accordingly, a voltage trimming circuit that adjusts the voltage level is required to apply various voltage levels required by the internal circuits of the semiconductor device or to generate an accurate voltage level.

However, the general voltage trimming circuit outputs the same voltage level regardless of the process, voltage, and temperature variation (hereinafter, referred to as "PVT variation") of the semiconductor device.

For example, in semiconductor devices, unlike transistors, PVT fluctuations occur due to process variations in transistor size or addition of impurities.

If the characteristics of current consumption and signal propagation rate (i.e., delay) when the PVT fluctuations do not occur in the semiconductor device are general, when the PVT fluctuations occur in the semiconductor device, the signal propagation speed may be faster ("faster PVT fluctuation") than the design intention. ") Slows down signal propagation (" slow PVT fluctuation ").

On the other hand, when "fast PVT fluctuations" occur, the current consumption is higher than when no PVT fluctuations occur. In the case of a "slow PVT fluctuation", current consumption is lower than if no PVT fluctuation occurred.

Therefore, the general voltage trimming circuit outputs the same voltage level regardless of the PVT fluctuation of the semiconductor device, so it is not possible to improve the signal propagation speed during "slow PVT fluctuation" or unnecessary current consumption during "fast PVT fluctuation". This occurred.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and provides a voltage trimming circuit of a semiconductor device capable of changing a voltage level in accordance with a PVT variation.

The voltage trimming circuit of the semiconductor device according to an exemplary embodiment of the present invention compares an oscillation signal passing an enable signal to an oscillator and an external clock, and variably divides the first voltage output from the voltage generator in response to the comparison result. And a voltage level selector for outputting a second voltage.

According to another exemplary embodiment of the present disclosure, a voltage trimming circuit of a semiconductor device may include: a counting unit configured to receive a first external clock and output a plurality of external clocks including the first external clock in response to an enable signal; A controller configured to receive the enable signal and output a control signal having a different activation timing according to a PVT variation of a semiconductor device; A skew code output unit configured to receive the plurality of external clocks and output a plurality of skew codes in response to the control signal; And a trimming circuit unit configured to variably divide the first voltage output from the voltage generator and output a second voltage in response to the plurality of skew codes.

The voltage trimming circuit of the semiconductor device according to the present invention can change the voltage level according to the PVT variation, thereby improving the signal propagation speed and current consumption of the semiconductor device.

1 is a voltage trimming circuit diagram of a semiconductor device according to an embodiment of the present invention;
2 is a circuit diagram of the controller of FIG. 1;
3 is a circuit diagram of the skew code output unit of FIG. 1;
4 is a circuit diagram of a trimming circuit part of FIG. 1;
5 is a timing diagram of a voltage trimming circuit of a semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

In general, a ring oscillator used in a semiconductor device includes an inverter chain. Inverters used in semiconductor devices are generally implemented with transistors.

Therefore, by comparing the period of the signal passing through the ring oscillator used in the semiconductor device with the period of the external clock, it is possible to determine whether the semiconductor device has a change in PVT.

1 is a voltage trimming circuit diagram of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, a voltage trimming circuit of a semiconductor device according to an embodiment of the present invention includes a voltage generator 500 and a voltage level selector 600.

The voltage level selector 600 includes a trimming circuit 400 and a skew code generator 700. The skew code generation unit 700 includes a counting unit 100, a control unit 200, and a skew code output unit 300.

Referring to FIG. 1, an operation of a voltage trimming circuit of a semiconductor device according to an exemplary embodiment of the present invention will be described below.

The voltage generator 500 compares the reference voltage VREF with the feedback voltage VFEED and transmits an activated signal to the seventh node n7 when the reference voltage VREF is higher than the feedback voltage VFEED. Output In this case, the second NMOS transistor N2 outputs the first voltage VREF1 to the first node n1 in response to the activation signal output from the seventh node n7.

The voltage level selector 600 receives the first voltage VREF1 and outputs a variable second voltage VREF2 in response to the enable signal EN and the first external clock CLK1. The voltage level selector 600 compares the enable signal EN and the first external clock CLK1 to detect whether the semiconductor device has a PVT variation. The voltage level selector 600 detects a change in the PVT of the semiconductor device and changes the voltage level of the second voltage VREF2.

The voltage level selector 600 receives the enable signal EN and the first external clock CLK1 to generate a plurality of skew codes T <1: 3> and a plurality of skew code generators 700. And a trimming circuit 400 for changing the voltage level of the second voltage VREF2 in response to the skew codes T <1: 3>.

The skew code generation unit 700 includes a counting unit 100, a control unit 200, and a skew code output unit 300.

In detail, the counting unit 100 divides the first external clock CLK1 in response to the enable signal EN to generate a plurality of external clocks CLK1, CLK2, and CLK3.

The enable signal EN may be a mode register set (“MRS”) signal.

The control unit 200 receives the enable signal EN and generates an control signal VOUT by oscillating.

The skew code output unit 300 receives a plurality of external clocks CLK1, CLK2, and CLK3 and outputs a plurality of skew codes T <1: 3> in response to the control signal VOUT.

The trimming circuit unit 400 includes a connection unit 410 and a voltage divider 420.

The connection part 410 includes a plurality of switches, and the voltage divider 420 includes a plurality of resistance elements.

The voltage divider 420 includes first to fifth resistors R1, R2, R3, R4, and R5. The first resistor R1 is connected between the first node n1 and the second node n2, the second resistor R2 is connected between the second node n2 and the third node n3, The third resistor R3 is connected between the third node n3 and the fourth node n4, the fourth resistor R4 is connected between the fourth node n4 and the fifth node n5, The fifth resistor R5 is connected between the fifth node n5 and the ground resistor.

The voltage generator 500 includes a comparator 510, a second NMOS transistor N2, a sixth resistor R6, and a seventh resistor R7. The comparator 510 compares the reference voltage VREF with the feedback voltage VFEED and outputs the same to the seventh node n7. The second NMOS transistor N2 is connected between the driving voltage VDD terminal and the first node n1, and an output signal of the seventh node n7 is input through the gate. The sixth resistor R6 is connected between the first node n1 and the sixth node n1, and the seventh resistor is connected between the sixth node n6 and the ground voltage VSS.

The voltage generator 500 compares the reference voltage VREF with the feedback voltage VFEED and transmits an activated signal to the seventh node n7 when the reference voltage VREF is higher than the feedback voltage VFEED. Output In this case, the second NMOS transistor N2 outputs the first voltage VREF1 to the first node n1 in response to the activation signal output from the seventh node n7.

The counting unit 100 in the skew code generator 700 divides the second external clock CLK2 and the first external clock CLK1 into which the first external clock CLK1 is divided in two in response to the enable signal EN. A third external clock CLK3 divided by four is generated. The counting unit 100 that divides the first external clock CLK1 into two or four divisions may include a plurality of flip-flops that divide the clock in response to the enable signal EN.

The controller 200 generates a control signal VOUT in response to the signal oscillating the enable signal EN. Therefore, since the control signal VOUT is output in response to a signal passing through the ring oscillator used in the semiconductor device, it is possible to determine whether PVT fluctuations of the semiconductor device occur based on the output timing of the control signal VOUT.

The skew code output unit 300 includes a plurality of switches and a plurality of latches, and latches the first to third external clocks CLK1, CLK2, and CLK3 output from the counting unit 100 in response to the control signal VOUT. To output a plurality of skew codes T <1: 3>. Since the timing of outputting the control signal VOUT changes due to the PVT variation of the semiconductor device, the plurality of skew codes T <1: 3> latching the first to third external clocks CLK1, CLK2, and CLK3 are connected to the semiconductor device. It depends on the PVT fluctuations. In other words, the plurality of skew codes T <1: 3> and the plurality of skew codes T <1: 3> may vary when there is no PVT variation and when the PVT variation occurs.

The trimming circuit 400 determines the resistance value of the voltage divider 420 in response to the plurality of skew codes T <1: 3>, and divides the first voltage VREF1 according to the resistance value to divide the second voltage. Output the voltage VREF2.

For example, based on the voltage level of the second voltage VREF2 when there is no PVT variation of the semiconductor device, when the PVT variation of the semiconductor device occurs, the voltage of the second voltage VREF2 output from the trimming circuit unit 400 is generated. The level is higher or lower when there is no PVT variation of the semiconductor device. Specifically, the trimming circuit unit 400 lowers the voltage level of the second voltage VREF2 by increasing the resistance value in the voltage divider 420 when the "fast PVT fluctuation" occurs, and the voltage when the "slow PVT fluctuation" occurs. The resistance value of the divider 420 is decreased to increase the voltage level of the second voltage VREF2.

2 is a circuit diagram of the controller 200 of FIG. 1.

Referring to FIG. 2, the control unit 200 according to an embodiment of the present invention may include a ring oscillator 210, a delay unit 220, a first latch unit 230, a first driver 240, and a second driver 250. ).

The ring oscillator 210 includes a first NAND gate ND1 and first to second inverters IV1 and IV2. The delay unit 220 includes a first delay element D1 and a third inverter IV3. The first latch unit 230 includes fourth to fifth inverters IV4 and IV5. In addition, the first driver 240 may be configured as a first PMOS transistor P1, and the second driver 250 may be configured as a first NMOS transistor N1.

Referring to Figure 2 describes the operation of the control unit 200 according to an embodiment of the present invention.

The ring oscillator 210 receives the enable signal EN and outputs an oscillating signal ROD. The first NAND gate ND1 of the ring oscillator 210 outputs an oscillating signal ROD in response to an enable signal EN and an output signal of the second inverter IV2. The first inverter IV1 inverts the output signal of the first NAND gate ND1 and outputs the inverted signal. The second inverter IV2 inverts the output signal of the first inverter IV1 and outputs the inverted signal. The first driver 240 outputs a signal to the eighth node n8 in response to the oscillating signal ROD. In detail, the first driver 240 may be configured of the first PMOS transistor P1, and the first PMOS transistor P1 is connected between the driving voltage VDD applying terminal and the eighth node n8 and the gate is closed. Through the output signal of the second inverter IV2 is input.

The delay unit 220 includes a delay element D1 that receives the enable signal EN and outputs the delayed time by a predetermined time, and a third inverter IV3 that inverts and outputs the output signal of the delay element D1. The delay unit 220 has a larger signal delay amount than the first NAND gate ND1 and a smaller signal delay amount than the ring oscillator 210. Here, the signal delay amount of the ring oscillator 210 refers to the delay amount when sequentially passing through the first NAND gate ND1, the first inverter IV1, and the second inverter IV2. As a result, when the signal delay amounts are arranged in large order, the signal delay amount of the ring oscillator 210 is greatest, followed by the signal delay amount of the delay unit 220. Finally, the signal delay amount of the first NAND gate ND1 in the ring oscillator 210 is the smallest. Preferably, the amount of signal delay of the ring oscillator 210 is the magnitude of the signal delay of the delay unit 220, and the amount of signal delay of the ring oscillator 210 secures the signal change timing margin of the first latch unit 230. It is larger than the signal delay amount of the delay unit 220. Ideally, the signal delay amount of the delay unit 220 and the ring oscillator 210 should be the same, but the signal delay amount of the ring oscillator 210 is delayed to secure the signal change timing margin of the first latch unit 230. The second driver 250 outputs a signal to the eighth node n8 in response to an output signal of the third inverter IV3. In detail, the second driver 250 may include the first NMOS transistor N1, and the first NMOS transistor N1 is connected between the eighth node n8 and the ground voltage VSS and is connected to the gate through the gate. The output signal of the third inverter IV3 is input.

The first latch unit 230 inverts the fourth inverter IV4 and the control signal VOUT, which inverts the output signal of the eighth node n8 and outputs the control signal VOUT, to the eighth node n8. And a fifth inverter IV5 for outputting.

Meanwhile, when the enable signal EN input to the ring oscillator 210 is activated, an oscillating signal ROD having a predetermined logic level is output. The first driver 240 is not driven while the oscillating signal ROD has a predetermined logic level. However, if the enable signal EN is activated, the delay unit 220 outputs a control signal VOUT that is activated after a predetermined time delay. In other words, when the enable signal EN is activated, the controller 200 outputs a control signal VOUT deactivated while the oscillating signal ROD has a predetermined logic level, and the logic of the oscillating signal ROD. The control signal VOUT, which is activated at the timing of the level transition, is output. When the oscillating signal ROD transitions from the predetermined logic level, the first driver 240 deactivates the control signal VOUT in response to the transitioned logic level.

Thereafter, the ring oscillator 210 outputs an oscillating signal ROD to which the logic level continuously transitions. However, the enable signal EN is deactivated later, and the second driver 250 that responds to the output signal of the delay unit 220 is not driven and thus the control signal VOUT is deactivated.

Therefore, even when the logic level of the oscillating signal ROD output from the ring oscillator 210 continues to transition, the control signal VOUT is activated only when the oscillating signal ROD transitions to the first logic level. In this case, the control signal VOUT is deactivated.

Considering that the signal delay amount of the delay unit 220 is greater than the signal delay amount of the first NAND gate ND1 and smaller than the signal delay amount of the ring oscillator 210, the enable signal EN is low level for a predetermined time. Referring to the operation of the control unit 200 from the time point is input as a pulse as follows.

When the enable signal EN is input to the ring oscillator 210 as a low level pulse for a predetermined time, the oscillating signal ROD becomes high level. When the oscillating signal ROD having a high level pulse width is input to the first driver 240, the first driving unit 240 is not driven.

When the enable signal EN is input as a low level pulse, the delay unit 220 inverts the predetermined time delay and outputs a high level pulse. The second driver 250 pulls down the eighth node n8 in response to the high level pulse of the delay unit 220 output for a predetermined time, thereby reducing the logic level of the eighth node n8. Make it low level. The first latch unit 230 latches the low level eighth node n8 output signal and inverts it to output the control signal VOUT having the high level.

Next, while the second driver 250 pulls down the eighth node n8 in response to the output signal of the second delay unit 220, the high level oscillating signal ROD is applied to the first inverter IV1. ) And passes through the second inverter IV2. At this time, a high level signal is output from the second inverter IV2. The first NAND gate ND1 outputs the low level oscillating signal ROD in response to the high level second inverter IV2 output signal and the enable signal EN transitioned to the high level. When the low level oscillating signal ROD is output from the oscillator 210, the first driver 240 pulls up the output signal of the eighth node n8. At this time, the logic level of the eighth node n8 becomes a high level, and the first latch unit 230 latches and inverts the output signal of the eighth node n8 to output a low-level control signal VOUT. .

Thereafter, the ring oscillator 210 outputs an oscillating signal ROD to which the logic level continuously transitions. However, since the first latch unit 230 latches and inverts the output signal of the eighth node n8 having the high level, there is no change in the logic level of the control signal VOUT having the low level.

Therefore, even if the logic level of the oscillating signal ROD output from the ring oscillator 210 continues to transition, the logic level of the control signal VOUT is high level only when the oscillating signal ROD is the first high level section. In other cases, the logic level of the control signal VOUT becomes a low level.

In addition, since the control signal VOUT depends on the ring oscillator 210, the output timing varies according to the PVT variation of the semiconductor device.

In the case of "fast PVT fluctuation", the enable signal EN passes quickly through the ring oscillator 210, and the high level section of the oscillating signal ROD becomes shorter than when there is no PVT fluctuation. However, in the case of "slow PVT fluctuation", the enable signal EN passes slowly through the ring oscillator 210, and the high level period of the oscillating signal ROD becomes longer than when there is no PVT fluctuation.

When the enable signal EN having a predetermined low level pulse width is input to the controller 200, when the oscillating signal ROD is the first high level section, the control signal VOUT having the high level is output. Thereafter, when the oscillating signal ROD transitions to a low level, the logic level of the control signal VOUT is changed to a low level and output.

3 is a circuit diagram of the skew code output unit 300 of FIG. 1.

Referring to FIG. 3, the skew code output unit 300 according to the embodiment of the present invention will be described.

The skew code output unit 300 includes first to third switch units 310, 311, and 312 and second to fourth latch units 320, 321, and 322.

The first switch unit 310 in response to the output signal of the twelfth inverter IV12, the control signal VOUT, and the twelfth inverter IV12 that inverts the control signal VOUT and outputs the first external clock CLK1. It includes a first pass gate (PG1) for outputting to the ninth node (n9). The second switch unit 311 in response to the output signal of the thirteenth inverter IV13, the control signal VOUT, and the thirteenth inverter IV13 that inverts the control signal VOUT and outputs the second external clock CLK2. It includes a second pass gate (PG2) for outputting to the tenth node (n10). The third switch 312 is in response to an output signal of the fourteenth inverter IV14, the control signal VOUT, and the fourteenth inverter IV14 that inverts the control signal VOUT and outputs the third external clock CLK3. It includes a third pass gate (PG3) for outputting the to the eleventh node (n11).

The second latch unit 320 inverts the output signals of the ninth node n9 and outputs the inverted output signals of the sixth inverter IV6 and the sixth inverter IV6 to the ninth node n9. And a seventh inverter IV7.

The third latch unit 321 inverts the output signals of the eighth inverter IV8 and the eighth inverter IV8 by inverting the output signal of the tenth node n10 and outputs the inverted signals to the tenth node n10. A ninth inverter IV9 is included.

The fourth latch unit 322 inverts the output signals of the eleventh node n11 and outputs the inverted output signals of the tenth inverter IV10 and the tenth inverter IV10 to the eleventh node n11. An eleventh inverter IV11 is included.

Referring to Figure 3 describes the operation of the skew code output unit 300 according to an embodiment of the present invention.

The first switch unit 310 outputs the first external clock CLK1 to the ninth node n9 in response to the control signal VOUT. At this time, when the oscillating signal ROD outputs the high level oscillating signal ROD by the enable signal EN, the control signal VOUT transitions to the low level oscillating signal ROD for the first time. Only activated.

In detail, when the timing of generating the high level pulse of the control signal VOUT is general based on when there is no PVT variation, the enable signal EN passes rapidly through the ring oscillator 210 when the “fast PVT variation” is performed. The high level section of the oscillating signal ROD is shorter than when there is no PVT variation. At this time, the timing of generating the high level pulse of the control signal VOUT also becomes faster. The first to third switch units 310, 311, and 312 output the first to third external clocks CLK1, CLK2, and CLK3 to the ninth to eleventh nodes n9, n10, and n11 faster than when there is no PVT fluctuation. .

However, in the case of "slow PVT fluctuation", the enable signal EN passes slowly through the ring oscillator 210, and the high level period of the oscillating signal ROD becomes longer than when there is no PVT fluctuation. At this time, the high level pulse generation timing of the control signal VOUT is slowed down. The first to third switch units 310, 311, and 312 output the first to third external clocks CLK1, CLK2, and CLK3 to the ninth to eleventh nodes n9, n10, and n11 more slowly than when there is no PVT fluctuation. .

Accordingly, the logic levels of the first to third external clocks CLK1, CLK2, and CLK3 latched to the second to fourth latch units 320, 321, and 322 are changed by PVT fluctuations, and the second to fourth latch units 320 are different. , Logic levels of the first to third skew codes T <1: 3> output from 321 and 322 also vary according to the PVT variation.

4 is a circuit diagram of the trimming circuit unit 400 of FIG. 1.

The trimming circuit unit 400 according to the embodiment of the present invention will be described with reference to FIG. 4.

The trimming circuit unit 400 includes a connection unit 410 and a voltage divider unit 420.

The connection part 410 is a fourth passgate PG4 connected between the first node n1 and the second node n2, and a fifth pass connected between the second node n2 and the third node n3. And a sixth passgate PG6 connected between the gate PG5 and the third node n3 and the fourth node n4.

The voltage divider 420 includes a first resistor R1 connected between the first node n1 and a second node, and a second resistor R2 connected between the second node n2 and the third node n3. ), A third resistor R3 connected between the third node n3 and the fourth node n4, a fourth resistor R4 connected between the fourth node n4 and the fifth node n5, and The fifth resistor R5 is connected between the fifth node n5 and the ground voltage VSS. The first voltage VREF1 is input to the first node n1, and the second voltage VREF2 is output from the fifth node n1.

An operation of the trimming circuit unit 400 according to an embodiment of the present invention will be described with reference to FIG. 4.

The connection unit 410 determines whether the first to fourth nodes n1, n2, n3, and n4 are connected in response to the first to third skew codes T <1: 3>. The voltage divider 420 divides the first voltage VREF1 by the resistance value to generate the second voltage VREF2. The resistance value of the voltage divider 420 is controlled by whether the first to fourth nodes n1, n2, n3, and n4 are connected.

In detail, the trimming circuit unit 400 lowers the voltage level of the second voltage VREF2 based on the voltage level of the second voltage VREF2 when there is no PVT change, and “low PVT” when the “fast PVT change” occurs. If the variation occurs, the voltage level of the second voltage VREF2 is increased.

For example, when the connection unit 410 connects the first node n1 and the second node n2 in response to the first to third skew codes T <1: 3> when there is no PVT variation, The resistance value of the distribution 420 is R2 + R3 + R4 + R5.

On the other hand, when the “fast PVT variation” occurs, if the connection unit 410 does not connect any node in response to the first to third skew codes T <1: 3>, the resistance value of the voltage divider 420 is R1 + R2 + R3 + R4 + R5. At this time, the total resistance value is increased than when there is no PVT variation of the voltage divider 420, thereby lowering the voltage level of the second voltage VREF2.

In addition, when “slow PVT fluctuation” occurs, the connection unit 410 connects the first node n1 and the second node n2 in response to the first to third skew codes T <1: 3>, and When the two nodes n2 and the third node n3 are connected, the resistance value of the voltage divider 420 becomes R3 + R4 + R5. At this time, the total resistance value decreases compared to when there is no PVT variation of the voltage divider 420, thereby increasing the voltage level of the second voltage VREF2. As another example, when the connection unit 410 connects the second node n2 and the third node n3 in response to the first to third skew codes T <1: 3>, the resistance of the voltage divider 420 may be reduced. The value is R1 + R3 + R4 + R5. At this time, when the value of the first resistor R1 is smaller than the value of the second resistor R2, the total resistance value is reduced compared to when there is no PVT variation of the voltage divider 420 so that the voltage level of the second voltage VREF2 is Increases

5 is a timing diagram of a voltage trimming circuit of a semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 1 to 5, the operation of the voltage trimming circuit of the semiconductor device according to the embodiment of the present invention will be described below.

When the enable signal EN transitions to the low level, the counting unit 100 divides the first external clock CLK1 to generate a second external clock CLK2 and a third external clock CLK3. Dividing the frequency of the first external clock CLK1 by two divides the second external clock CLK2, and dividing the frequency of the first external clock CLK1 by four divides the third external clock CLK3.

The controller 200 receives the enable signal EN and generates an oscillating signal ROD. The oscillating signal (ROD) is based on the absence of PVT fluctuations. When the "fast PVT fluctuation" occurs, the enable signal (EN) passes quickly through the ring oscillator, so the oscillating signal ( ROD) logic level transitions. In contrast, when the "slow PVT fluctuation" occurs, the enable signal EN passes slowly through the ring oscillator, so that the logic level of the oscillating signal ROD is slower than when there is no PVT fluctuation.

The control signal VOUT output from the controller 200 is activated when the oscillating signal ROD transitions to a logic level. The skew code output 300 stores logic levels of the first to third external clocks CLK1, CLK2, and CLK3 at the time when the control signal VOUT is activated, thereby generating the first to third skew codes T <1: 3>. Outputs

For example, when there is no PVT variation, the logic level of the first external clock CLK1 is low, the logic level of the second external clock CLK2 is high, and the logic level of the third external clock CLK3 is high. The first skew code T1 is at a high level, the second skew code T2 is at a low level, and the logic level of the third skew code T3 is at a low level. In this case, the trimming circuit unit 400 connects the first node n1 and the second node n2 in response to the first to third skew codes T <1: 3>. Therefore, when there is no PVT variation, the total resistance value of the voltage divider 420 becomes R2 + R3 + R4 + R5.

On the other hand, the logic level of the first external clock CLK1 is high level when the "fast PVT fluctuation" occurs, the logic level of the second external clock CLK2 is high level, and the logic level of the third external clock CLK3 is Since it is high level, the first skew code T1 is low level, the second skew code T2 is low level, and the logic level of the third skew code T3 is low level. In this case, the trimming circuit unit 400 does not connect any node in response to the first to third skew codes T <1: 3>. Thus, when "fast PVT variation" occurs, the total resistance value of the voltage divider 420 becomes R1 + R2 + R3 + R4 + R5. The total resistance value of the voltage divider 420 is increased compared to when there is no PVT variation, thereby lowering the voltage of the second voltage VREF2.

In addition, when the "slow PVT fluctuation" occurs, the logic level of the first external clock CLK1 is high level, the logic level of the second external clock CLK2 is low level, and the logic level of the third external clock CLK3 is Since it is high level, the first skew code T1 is low level, the second skew code T2 is high level, and the logic level of the third skew code T3 is low level. In this case, the trimming circuit unit 400 connects the second node n2 and the third node n3 in response to the first to third skew codes T <1: 3>. Thus, when "slow PVT fluctuation" occurs, the total resistance value of the voltage divider 420 becomes R1 + R3 + R4 + R5. If the value of the first resistor R1 is smaller than the value of the second resistor R2, the total resistance of the voltage divider 420 is smaller than that of the PVT fluctuation, thereby increasing the voltage of the second voltage VREF2.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: counting unit 200: control unit
210: ring oscillator 220: delay unit
230: first latch portion 240: first drive portion
250: second drive unit 300: skew code output unit
310: first switch unit 311: second switch unit
312: second switch unit 320: second latch unit
321: third latch portion 322: fourth latch portion
400: trimming circuit portion 410: connection portion
420: voltage divider 500: voltage generator
510: comparator 600: voltage level selector
700: skew code generation unit

Claims (21)

A semiconductor comprising a voltage level selector configured to compare an oscillation signal passing the enable signal to the oscillator and an external clock, and variably divide the first voltage output from the voltage generator in response to the comparison result to output a second voltage. Voltage trimming circuit of the device.
The method of claim 1,
The voltage level selector,
When the oscillation signal transitions faster than the time when the logic level of the oscillation signal transitions when the PVT variation of the semiconductor device does not occur, the voltage level of the second voltage does not occur when the PVT variation of the semiconductor device occurs. And lowering the voltage trimming circuit of the semiconductor device.
The method of claim 1,
The voltage level selector,
When the oscillation signal transitions later than the time when the logic level of the oscillation signal transitions when there is no PVT variation of the semiconductor device, when the PVT variation of the semiconductor device does not occur It is higher, the voltage trimming circuit of the semiconductor device.
The method of claim 1,
The voltage level selector,
Generate a control signal that is activated only when the logic level of the oscillation signal first transitions, and divide the external clock in response to the enable signal to generate a plurality of external clocks, and when the control signal is activated, the plurality of external clocks. A skew code generation unit configured to output a clock as a plurality of skew codes; And
And a trimming circuit unit which outputs the second voltage in response to the skew code.
5. The method of claim 4,
The skew code generation unit,
A counting unit which divides the enable signal and the external clock to generate the plurality of external clocks; And
A controller configured to generate the oscillation signal by passing the enable signal through the oscillator, and generate the control signal that is activated only when the oscillation signal first transitions to a logic level; And
And a skew code output unit configured to latch the plurality of external clocks and output the plurality of skew codes in response to the control signal.
5. The method of claim 4,
The trimming circuit unit,
A plurality of resistors between the first voltage and the ground voltage,
And adjusting the connection of the plurality of resistors in response to the plurality of skew codes to generate the second voltage.
The method of claim 1,
The enable signal,
And a mode register set signal.
A counting unit configured to receive a first external clock and output a plurality of external clocks including the first external clock in response to an enable signal;
A controller configured to receive the enable signal and output a control signal having a different activation timing according to a PVT variation of a semiconductor device;
A skew code output unit configured to receive the plurality of external clocks and output a plurality of skew codes in response to the control signal; And
And a trimming circuit configured to variably divide the first voltage output from the voltage generator and output a second voltage in response to the plurality of skew codes.
The method of claim 8,
The counting unit,
And dividing the first external clock to output a second external clock and a third external clock when the enable signal is activated.
The method of claim 9,
The counting unit,
And when the enable signal is activated, outputting the second external clock dividing the frequency of the first external clock by two and the third external clock dividing the first external clock by four. Circuit.
The method of claim 8,
The control unit,
An oscillator configured to receive the enable signal and generate an oscillation signal;
A delay unit delaying the enable signal for a predetermined time and inverting the output signal;
A first driver outputting a signal to a first node in response to an output signal of the oscillator;
A second driver outputting a signal to the first node in response to an output signal of the delay unit; And
And a first latch unit for latching an output signal of the first node to output the control signal.
12. The method of claim 11,
Wherein the delay unit comprises:
And delaying the enable signal by the time passing through the oscillator.
12. The method of claim 11,
Wherein the control signal comprises:
And the voltage trimming circuit of the semiconductor device is activated only when the logic level of the oscillation signal is first transitioned.
The method of claim 10,
The skew code output unit,
And a plurality of switch parts for determining whether the plurality of external clocks are output in response to the control signal, and a plurality of latch parts for latching signals output from the plurality of switch parts. .
15. The method of claim 14,
The skew code output unit
A first switch unit configured to determine whether to output the first external clock in response to the control signal;
A second switch unit configured to determine whether to output the second external clock in response to the control signal;
A third switch unit configured to determine whether to output the third external clock in response to the control signal;
A second latch unit for latching an output signal of the first switch unit to output a first skew code;
A third latch unit for latching an output signal of the second switch unit to output a second skew code; And
And a fourth latch unit for latching an output signal of the third switch unit and outputting a third skew code.
The method of claim 8,
The trimming circuit unit,
A voltage divider having a plurality of resistors connected in series between the first voltage and the ground voltage; And
And a connection unit connected between the plurality of resistors and connected between the plurality of resistors in response to the plurality of skew codes.
17. The method of claim 16,
The connecting portion
A voltage trimming circuit of a semiconductor device, comprising a plurality of passgates.
The method of claim 8,
And the counting unit includes a plurality of flip-flops.
The method of claim 8,
The enable signal,
And a mode register set signal.
12. The method of claim 11,
The first drive unit,
A voltage trimming circuit of a semiconductor device, characterized in that it is a PMOS transistor.
12. The method of claim 11,
The second drive unit,
A voltage trimming circuit of a semiconductor device, characterized in that it is an NMOS transistor.
KR1020120096894A 2012-09-03 2012-09-03 Voltage trimming circuit of semiconductor apparatus KR20140030568A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10074412B2 (en) 2016-11-21 2018-09-11 SK Hynix Inc. Semiconductor memory device and method for operating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10074412B2 (en) 2016-11-21 2018-09-11 SK Hynix Inc. Semiconductor memory device and method for operating the same

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