KR20140026182A - Semiconductor memory apparatus - Google Patents
Semiconductor memory apparatus Download PDFInfo
- Publication number
- KR20140026182A KR20140026182A KR1020120093243A KR20120093243A KR20140026182A KR 20140026182 A KR20140026182 A KR 20140026182A KR 1020120093243 A KR1020120093243 A KR 1020120093243A KR 20120093243 A KR20120093243 A KR 20120093243A KR 20140026182 A KR20140026182 A KR 20140026182A
- Authority
- KR
- South Korea
- Prior art keywords
- data
- output
- signal
- data storage
- test
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
Description
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory device.
The semiconductor memory device stores data and outputs the stored data. Such a semiconductor memory device performs a test in a wafer state, and a normal semiconductor memory device is packaged and manufactured as a product.
As shown in FIG. 1, the general
The
When testing a semiconductor memory device in a wafer state, signals are transferred between a test device and a semiconductor memory device by using the
The test includes a test for determining whether the stored data after the read command is output to the outside of the semiconductor memory device at a set time.
In this case, the stored data is tested using the
In particular, when the
The present invention provides a semiconductor memory device in which a test for determining whether stored data after a read command is output outside the semiconductor memory device at a set time can be easily performed.
In an embodiment, a semiconductor memory device may include a data storage area for storing data, a plurality of data lines connected to the data storage area, and a plurality of data lines for inputting and outputting data, the plurality of data lines, and a plurality of bump pads, respectively. And a plurality of data output units configured to output data input from the data storage area through the plurality of data lines to the plurality of bump pads, and to receive, store, and output the outputs of the plurality of data output units in response to a clock. A plurality of data storage units, an output unit of the plurality of data storage units, and a data determination unit that outputs a result signal to a probe test pad in response to a test data selection signal.
A semiconductor memory device according to another embodiment of the present invention includes a data storage area for storing data and sequentially outputs high-level data and low-level data in response to a read command. A data storage unit for receiving and storing the data, and outputting the data, and enabling a result signal when an output signal of the data storage unit transitions from a low level to a high level, or output signals of the data storage unit And a data determiner for enabling the resultant signal when transitioning to a low level.
According to another exemplary embodiment of the present inventive concept, a test method of a semiconductor memory device includes a data storage step of storing high-level data and low-level data in a data storage area, and inputting two read commands to the high-level data and the A data output step of outputting one of the low-level data first, and outputting the other one, a data storage step of inputting and storing a signal output from the data output step in response to a clock, and outputting the data in the data storage step And a result signal output step of outputting a result signal, which is disabled and enabled in response to the test data selection signal, to a probe test pad, and a timing at which a read command input later of the two read commands is input. Until the timing at which the resulting signal is enabled. And a test result determination step of determining the test result by measuring the liver.
The semiconductor memory device according to the present invention can accurately determine the test result, thereby improving the reliability of the semiconductor memory device.
1 is a configuration diagram of a semiconductor memory device;
2 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention;
3 is a configuration diagram of a first data storage unit of FIG. 2;
4 is a configuration diagram of a data determination unit of FIG. 2;
5 and 6 are timing diagrams of a semiconductor memory device according to an embodiment of the present invention.
As shown in FIG. 2, in the semiconductor memory device according to the embodiment of the present invention, the
The
The first to third
Each of the first to third
When the test mode signal TM_tAA is enabled, the first
When the test mode signal TM_tAA is enabled, the second
The third
The data determiner 500 outputs a result signal RESULT to the
The first to third
As illustrated in FIG. 3, the first
When the test mode signal TM_tAA is disabled, the first
As illustrated in FIG. 4, the
When the test data selection signal TM_DS is enabled, the
The operation of the semiconductor memory device according to the embodiment of the present invention configured as described above will be described with reference to FIGS. 2 to 4.
The
When a read command is input, the
The first to third
The first to third data storages 310 to 330 receive and store the first to third output data Data_A, Data_B, and Data_C in response to the clock CLK when the test mode signal TM_tAA is enabled. The stored data is output as the first to third stored data Data_saA, Data_saB, and Data_saC. The first to third
The first to
When the test data selection signal TM_DS is enabled, the
The
The test method of the semiconductor memory device operating as described above will be described with reference to FIGS. 5 and 6.
The high level data and the low level data are stored in the
Two consecutive read commands RD are input to first output one of the high level data and the low level data stored in the
When the clock CLK transitions to a high level, the data output from the
When the clock CLK transitions to a high level, the result signal RESULT, which is disabled and enabled in response to the stored data and the test data selection signal, is output to the
5 and 6 assume that the CAS latency at which data is output to the outside of the semiconductor memory device when the clock CLK has passed three cycles after the read command RD is three.
In FIG. 5A, high-level data and low-level data are stored in the
After three cycles of the clock CLK have elapsed since the first read command RD has been input, the first to third output data Data_A and Data_B having high levels are provided through the first to third
After three cycles of the clock CLK have passed since the second read command RD is input, the first to third output data Data_A having a low level through the first to third
The first to third output data Data_A, Data_B, and Data_C of the high level output through the first read command RD are stored when the clock CLK transitions to the high level to store the first to third stored data ( Data_saA, Data_saB, Data_saC) are output.
The first to third stored data Data_saA, Data_saB, and Data_saC of the high level generated by the first read command RD are the first to third stored data Data_saA of the low level by the second read command RD. The data value is maintained until Data_saB and Data_saC) are generated.
Since the test data selection signal TM_DS is disabled at the low level, the
Accordingly, the resultant signal until the first to third stored data Data_saA, Data_saB, and Data_saC of the high level generated by the first read command RD are transitioned to the low level by the second read command RD. (RESULT) is disabled at the low level. Therefore, when the first to third stored data Data_saA, Data_saB, and Data_saC of low level are generated by the second read command RD, the result signal RESULT is enabled to the high level.
In a method of testing a semiconductor memory device in accordance with an embodiment of the present invention by connecting a semiconductor memory device in a wafer state to a test device, the read command RD is input from the test device to the semiconductor memory device in a wafer state, The
Therefore, after the second read command RD is input, the time for which the result signal RESULT outputted through the
In FIG. 5B, first through third output data Data_A, Data_B, and Data_C having low levels are first outputted through two consecutive read commands RD, and then the first through third of high levels are output. 3 When the output data Data_A, Data_B, and Data_C are output, the timing diagram for performing the test by enabling the test data selection signal TM_DS to a high level is shown.
In FIGS. 5A and 5B, when three cycles of the clock CLK have elapsed after the read command is input, the cascade latency CL for outputting data stored in the
5A and 5B show a result signal RESULT output from the
6C and 6D, the data stored in the
In case (C) of FIG. 6, the first to third output data Data_A, Data_B, and Data_C having a high level are output to the first read command RD, and the first to the low level to the second read command RD. Third output data Data_A, Data_B, Data_C are output.
The first to third output data Data_A, Data_B, and Data_C of the high level output by the first read command RD have three cycles of the clock CLK after the first read command RD is input. The first to third stored data (Data_saA, Data_saB, Data_saC) are not stored in the first to third
The first to third output data Data_A, Data_B, and Data_C of the low level output by the second read command RD and three cycles of the clock CLK have elapsed after the second read command RD is input. It is not stored at the point of time, and is stored at the time when four cycles of the clock CLK pass and is input to the
Therefore, the
The semiconductor memory device of the present invention should output the output data Data_A, Data_B, and Data_C at the time when three cycles of the clock CLK pass after the read command RD is input, as shown in FIG. After the read command RD is input, output data Data_A, Data_B, and Data_C are output between three and four periods of the clock CLK. The output data Data_A, Data_B, and Data_C are stored and output as stored data Data_saA, Data_saB, and Data_saC when the clock CLK passes four cycles after the read command RD is input.
Therefore, when the stored data Data_saA, Data_saB, and Data_saC transition from the high level to the low level, the result signal RESULT also transitions from the low level to the high level, and the timing at which the result signal RESULT transitions to the high level has two timings. The clock CLK passes four cycles after the first read command RD.
Therefore, in FIG. 6C, the resultant signal REULT transitions to a high level later than one cycle of the clock CLK in comparison with the case of FIG. 5A.
Therefore, in the normal case, when the second read command RD is input and three cycles of the clock CLK pass, the resultant signal RESULT should transition to a high level. However, FIG. 6A illustrates the second read command RD. ), And the resultant signal RESULT transitions to a high level when four cycles of the clock CLK pass, it can be seen that the test result of the semiconductor memory device is a fail.
6D, the output data Data_A, Data_B, and Data_C output by the first read command RD are at a low level, and the output data Data_A and Data_B output by the second read command RD. , Data_C) is at a high level. Therefore, the stored data Data_saA, Data_saB, and Data_saC by the first read command RD are at low level, and the stored data Data_saA, Data_saB, Data_saC by the second read command RD is at high level.
The result signal RESULT is enabled from the low level to the high level when the stored data Data_saA, Data_saB, and Data_saC transition from the low level to the high level.
In the case of FIG. 6D, as in FIG. 6C, the resultant signal RESULT is enabled when the clock CLK has passed four cycles after the second read command RD has been input. You can see that the test results of the device are failing.
As a result signal RESULT is output through the
As described above, the semiconductor memory device according to the embodiment stores the output data Data_A, Data_B, and Data_C output to the
It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.
Claims (13)
A plurality of data lines connected to the data storage area to input and output the data;
A plurality of data output units connected to the plurality of data lines and the plurality of bump pads, respectively, and outputting data input from the data storage area through the plurality of data lines to the plurality of bump pads;
A plurality of data storage units configured to receive, store, and output the outputs of the plurality of data output units in response to a clock; And
And a data determination unit outputting a result signal to a probe test pad in response to an output of the plurality of data storage units and a test data selection signal.
The probe test pad is larger in size than the bump pad.
The plurality of data storage unit
And receiving and storing outputs of the plurality of data output units when the clock transitions to a specific level, and outputs the stored values.
The plurality of data storage unit
When the test mode signal is enabled, when the clock transitions to a specific level, the output of the plurality of data output units is received and stored.
And preventing output of the plurality of data output units from being input when the test mode signal is disabled.
The data determination unit
When the test data selection signal is enabled, when the outputs of the plurality of data storage units are all at a high level, the result signal is enabled.
And if the test data selection signal is disabled, when the outputs of the plurality of data storage units are all at a low level, the result signal is enabled.
A data output step of inputting two read commands to output one of the high level data and the low level data first and then output the other one;
A data storage step of inputting and storing a signal output in the data output step in response to a clock, and outputting the signal;
A result signal output step of outputting a signal output in the data storage step and a result signal disabled and enabled in response to a test data selection signal to a probe test pad; And
And a test result determining step of determining a test result by measuring a time from a timing at which a read command input later among the two read commands is input to a timing at which the result signal is enabled. Way.
The result signal output step is
When the test data selection signal is enabled and the signal output in the data storage step changes from a low level to a high level, the result signal is disabled when the signal output in the data output step is low level, and the data output step A first output step of enabling the resultant signal if the signal output from the signal is at a high level, and
When the test data selection signal is disabled and the signal output in the data output stage changes from a high level to a low level, the result signal is disabled when the signal output in the data output stage is a high level, and the data output stage And a second output step of enabling the resultant signal when the signal output from the low level is low.
The data storage step
Receiving and storing a signal output in the data output step when the clock transitions to a high level when a test mode signal is enabled; and
Preventing the signal output in the data output step from being input and stored when the test mode signal is disabled.
A data storage unit for receiving and storing the data in response to a clock and outputting the data; And
A data determination unit that enables a result signal when the output signal of the data storage unit transitions from a low level to a high level, or enables the result signal when the output signal of the data storage unit transitions from a high level to a low level A semiconductor memory device comprising: a.
The data storage unit
When the test mode signal is enabled, the data is received, stored, and outputted in response to the clock.
And preventing the data from being input when the test mode signal is disabled.
The data determination unit
When the test data selection signal is enabled, the result signal is enabled when the output signal of the data storage unit transitions from a low level to a high level.
And if the test data selection signal is disabled, enabling the result signal when the output signal of the data storage unit transitions from a high level to a low level.
A data output step of inputting two read commands, outputting a plurality of the high level data to a first read command, and then outputting a plurality of the low level data to a second read command;
A data storage step of inputting, storing, and outputting signals output in the data output step in response to a clock;
Disabling the resultant signal in response to the timing of the last output signal among the signals output by the first read command in the data storage step, and among the signals output by the second read command in the data storage step A result signal output step of enabling the result signal in response to a timing of a signal output last; And
And determining a test result by measuring a time from a timing at which the second read command is input to a timing at which the result signal is enabled.
The result signal output step is
Disabling the result signal when the signals output by the first read command are all at a high level, and enabling the result signal when the signals output by the second read command are at a low level. A test method for a semiconductor memory device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120093243A KR20140026182A (en) | 2012-08-24 | 2012-08-24 | Semiconductor memory apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120093243A KR20140026182A (en) | 2012-08-24 | 2012-08-24 | Semiconductor memory apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20140026182A true KR20140026182A (en) | 2014-03-05 |
Family
ID=50641009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020120093243A KR20140026182A (en) | 2012-08-24 | 2012-08-24 | Semiconductor memory apparatus |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20140026182A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170077925A (en) * | 2015-12-28 | 2017-07-07 | 에스케이하이닉스 주식회사 | Semiconductor circuit and stack-type memory system |
| US9805824B2 (en) | 2015-09-08 | 2017-10-31 | SK Hynix Inc. | Semiconductor devices and semiconductor systems |
-
2012
- 2012-08-24 KR KR1020120093243A patent/KR20140026182A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9805824B2 (en) | 2015-09-08 | 2017-10-31 | SK Hynix Inc. | Semiconductor devices and semiconductor systems |
| KR20170077925A (en) * | 2015-12-28 | 2017-07-07 | 에스케이하이닉스 주식회사 | Semiconductor circuit and stack-type memory system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6711042B2 (en) | Semiconductor device whereon memory chip and logic chip are mounted, making testing of memory chip possible | |
| US20120138927A1 (en) | Semiconductor device having stacked structure including through-silicon-vias and method of testing the same | |
| US7622908B2 (en) | Built-in system and method for testing integrated circuit timing parameters | |
| JP2021093129A (en) | Technique for command bus training to memory device | |
| KR20140136204A (en) | Semiconductor system | |
| KR20120068620A (en) | Semiconductor memory device and method for testing the same | |
| TWI489473B (en) | Semiconductor memory apparatus and test method thereof | |
| KR20140026182A (en) | Semiconductor memory apparatus | |
| KR101535228B1 (en) | Built off test apparatus | |
| KR102538991B1 (en) | Semiconductor test device and semiconductor test method | |
| US9299403B2 (en) | Semiconductor devices and semiconductor systems including the same | |
| US7853840B2 (en) | Semiconductor memory device and methods thereof | |
| US7802154B2 (en) | Method and apparatus for generating high-frequency command and address signals for high-speed semiconductor memory device testing | |
| KR100825013B1 (en) | Semiconductor device for command test of package level | |
| KR20140075347A (en) | Semiconductor apparatus | |
| JP2010040092A (en) | Semiconductor integrated circuit | |
| JP2016138799A (en) | Semiconductor integrated circuit device and semiconductor integrated circuit device testing method | |
| KR102221417B1 (en) | Biuilt-in test circuit of semiconductor apparatus | |
| KR20150078012A (en) | Semiconductor memory apparatus and test method using the same | |
| US8953391B1 (en) | Semiconductor apparatus | |
| TW201403615A (en) | Memory bank | |
| KR20130072854A (en) | Semiconductor memory system | |
| KR100924303B1 (en) | Method and Apparatus For Monitoring Memory Address | |
| JP2006317178A (en) | SEMICONDUCTOR UNIT OF SiP TYPE | |
| US8549371B1 (en) | Semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |