KR20130070929A

KR20130070929A - Semiconductor memory device and method of operating the same

Info

Publication number: KR20130070929A
Application number: KR1020110138204A
Authority: KR
Inventors: 강정규
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2011-12-20
Filing date: 2011-12-20
Publication date: 2013-06-28

Abstract

PURPOSE: A semiconductor memory device and an operation method thereof are provided to improve the properties of program disturbance by changing a channel boosting level of a channel region in a program prohibition cell. CONSTITUTION: It is determined whether or not a selected word line is a first word line adjacent to a drain selection line or a source selection line(S320). A program loop is performed for storing data in memory cells of the first word line(S330). It is checked whether a threshold voltage of the memory cell is increased to a target level, and a program verification operation is performed to determine the completion of a program operation(S335). It confirms whether the word line in which the program loop is performed is the final word line(S340). [Reference numerals] (AA) Start; (BB,DD,FF) No; (CC,EE,GG) Yes; (HH) End; (S310) Select a first word line; (S320) Edge word line?; (S331) Execute a program operation(channel of a program prohibition cell : Vpre1); (S333) Execute the program operation(channel of the program prohibition cell : Vpre2); (S335) Complete the program?; (S337) Change the voltage of the program; (S340) Last word line?; (S350) Select a next word line

Description

Semiconductor memory device and method of operating same

The present invention relates to a semiconductor memory device and a method of operating the same, and more particularly, to a semiconductor memory device for storing data and a method of operating the same.

In a NAND flash memory device, a plurality of word lines are disposed between a drain select line and a source select line, and a plurality of memory cells are connected to each word line. The string connected between the bit line and the common source line includes a drain select transistor, a plurality of memory cells and a source select transistor. Here, the drain of the drain select transistor is connected to the bit line and the gate is connected to the drain select line. The source of the source select transistor is connected to the common source line and the gate is connected to the drain select line. The plurality of memory cells are connected in series between the drain select transistor and the source select transistor and gates (ie, control gates) are respectively connected to the word lines. Here the memory cells are located on the same column.

During a program operation for storing data, a program voltage is applied to a selected word line among word lines. Some of the memory cells connected to the selected word line are designated as program inhibit cells according to the stored data. The program inhibiting cell is a cell whose threshold voltage should not change even if the program voltage is not applied. The method for preventing the threshold voltage from changing is as follows. The program inhibit voltage is applied to a bit line electrically connected to the program inhibit cell, and the channel region of the program inhibit cell is precharged using the program inhibit voltage. Subsequently, a pass voltage is applied to the word lines and then a program voltage is applied to the selected word line, which is increased by boosting the channel voltage by the pass voltage. As a result, the difference between the program voltage applied to the word line and the boosted channel voltage is small so that the threshold voltage of the program inhibited cell does not change.

In this way, the channel voltage of the program inhibiting cell should be uniformly increased by channel boosting in all word lines, and the boosted channel voltage may vary according to the position of the word line, thereby causing an error. For example:

Memory cells in the first word line adjacent to the source select line or the last word line adjacent to the drain select line are more likely to fail due to a Hot Carrier Injection (HCI) phenomenon during a program operation. . This is a problem that occurs in the case of the memory cells of the first word line adjacent to the source select line or the last word line adjacent to the drain select line due to the high positional probability that hot carriers are generated.

Therefore, in the memory cells of the first word line adjacent to the source select line or the last word line adjacent to the drain select line, it is necessary to reduce the generation of a fail bit due to a hot carrier injection phenomenon.

According to an exemplary embodiment of the present invention, the channel boosting level of a channel region of a program inhibiting cell is changed during a program operation on memory cells of a word line adjacent to a drain select line or a source select line, thereby preventing occurrence of error bits due to hot carrier injection. Can be suppressed and the program disturbance characteristics improved.

A method of operating a semiconductor memory device may include determining whether a selected word line among word lines between a drain select line and a source select line is the drain select line or a first word line adjacent to the source select line. In the case of the first word line, precharging a channel region of a program inhibited cell among the memory cells of the first word line to a first level lower than a second level, and applying a program voltage to the first word line and rest. Applying a pass voltage to word lines to perform a first program operation for storing data in the memory cells, wherein the second level is a second word in which the selected word line excludes the first word line; In the case of a line, the channel region of the program inhibiting cell among the memory cells of the second word line is Characterized in that the level to.

The semiconductor memory device frees a channel region of a program inhibited cell determined according to input data among memory blocks including memory cells connected to a plurality of word lines between a drain select line and a source select line, and memory cells connected to a selected word line. An operating circuit configured to perform a program operation for storing the data in the memory cells of the selected word line, and wherein the selected word line is a first word line adjacent to the drain select line or the source select line; and And a control circuit configured to control the operation circuit to change the precharge level of the channel region of the program inhibiting cell in the case of the second word line except the first word line.

According to an exemplary embodiment of the present invention, the channel boosting level of a channel region of a program inhibiting cell is changed during a program operation on memory cells of a word line adjacent to a drain select line or a source select line, thereby preventing occurrence of an error bit due to a hot carrier injection phenomenon. Can be suppressed and the program disturbance characteristics improved.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.
3 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention.
4A through 4C are circuit diagrams illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.
5 is a timing diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device may include an operation circuit configured to perform a program operation, a read operation, and an erase operation for data input / output of memory cells included in a selected page of a memory array 110 and a memory cell block 110MB. 130 to 170, and a control circuit 120 configured to control the operation circuits 130 to 170. In the case of a NAND flash memory device, the operation circuit includes the voltage supply circuits 130 and 140, the page buffer group 150, the column selection circuit 160, and the input / output circuit 170.

The memory array 110 includes a plurality of memory blocks 110MB. The structure of the memory block will be described in detail as follows.

FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.

Referring to FIG. 2, each memory block includes a plurality of strings ST connected between bit lines BLe0 to BLek and BLo0 to BLok and a common source line CSL. That is, the strings ST are connected to the corresponding bit lines BLe0 to BLek and BLo0 to BLok, respectively, and are commonly connected to the common source line CSL. Each string ST may include a source select transistor SST having a source connected to a common source line CSL, a plurality of memory cells Ce00 to Ce0, and a drain select transistor having a drain connected to a bit line BLe0. DST). The memory cells Ce00 to Ce0 are connected in series between the select transistors SST and DST. The gate of the source select transistor SST is connected to the source select line SSL and the gates of the memory cells Ce00 to Cen0 are connected to the word lines WL0 to WLn respectively. Is connected to a drain select line (DSL).

In the NAND flash memory device, memory cells included in a memory cell block may be divided into physical page units or logical page units. For example, memory cells (Ce00 through Ce0k, Co00 through Co0k) connected to one word line (e.g., WL0) constitute one physical page (PAGE). In addition, even-numbered memory cells Ce00 to Ce0k connected to one word line (e.g., WL0) constitute one even physical page, odd-numbered memory cells Co00 to Co0k constitute one odd physical page . These pages (or even pages and odd pages) are the basic unit of program operation or read operation.

Referring back to FIG. 1, the control circuit 120 may include an internal command signal for controlling the voltage generation circuit 130 for data input / output in response to a command signal CMD input through the input / output circuit 170 from the outside. PB control signals PB_SIGNALS for controlling the page buffers PB0 to PBk included in the CMDi and the page buffer group 150 are output. In addition, the control circuit 120 outputs the row address signal RADD and the column address signal CADD in response to the address signal ADD. The row address signal RADD is output to distinguish the selected memory block from the unselected memory blocks, and the column address signal CADD is used to sequentially select the page buffers PB0 to PBk of the page buffer group 150. Is output. In particular, the control circuit 120 may include the case where the selected word line is the first word line adjacent to the drain select line DSL or the source select line SSL during a program operation for storing data, and the selected word line is the first word line. In the case of the second word line except for, the control circuits 130 to 170 are configured to change the precharge level of the channel region of the program inhibiting cell.

The voltage supply circuits 130 and 140 may operate with the operating voltages (eg, Vpgm, Vpass, Vvfy, Vdsl, Vssl, Vcsl) required for data input / output operations of the memory cells in response to the internal command signal CMDi of the control circuit 120. Is supplied to local lines (eg, DSL, WL0 to WLn, SSL, CSL) of the selected memory cell block. This voltage supply circuit includes a voltage generator circuit 130 and a row decoder 140.

The voltage generation circuit 130 may globalize operating voltages (eg, Vpgm, Vpass, Vvfy, Vdsl, Vssl, Vcsl) required for data input / output operations of the memory cells in response to the internal command signal CMDi of the control circuit 120. Output to lines For example, the voltage generation circuit 130 outputs the program voltage Vpgm to the global line to be connected to the selected local word line during the program operation, and applies the program pass voltage Vpass to the global lines to be connected to the unselected local word lines. The selector outputs the select voltages Vdsl and Vssl to the global select lines to be connected to the local select lines, and outputs the source voltage Vcsl to the common source line CSL.

In particular, when the word line selected for the program operation is the first word line adjacent to the drain select line DSL or the source select line SSL, and when the selected word line is the second word line except the first word line, the program is executed. In order to differently set the level at which the channel region of the forbidden cell is precharged, the voltage generation circuit 130 may select the select voltage to be applied to the drain select line DSL in response to the internal command signal CMDi of the control circuit 120. Vdsl) is changed according to the position of the word line.

In addition, the voltage generation circuit 130 outputs a program verification voltage Vvfy for applying to a selected word line in a program verifying operation, and outputs a program pass voltage Vpass for applying to unselected word lines, and selects the selected word line. The select voltages Vdsl and Vssl for applying to the lines DSL and SSL are output, and the source voltage Vcsl for applying to the common source line CSL is output.

In a program operation of an increment step pulse program (ISPP) method, the voltage generation circuit 130 may raise the program voltage Vpgm in steps. In addition, the voltage generation circuit 130 outputs a higher level pass voltage Vpass during the program operation than during the program verify operation.

In response to the row address signals RADD of the control circuit 120, the row decoder 140 selects a memory block 110MB in which the operating voltages output from the voltage generation circuit 130 as global lines are selected in the memory array 110. Connect the global lines and the local lines DSL, WL0 to WLn, SSL of the selected memory block to be transferred to the local lines DSL, WL0 to WLn, SSL.

The page buffer groups 150 respectively include a plurality of page buffers PB0 to PBk connected to the memory array 110 through bit lines BLe0 to BLek and BLo0 to BLok. The page buffers PB0 to PBk of the page buffer group 150 are bit lines BLe0 to PB0 in response to data input to store data in memory cells in response to the PB control signal PB_SIGNALS of the control circuit 120. In order to selectively precharge the BLek or BLo0 to BLok, or to read data from the memory cells, the voltages of the bit lines BLe0 to BLek or BLo0 to BLok are sensed. In particular, the page buffers PB0 to PBk apply a program inhibit voltage for precharging the channel region of the program inhibit cell to a bit line electrically connected to the program inhibit cell during a program operation. In this case, when the word line selected for the program operation is the first word line adjacent to the drain select line DSL or the source select line SSL, and when the selected word line is the second word line except the first word line, the program is executed. In order to set the level at which the channel region of the inhibit cell is precharged differently, the page buffer may change the program inhibit voltage to be applied to the bit line according to the position of the word line in response to the PB control signals PB_SIGNALS of the control circuit 120. You can change it. That is, the level at which the channel region of the program inhibiting cell is precharged may be adjusted according to the select voltage Vdsl applied to the drain select line by the voltage generation circuit 130 or the program inhibit voltage applied to the bit line by the page buffer. have.

The column selection circuit 160 selects the page buffers PB0 to PBk included in the page buffer group 150 in response to the column address CADD. That is, the column select circuit 160 sequentially transfers data to be stored in the memory cells to the page buffers PB0 to PBk in response to the column address CADD during the program operation. In addition, the page buffers PB0 to PBk are sequentially selected in response to the column address CADD so that data of memory cells latched in the page buffers PB0 to PBk may be output to the outside during the read operation.

The input / output circuit 170 transfers data to the column selection circuit 160 under the control of the control circuit 120 to input data input from the outside into the page buffer group 150 for storage in memory cells during a program operation. do. When the column selection circuit 160 transfers the data transferred from the input / output circuit 170 to the page buffers PB0 to PBk of the page buffer group 150 according to the method described above, the page buffers PB0 to PBk are input. The stored data is stored in an internal latch circuit. In addition, during the read operation, the input / output circuit 170 outputs data transferred from the page buffers PB0 to PBk of the page buffer group 150 through the column select circuit 160 to the outside.

A method of operating a semiconductor memory device according to an exemplary embodiment of the present invention including the above components will be described below. For reference, all operations described below, such as the application operation of the program voltage, the application operation of the program pass voltage, the application operation of the program inhibit voltage, and the precharge operation of the channel region, are performed by the operation circuit under the control of the control circuit.

3 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention. 4A through 4C are circuit diagrams illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention. 5 is a timing diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, in step S310, a first word line is selected for a program operation. In operation S310, data for storing the memory cells connected to the first word line is latched in the page buffers. The program inhibit cell is determined among the memory cells connected to the first word line according to the data latched in the page buffers.

In operation S320, it is checked whether the selected word line is an edge word line, that is, a word line adjacent to the drain select line DSL or the source select line SSL. This checking operation may be performed by sensing a row address. If the selected word line is an edge word line, the process proceeds to step S331. If the selected word line is not an edge word line, the process proceeds to step S333. If it is assumed that the first word line is a word line adjacent to the source select line SSL, the flow proceeds to step S331.

In step S330, a program loop is performed to store data in memory cells of the first word line. When the program loop proceeds in the Increment Step Pulse Program (ISPP) method, the program loop includes a program operation, a program verify operation, and a program voltage change operation. Specifically, it is as follows.

3 and 4A, in step S331, a program operation is performed to increase the threshold voltages of selected memory cells according to data latched in a page buffer. At this time, when '0' data is stored, the threshold voltage of the memory cell (eg, Ce00) is increased, and when '1' data is stored, the threshold voltage of the memory cell (eg, Ce01) is maintained without changing. Since the program voltage is applied to all the memory cells Ce00 and Ce01 connected to the first word line WL0 for the program operation, the threshold voltage of the program inhibit cell Ce01 in which '1' data is stored is prevented from being changed. In order to apply the pass voltage Vpass and the program voltage Vpgm, the channel region of the program inhibiting cell Ce01 must be precharged. In order to precharge the channel region of the program inhibiting cell Ce01, a program inhibit voltage (eg, Vcc) is applied to the bit line BLe1, and a drain select for transferring the program inhibit voltage Vcc to the program inhibit cell Ce01. A select voltage Vdsl1 (for example, 1.8V) higher than the precharge level is applied to the drain select line DSL of the transistor DST1 by the threshold voltage of the drain select transistor DST1 (section 3 in FIG. 5). As a result, the program inhibit voltage Vcc is transferred to the channel region of the program inhibit cell Ce01 through the drain select transistor DST1, and the channel voltage Vpre1 of the program inhibit cell Ce01 is raised to the first level Vdsl1-Vth. To rise). When precharging the channel region of the program inhibiting cell Ce01, all channel regions of the memory cells Ce11 ˜ Ce1 electrically connected to the bit line BLe1 in the string including the program inhibiting cell Ce01 are all at a first level. Precharged to (Vdsl1-Vth).

Meanwhile, a program allowable voltage (eg, 0 V) is applied to the bit line BLe0 of the memory cell Ce00 in which '0' data is stored, and the channel region of the memory cell Ce00 is discharged.

Next, a pass voltage Vpass is applied to the word lines WL0 to WLn (sections 6 to 9 of FIG. 5). As the pass voltage Vpass is applied, the channel voltage rises to the boosting level Vdsl1-Vth + Vboost in the channel region of the program inhibiting cell Ce01 due to capacitive coupling phenomenon. At this time, the drain select transistor DST1 is turned off. In order to surely turn off the drain select transistor DST1, a voltage lower than the select voltage Vdsl may be applied to the drain select line DSL (sections 6 to 9 of FIG. 5). This prevents leakage of channel voltage.

After the channel voltage of the program inhibiting cell Ce01 rises to the boosting level Vdsl1 -Vth + Vboost, the program voltage Vpgm is applied to the selected word line WL0 (sections 7 to 8 of FIG. 5). Since the memory cell Ce00 has a large difference between the channel voltage and the program voltage, electrons are injected into the floating gate to increase the threshold voltage. However, since the program inhibit cell Ce01 has a small difference between the channel voltage and the program voltage, electrons are not injected into the floating gate and the threshold voltage does not change.

In operation S335, a program verify operation is performed to determine whether the threshold voltage of the memory cell Ce00 has risen to a target level and to determine whether the program operation is completed. Since the program verifying operation is well known, a detailed description thereof will be omitted.

If the threshold voltage of the memory cell Ce00 does not rise to the target level, an operation for raising the program voltage by the step voltage is performed in step S337. Then, the program operation S331 and the program verify operation S335 are performed again. The program loop S330 is repeatedly executed until the threshold voltage of the memory cell Ce00 reaches a target level.

If it is determined that the threshold voltage of the memory cell Ce00 has risen to the target level, in step S340, it is checked whether the word line subjected to the program loop is the last word line. If it is not the last word line in the memory block, the next word line is selected in step S350, and steps S320 and S330 are repeated.

3 and 4B, when the word line selected in step S330 is not an edge word line, in step S330, another data is precharged after precharging the channel region of the program inhibited cell to the changed level Vpre2. A program loop is performed to store the memory cells Ce20 and Ce21 of the selected word line WL2. Specifically, it is as follows.

In operation S333, a program operation is performed to increase the threshold voltage of the selected memory cell (eg, Ce20) according to the data latched in the page buffers for storage in the memory cells Ce20 and Ce21 of the word line WL2. do. As in step S331, when the '0' data is stored, the threshold voltage of the memory cell (eg, Ce20) is increased, and when the '1' data is stored, the threshold voltage of the memory cell (eg, Ce21) is changed. Keep it.

In order to precharge the channel region of the program inhibiting cell Ce21, a program inhibit voltage (eg, Vcc) is applied to the bit line BLe1, and a drain select for transferring the program inhibit voltage Vcc to the program inhibit cell Ce21. A select voltage Vdsl2 (for example, 2.3V) higher than the precharge level Vpre2 is applied to the drain select line DSL of the transistor DST1 by the threshold voltage of the drain select transistor DST1. At this time, the precharge level Vpre2 of the channel region of the program inhibiting cell Ce21 is higher than the precharge level Vpre1 of the channel region of the program inhibiting cell Ce01 by a predetermined level (aV, for example, 0.5V). The select voltage Vdsl2 is also applied at a level higher by a predetermined level aV than the select voltage Vdsl1 applied in the previous program operation S331.

Thus, the program inhibit voltage Vcc is transferred to the channel region of the program inhibit cell Ce21 through the drain select transistor DST, and the precharge level Vpre2 of the program inhibit cell Ce21 is changed to the previous first level ( It rises to the 2nd level Vdsl2-Vth higher by the predetermined level aV than Vdsl1-Vth. When precharging the channel region of the program inhibiting cell Ce21, all of the channel regions of the memory cells Ce31 ˜ Ce1 electrically connected to the bit line BLe1 in the string including the program inhibiting cell Ce21 are all at the second level. Precharged to (Vdsl2-Vth).

Meanwhile, a program allowable voltage (eg, 0 V) is applied to the bit line BLe0 of the memory cell Ce20 in which '0' data is stored, and the channel region of the memory cell Ce20 is discharged.

Subsequently, a pass voltage Vpass is applied to the word lines WL0 to WLn. As the pass voltage Vpass is applied, the channel voltage increases to the boosting level Vdsl2-Vth + Vboost in the channel region of the program inhibiting cell Ce21 due to the capacitive coupling phenomenon. At this time, the drain select transistor DST1 is turned off.

After the channel voltage of the program inhibiting cell Ce21 rises to the second level Vdsl2-Vth + Vboost by channel boosting, the program voltage Vpgm is applied to the selected word line WL2. Since the memory cell Ce20 has a large difference between the channel voltage and the program voltage, electrons are injected into the floating gate to increase the threshold voltage. However, since the program inhibit cell Ce21 has a small difference between the channel voltage and the program voltage, electrons are not injected into the floating gate and the threshold voltage does not change.

Since the program inhibit cell Ce21 is farther from the drain select line DSL or the source select line SSL than the program inhibit cell Ce01, less hot carrier injection occurs in the program inhibit cell Ce21. Therefore, even if the channel voltage is boosted after precharging the channel region of the program inhibiting cell Ce21 higher than the channel region of the program inhibiting cell Ce01, the possibility of hot carrier injection is not large. As a result, for the program inhibited cells Ce01 that are vulnerable to the hot carrier injection phenomenon according to the positions of the program inhibiting cells Ce01 and Ce21, the occurrence of the hot carrier injection phenomenon is suppressed to suppress the occurrence of error bits and to improve the program disturb characteristics. can do. In addition, for the program inhibited cells Ce21 that are not relatively vulnerable to the hot carrier injection phenomenon, sufficient channel voltage can be ensured regardless of the hot carrier injection phenomenon, thereby suppressing occurrence of error bits due to FN tunneling and improving program disturb characteristics. can do.

Thereafter, in operation S335, a program verify operation is performed to check whether the threshold voltage of the memory cell Ce20 has risen to a target level. When the threshold voltage is lower than the target level, in step S337, the level of the program voltage Vpgm is increased by the step voltage, and steps S333 and S335 are performed again. Similarly, the program loop S330 is repeatedly executed within a predetermined number of times until the threshold voltage of the memory cell Ce20 rises to the target level.

In step S340, it is checked whether the word line subjected to the program loop is the last word line. If it is not the last word line in the memory block, the next word line is selected in step S350, and steps S320 and S330 are repeated.

3 and 4C, when the last word line WLn is selected in step S340, the above-described steps S333, 335, and 337 are repeated. Here, it is assumed that the last word line WLn is a word line adjacent to the drain select line DSL.

Steps S333, 335, and 337 are performed, and when the word line WLn subjected to the program loop is identified as the last word line in step S340, the operation ends.

As described above, the channel boosting level of the channel region of the program inhibiting cell may be changed during a program operation on the memory cells of the word line adjacent to the drain select line DSL or the source select line SSL. It is possible to suppress the occurrence of error bits and to improve the program disturbance characteristic.

The embodiments of the present invention described above are not only implemented by the apparatus and method but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, The embodiments can be easily implemented by those skilled in the art from the description of the embodiments described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

110: memory array 110 MB: memory block
ST: string PAGE0: page
120: control circuit 130: voltage generating circuit
140: row decoder 150: page buffer group
PB0 to PBk: Page buffer 160: Column selection circuit
170: Input / output circuit

Claims

Determining whether a selected word line among word lines between a drain select line and a source select line is the drain select line or a first word line adjacent to the source select line;
Precharging a channel region of a program inhibited cell among memory cells of the first word line to a first level lower than a second level when the selected word line is the first word line; And
Applying a program voltage to the first word line and applying a pass voltage to the remaining word lines to perform a first program operation for storing data in the memory cells;
And wherein the second level is a level for precharging a channel region of a program inhibited cell among memory cells of the second word line when the selected word line is a second word line except the first word line. How the memory device works.

The method of claim 1, further comprising: precharging a channel region of a program inhibited cell among memory cells of the second word line to the second level when the selected word line is the second word line; And
And applying a program voltage to the second word line and applying a pass voltage to the remaining word lines to perform a second program operation for storing data in the second memory cells. .

The method of claim 1, wherein precharging the channel region to the first level.
A first select voltage higher than a first level by a threshold voltage to the drain select line of a drain select transistor configured to apply a program inhibit voltage to the bit line connected to the program inhibit cell and to transfer the program inhibit voltage to the program inhibit cell; The operating method of the semiconductor memory device is applied.

The method of claim 1,
When precharging the channel region to the first level, a semiconductor memory in which channel regions of memory cells electrically connected to a bit line are precharged to the first level in a string including a program inhibiting cell among the first memory cells. How the device works.

The method of claim 2, wherein in the precharging of the channel region to the second level,
A second select voltage higher by a threshold voltage than the second level to the drain select line of the drain select transistor that applies a program inhibit voltage to the bit line connected to the program inhibit cell and transfers the program inhibit voltage to the program inhibit cell; The operating method of the semiconductor memory device is applied.

3. The method of claim 2,
When precharging the channel region to the second level, a semiconductor memory in which channel regions of memory cells electrically connected to a bit line are precharged to the second level in a string including a program inhibited cell among the second memory cells. How the device works.

A memory block including memory cells connected to the plurality of word lines between the drain select line and the source select line;
An operation circuit configured to precharge a channel region of a program inhibiting cell determined according to input data among memory cells connected to a selected word line, and to perform a program operation for storing the data in the memory cells of the selected word line; And
When the selected word line is the first word line adjacent to the drain select line or the source select line and the second word line except the first word line, the precharge level of the channel region of the program inhibiting cell is changed. And a control circuit configured to control the operation circuit to change.

The method of claim 7, wherein
In order to precharge the channel region, the operation circuit applies a program inhibit voltage to a bit line connected to the program inhibit cell and applies the program inhibit voltage to the drain select line of a drain select transistor that transfers the program inhibit voltage to the program inhibit cell. And apply a select voltage higher by a threshold voltage than a target precharge level of the channel region.

The method of claim 7, wherein
And when the channel region is precharged, channel regions of memory cells electrically connected to bit lines among memory cells included in the same string together with the program inhibiting cell are precharged by the operation circuit.

The method of claim 7, wherein
When the selected word line is the first word line adjacent to the drain select line or the source select line, the precharge level of the channel region of the program inhibited cell is lower than that of the second word line except for the first word line. And the control circuit controls the operation circuit.