KR20130070249A - Semiconductor memory and memory system - Google Patents

Semiconductor memory and memory system Download PDF

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Publication number
KR20130070249A
KR20130070249A KR1020110137482A KR20110137482A KR20130070249A KR 20130070249 A KR20130070249 A KR 20130070249A KR 1020110137482 A KR1020110137482 A KR 1020110137482A KR 20110137482 A KR20110137482 A KR 20110137482A KR 20130070249 A KR20130070249 A KR 20130070249A
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KR
South Korea
Prior art keywords
memory
memory module
direct access
package substrate
external terminals
Prior art date
Application number
KR1020110137482A
Other languages
Korean (ko)
Inventor
양형균
이형동
권용기
문영석
김성욱
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110137482A priority Critical patent/KR20130070249A/en
Publication of KR20130070249A publication Critical patent/KR20130070249A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: A system integrated circuit is provided to increase system reliability by remarkably improving the error detection range of a semiconductor memory. CONSTITUTION: Multiple external terminals(700) are connected to the bottom of a package substrate(600). A memory module(200) is mounted at the top of the package substrate. A memory controller(300) is connected with the memory module through an input/output interface. A direct access line(900) performs various signal communications with the memory module in direct access test mode. An interposer(500) is prepared for an electrical interface between a signal bus(400) and the package substrate. [Reference numerals] (230) Test block

Description

System Integrated Circuits {SEMICONDUCTOR MEMORY AND MEMORY SYSTEM}

The present invention relates to semiconductor circuits, and more particularly to system integrated circuits.

A system integrated circuit according to the prior art may be a type in which a system such as a memory controller for controlling a semiconductor memory such as a semiconductor memory and a central processing unit (CPU) or a graphics processing unit (GPU) may be included in one package. This is called a SIP (System In Package).

In such a SIP, an input / output interface (IO) of a semiconductor memory is not implemented outside the package.

Therefore, the BIST (Built-in Self Test) is installed in the semiconductor memory module so that some tests can be performed among various tests of the semiconductor memory.

However, in case of BIST, since it contains only the preset test pattern which cannot be modified after packaging, if there is a problem in BIST itself or an error that BIST cannot detect, it cannot solve the semiconductor memory as well as system error. There is a problem that can be.

Embodiments of the present invention seek to provide a system integrated circuit capable of improving the error detection range.

An embodiment of the present invention is a system integrated circuit in which a semiconductor memory and a memory controller configured to control the semiconductor memory are included in one package, wherein some of the external terminals of the package and a communication channel of the semiconductor memory are directly connected. do.

Embodiment of the present invention is a package substrate; A plurality of external terminals connected to a lower portion of the package substrate; A memory module mounted on the package substrate; A memory controller mounted on the package substrate, connected to the memory module through an input / output interface, and configured to communicate with an external device through the plurality of external terminals; And a direct access line for directly connecting a portion of the communication channel of the memory module to the plurality of external terminals.

Embodiments of the present invention can greatly improve the error detection range of the semiconductor memory, thereby improving system reliability.

1 is a cross-sectional view of a system integrated circuit 100 according to an embodiment of the present invention;
FIG. 2 is a block diagram showing a configuration example of an interface circuit for the direct access test mode of FIG. 1; FIG.
3 is a block diagram showing an example of the configuration of an interface circuit for the direct access test mode of FIG.
4 is a block diagram showing the internal configuration of the test block 230 of FIG.
5 is a flowchart illustrating a system integrated circuit test method according to an exemplary embodiment of the present invention.

An embodiment of the present invention is to allow direct testing of a memory without going through a memory controller, such as built-in self test (BIST), which is a direct access test mode. Mode). Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, a system integrated circuit 100 according to an exemplary embodiment may include a memory module 200, a memory controller 300, a signal bus 400, an interposer 500, and a package. A substrate 600, a package external terminal 700, a test access port (TAP) 800, and a direct access line 900 are included.

The memory module 200 is formed by stacking a plurality of slices 210 and 220.

The plurality of slices 210 are stacked memories.

The slice 220 is a logic circuit block, and may include a test block 230 and an input output interface (IO).

As described later, the test block 230 is a circuit block for performing a BIST.

The plurality of slices 210 and 220 may be connected through vias, for example, through silicon vias (TSVs). In this case, the TSV may be used for communication of the plurality of stacked slices 210 and 220.

The memory controller 300 may be a central processing unit (CPU) or a graphic processing unit (GPU), and may include IO for communicating with the IO of the memory module.

The interposer 500 is configured for electrical interface between the signal bus 400 and the package substrate 600.

The package external terminal 700 may be a lead pin array 700.

The test access port 800 is configured for input / output of various signals for BIST, that is, clock, reset, and data.

The direct access line 900 is a signal line for performing various signal communication with the memory module 200 in the direct access test mode according to an embodiment of the present invention, and is connected to predetermined read pins in the lead pin array 700. .

Meanwhile, in the above-described contact access test mode, the channels of each of the plurality of slices 210 of FIG. 1 are directly connected to the lead pin array 700 through the direct access line 900.

Therefore, the embodiment of the present invention allows the channels of the plurality of slices 210 to be shared so as to increase the pin usage efficiency of the lead pin array 700. The method will be described with reference to FIGS. 2 and 3. do.

First, as shown in FIG. 2, when the plurality of slices 210 are slices 1 to 4, four channels and total channels may be 16 for each slice.

In the embodiment of the present invention, four channels of each of slices 1 to 4 are input to the multiplexer 211.

In addition, the multiplexer 211 selects any one of four channels among the slices 1 to 4 by using the channel selection signals CS <1: 0> to connect to the direct access line 900. In this way, the channels of the slices 1 to 4 may be shared.

In this case, the channel selection signals CS <1: 0> may also be input through the direct access line 900.

In addition, referring to FIG. 3, four channels of each of the slices 1 to 4 are commonly connected to the direct access line 900, and a channel selection signal CS <0:15> is input to each of the slices 1 to 4. It is also possible.

In this case, the channel selection signals CS <0:15> can be input only in the direct access test mode.

As a result, only a slice corresponding to the channel selection signal CS <0:15> may directly communicate with external test equipment through the direct access line 900.

As shown in FIG. 4, the test block 230 includes a BIST circuit 231 and a TAP controller 232 for controlling communication of the BIST circuit 231 with the TAP 800.

The TAP controller 232 may include a finite state machine (FSM).

Hereinafter, a test and error analysis method of a system integrated circuit according to an exemplary embodiment of the present invention will be described with reference to FIG. 5.

First, a memory design including a BIST circuit is made (S11).

Then, the memory is stacked and SIP is manufactured by connecting the stacked memory with a memory controller such as a CPU or a GPU (S12).

Subsequently, a memory test, that is, BIST, is performed in the manufactured SIP (S13).

If it is determined that the BIST result (S13), and normal (PASS), the various system application programs are tested (S14).

On the other hand, if it is determined that the BIST result (S13), the error (FAIL), the repair and confirmation procedure is performed (S15).

If it is determined as normal (PASS) in the repair and confirmation procedure (S15), various system applications are tested (S14).

On the other hand, if it is determined that the error (FAIL) in the repair and confirmation procedure (S15), a direct access test (DA TEST) is performed (S16).

In this case, referring to FIG. 1, the direct access test S16 is performed by connecting a predetermined lead pin and test equipment in the lead pin array 700.

That is, the test equipment sends and receives commands, addresses, clocks, and data through preset lead pins, and tests the stacked memories 210.

The failure analysis (FA) is performed according to the result of performing the direct access test (S16) as described above (S17).

Accordingly, the error detection range of the system integrated circuit may be improved by additionally detecting an error that is not detected by the BIST through the error analysis S17 and reflecting the error in the memory design step S11.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (6)

A system integrated circuit comprising a semiconductor memory and a memory controller configured to control the semiconductor memory in one package,
A part of the external terminals of the package and a communication channel of the semiconductor memory are directly connected. The method of claim 1,
And the semiconductor memory and the memory controller are connected through each other's input / output interface, and the memory controller is connected to the external terminals through a signal bus. A package substrate;
A plurality of external terminals connected to a lower portion of the package substrate;
A memory module mounted on the package substrate;
A memory controller mounted on the package substrate, connected to the memory module through an input / output interface, and configured to communicate with an external device through the plurality of external terminals; And
And a direct access line for directly connecting a communication channel of the memory module to a part of the plurality of external terminals. The method of claim 3, wherein
The memory module
A plurality of stacked semiconductor memories, and
And a multiplexer configured to connect one of the communication channels of each of the plurality of semiconductor memories with the direct access line in response to a channel select signal. The method of claim 3, wherein
And a test access port (TAP) connected to the plurality of external terminals. The method of claim 5, wherein
The memory module
A plurality of stacked semiconductor memories,
A multiplexer configured to connect one of the communication channels of each of the plurality of semiconductor memories with the direct access line in response to a channel select signal;
A built-in self test (BIST) circuit for self-testing the plurality of semiconductor memories, and
And a TAP controller for controlling communication of the BIST circuit and the TAP.
KR1020110137482A 2011-12-19 2011-12-19 Semiconductor memory and memory system KR20130070249A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160134411A (en) * 2015-05-13 2016-11-23 삼성전자주식회사 Semiconductor Memory Device For De-concentrating Refresh Commands and System Including The Same
KR20180011991A (en) * 2016-07-26 2018-02-05 삼성전자주식회사 Stacked memory device, system including the same and associated method
KR20190123595A (en) * 2018-04-24 2019-11-01 삼성전자주식회사 Interposer device and semiconductor test system including the same
US10692583B2 (en) 2018-05-17 2020-06-23 Samsung Electronics Co., Ltd. Multi-channel package, and test apparatus and test method of testing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160134411A (en) * 2015-05-13 2016-11-23 삼성전자주식회사 Semiconductor Memory Device For De-concentrating Refresh Commands and System Including The Same
KR20180011991A (en) * 2016-07-26 2018-02-05 삼성전자주식회사 Stacked memory device, system including the same and associated method
KR20190123595A (en) * 2018-04-24 2019-11-01 삼성전자주식회사 Interposer device and semiconductor test system including the same
US10692583B2 (en) 2018-05-17 2020-06-23 Samsung Electronics Co., Ltd. Multi-channel package, and test apparatus and test method of testing the same

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