KR20130045171A - Receiver circuit and system including p-type sense amplifier - Google Patents

Abstract

PURPOSE: A receiving circuit including a P-type sense amplifier and a system are provided to improve the sensitivity of an input signal using a plurality of reference voltages. CONSTITUTION: A receiving circuit includes a switching PMOS transistor, an input unit(130), and an amplifying unit(150). The switching PMOS transistor applies a power voltage to a power node in response to a clock signal. The input unit is connected to the power node and receives power. The input unit generates a first sensing signal corresponding to an input signal and a second sensing signal corresponding to a reference voltage in response to the input signal and the reference voltage. The amplifying unit generates a first output signal and a second output signal by amplifying the first sensing signal and the second sensing signal.

Description

Receiver circuit and system including p-type sense amplifier

The present invention relates to an integrated circuit for signal transmission, and more particularly to a receiving circuit and system comprising a P-type sense amplifier.

Conventional receiving circuits generally include an n-type sense amplifier that senses and amplifies an input signal using an n-channel metal oxide semiconductor (NMOS) transistor. However, the N-type sense amplifier has a problem in that the sensing sensitivity may be lowered according to the pattern of the input signal, and in the worst case, the sensing operation may not be performed at all.

One object of the present invention for solving the above problems is to provide a receiving circuit that can improve the sensing sensitivity of the input signal small swing in the vicinity of the ground voltage.

It is another object of the present invention to provide a system including a transmission circuit for transmitting an input signal that is small swing near a ground voltage and a receiving circuit that can improve the sensing sensitivity of the input signal.

In order to achieve the above object, the receiving circuit according to the embodiments of the present invention includes a switching PMOS transistor, an input unit and an amplifier.

The switching PMOS transistor applies a power supply voltage to a power supply node in response to a clock signal. The input unit is connected to the power node to receive power, and generates a first sensing signal corresponding to the input signal and a second sensing signal corresponding to the reference voltage in response to an input signal and at least one reference voltage. The amplifying unit amplifies the first sensing signal and the second sensing signal to generate a first output signal and a second output signal.

The receiving circuit may further include a ground termination resistor connected between a receiving node receiving the input signal and a ground voltage. The input signal may be a signal swinging between a low voltage level corresponding to the ground voltage and a high voltage level smaller than the power supply voltage.

The input unit may be connected between the power node and a first node generating the first sensing signal, and an input PMOS transistor to which the input signal is applied to a gate, and the power node and the second sensing signal to generate the second sensing signal. The reference PMOS transistor may be connected between two nodes, and the reference PMOS transistor having an average voltage level of the low voltage level and the high voltage level of the input signal may be applied to a gate.

The at least one reference voltage may include a plurality of reference voltages having different voltage levels.

The at least one reference voltage may include a first reference voltage greater than the average voltage level of the low voltage level and the high voltage level of the input signal and a second reference voltage less than the average voltage level.

The input unit generates the first sensing signal and the second sensing signal based on the input signal and the first reference voltage when the input signal has the low voltage level, and the input signal is the high voltage. In the case of having a level, the first sensing signal and the second sensing signal may be generated based on the input signal and the second reference voltage.

The at least one reference voltage may include a first reference voltage having the high voltage level of the input signal and a second reference voltage having the low voltage level of the input signal.

The input unit is connected between the power node and a first node generating the first sensing signal, and the first input PMOS transistor to which the input signal is applied to a gate generates the power node and the second sensing signal. A first reference PMOS transistor connected between a second node and a first reference voltage applied to a gate; a second input PMOS connected between the power node and the first node and the input signal applied to a gate And a second reference PMOS transistor connected between the transistor, the power node, and the second node, and wherein the second reference voltage is applied to a gate.

The amplifier unit is connected between the power supply voltage and the ground node, and the ground voltage in response to a latch unit inverted clock signal including a latch node and an inverted latch node that respectively generate the first output signal and the second output signal. Switching NMOS transistor for applying a voltage to the ground node; a first NMOS transistor connected between the first node receiving the first sensing signal and the ground voltage and the clock signal applied to a gate; A second NMOS transistor connected between a second node receiving a sensing signal and the ground voltage, a second NMOS transistor to which the clock signal is applied to a gate, connected between the power supply voltage and the latch node, and the first sensing signal to a gate A second sensing signal connected between the first PMOS transistor and the power supply voltage and the inversion latch node It may include a second PMOS transistor applied to the gate.

The amplifier may be connected between a first node receiving the first sensing signal, a second node receiving the second sensing signal, and the ground voltage, and generate the first output signal and the second output signal, respectively. A latch unit including a latch node and an inverted latch node connected between the latch node and the ground voltage, and between the first NMOS transistor to which the clock signal is applied to a gate and the inverted latch node and the ground voltage. The clock signal may include a second NMOS transistor to which the clock signal is applied to a gate.

The receiving circuit may further include a rear end amplifier configured to amplify the first output signal and the second output signal to generate a third output signal that swings between the power supply voltage and the ground voltage.

In order to achieve the above another object, a system according to embodiments of the present invention includes a transmitting circuit including a transmitting driver for driving a transmitting node in response to a pull-up signal and a pull-down signal, and a receiving node connected to the transmitting node by a transmission line. It includes a receiving circuit for receiving an input signal through.

The receiving circuit is a switching PMOS transistor that applies a power supply voltage to a power supply node in response to a clock signal, the power supply being connected to the power supply node and receiving power, the input signal in response to the input signal and at least one reference voltage. An input unit including PMOS transistors generating a first sensing signal corresponding to the signal and a second sensing signal corresponding to the reference voltage, and amplifying the first sensing signal and the second sensing signal to amplify the first output signal and the first sensing signal; And an amplifier for generating two output signals.

The receiving circuit may further include a ground termination resistor connected between the receiving node and a ground voltage. The input signal may be a signal swinging between a low voltage level corresponding to the ground voltage and a high voltage level smaller than the power supply voltage.

The receiving circuit further includes a reference voltage generator for generating a first reference voltage greater than an average voltage level of the low voltage level and the high voltage level and a second reference voltage less than the average voltage level based on the input signal. can do.

The transmission circuit has the same configuration as that of the transmission driver, and has the same configuration as the first reference driver and the transmission driver for providing a first reference voltage having the high voltage level of the input signal to the reception circuit. The apparatus may further include a second reference driver configured to provide a second reference voltage having the low voltage level of the input signal to a receiving circuit.

Receiving circuits and systems according to embodiments of the present invention may improve sensing sensitivity of an input signal that is small swing near a ground voltage using a p-type sense amplifier.

In the embodiments of the present invention, the receiving circuit and the system may further improve the sensing sensitivity of the input signal by using the plurality of reference voltages.

1 is a diagram illustrating a receiving circuit according to embodiments of the present invention.
2 is a diagram illustrating a system according to embodiments of the present invention.
3 is a diagram illustrating a pull-up operation of a transmission driver included in the system of FIG. 2.
4 is a diagram illustrating a pull-down operation of a transmission driver included in the system of FIG. 2.
FIG. 5 is a diagram illustrating a voltage level of an input signal received by a receiving circuit included in the system of FIG. 2.
6 is a circuit diagram illustrating an example of an amplifier included in the receiver circuit of FIG. 1.
7 is a diagram illustrating a receiving circuit according to embodiments of the present invention.
8 illustrates an operation of a receiving circuit according to embodiments of the present invention.
9 is a circuit diagram illustrating another example of an amplifier included in the receiver circuit of FIG. 1.
10 illustrates a p-type sense amplifier according to embodiments of the present invention.
11 illustrates an operation of a receiver circuit according to embodiments of the present invention.
12 illustrates a sensing margin of a receiving circuit according to embodiments of the present invention.
13 and 14 are diagrams illustrating a system for performing bidirectional communication according to embodiments of the present invention.
15 illustrates a multi-channel system according to embodiments of the present invention.
16 and 17 illustrate systems for providing a plurality of reference voltages according to embodiments of the present invention.
18 is a diagram illustrating operation of the system of FIG. 17.
19 is a diagram illustrating a system for performing another DL transmission in embodiments of the present invention.
20 and 21 are diagrams illustrating a semiconductor package including a semiconductor memory system according to example embodiments.
22 is a block diagram illustrating an example in which a system according to embodiments of the present disclosure is applied to an electronic device.
23 is a block diagram showing an example of an interface used in the electronic apparatus of Fig.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected or connected to that other component, but it may be understood that other components may be present in the middle. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions describing the relationship between components, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a diagram illustrating a receiving circuit according to embodiments of the present invention.

Referring to FIG. 1, the receiving circuit RX includes an P-type sense amplifier 100. The P-type sense amplifier 100 may include a switching unit 110, an input unit 130, and an amplifier 150.

The switching unit 110 may include a p-channel metal oxide semiconductor (PMOS) transistor (PMS). The switching PMOS transistor PMS applies the power supply voltage VDDQ to the power supply node NP in response to the clock signal CLK. The switching PMOS transistor PMS is turned off during the first half cycle period in which the clock signal CLK is logic high to float the power supply node NP, and the clock signal CLK is logic low. During the second half period, which is logic low, the signal is turned on to apply the power supply voltage VDDQ to the power supply node NP. Therefore, the P-type sense amplifier 100 repeats the sensing operation during the first half period and the floating operation during the second half period.

The input unit 130 is connected to the power supply node NP to receive power through the switching PMOS transistor PMS, and to the input signal DIN in response to the input signal DIN and at least one reference voltage VREF. The PMOS transistors PMI and PMR may generate the second sensing signal DIB corresponding to the corresponding first sensing signal DI and the reference voltage VREF.

The amplifier 150 amplifies the first sensing signal DI and the second sensing signal DIB to generate a first output signal Q and a second output signal QB.

The receiving circuit RX may further include a ground termination resistor 200 connected between the receiving node NR receiving the input signal DIN and the ground voltage VSSQ. The ground termination resistor unit 200 may include at least one termination resistor Rt. In this case, as described below with reference to FIG. 5, the input signal DIN swings between a low voltage level VOL corresponding to the ground voltage VSSQ and a high voltage level VOH smaller than the power supply voltage VDDQ. It may be a signal.

In an embodiment, as illustrated in FIG. 1, the input unit 130 may generate a second sensing signal DIB based on one reference voltage VREF. In another embodiment, as illustrated in FIG. 10. As such, the input unit 130a may generate the second sensing signal DIB based on the plurality of reference voltages VREF1 and VREF2.

When generating the second sensing signal DIB based on one reference voltage VREF, the input unit 130 may include an input PMOS transistor PMI and a reference PMOS transistor PMR.

The input PMOS transistor PMI is connected between the power supply node NP and the first node N1 generating the first sensing signal DI, and the input signal DIN is applied to the gate. The reference PMOS transistor PMR is connected between the power supply node NP and the second node N2 generating the second sensing signal DIB, and the reference voltage VREF is applied to the gate. In this case, the reference voltage VREF may have a low voltage level VOL of the input signal DIN and an average voltage level VA of the high voltage level VOH.

2 is a diagram illustrating a system according to embodiments of the present invention.

Referring to FIG. 2, the system 10 includes a transmitting circuit TX and a receiving circuit RX connected via a transmission line TL. The transmitting circuit TX and the receiving circuit RX may be included in different devices, respectively, and may be integrated in different chips. The transmission line TL may be implemented with any conductive line and may be included in the bus system. For example, the transmission line TL may be formed on or in the surface of a printed circuit board (PCB).

The transmission circuit TX includes a transmission driver 350 that drives the transmission node TX in response to the pull-up signal PU and the pull-down signal PD. The transmission circuit TX may further include a predriver PREDR 310, and the predriver 310 outputs a pull-up signal PU and a pull-down signal PD corresponding to the transmission signal DT. The pull-up signal PU and the pull-down signal PD are signals that complementarily transition between a logic high level and a logic low level according to the transmission signal DT.

The receiving circuit RX receives the input signal DIN through the receiving node NR connected to the transmitting node NT and the transmission line TL. As described above with reference to FIG. 1, the receiving circuit RX may include a P-type sense amplifier 100 and a ground termination resistor 200. The P-type sense amplifier 100 may include a switching unit 110, an input unit 130, and an amplifier 150. The switching unit 110 may include a switching PMOS transistor (PMS). The switching PMOS transistor PMS applies the power supply voltage VDDQ to the power supply node NP in response to the clock signal CLK. The input unit 130 is connected to the power supply node NP to receive power through the switching PMOS transistor PMS, and to the input signal DIN in response to the input signal DIN and at least one reference voltage VREF. The PMOS transistors PMI and PMR may generate the second sensing signal DIB corresponding to the corresponding first sensing signal DI and the reference voltage VREF. The amplifier 150 amplifies the first sensing signal DI and the second sensing signal DIB to generate a first output signal Q and a second output signal QB.

As shown in FIG. 2, the transmission driver 350 may include a pull-up NMOS transistor NMU and a pull-down NMOS transistor NMD coupled between a power supply voltage VDDQ and a ground voltage VSSQ. have. The power supply voltage VDDQ and the ground voltage VSSQ of the transmitting circuit TX may be the same as or different from those of the receiving circuit RX.

Typical transmit drivers include PMOS transistors used as pull-up drivers and NMOS transistors used as pull-down drivers. The carrier mobility of the PMOS transistor, that is, the hole mobility, is smaller than the carrier mobility of the NMOS transistor, that is, the electron mobility, so that the PMOS transistor is an NMOS transistor. In comparison, the operating speed is small and the area is increased.

Therefore, as shown in FIG. 2, the pull-up driver of the transmission driver 350 may be implemented by the NMOS transistor NMU, thereby reducing the area of the transmission circuit TX and increasing the operation speed. When the pull-up driver is implemented as an NMOS transistor, the transmit driver 350 may operate at a high frequency because the electron mobility of the NMOS transistor is larger than the hole mobility of the PMOS transistor. have.

3 is a diagram illustrating a pull-up operation of a transmission driver included in the system of FIG. 2, FIG. 4 is a diagram illustrating a pull-down operation of a transmission driver included in the system of FIG. 2, and FIG. 5 is included in the system of FIG. 2. It is a figure which shows the voltage level of the input signal which a receiving circuit receives.

3 and 5, in the pull-up operation, the pull-up NMOS transistor NMU is turned on in response to a logic high-level pull-up signal PU, and the pull-down NMOS transistor NMD is turned on at a logic low level pull-down signal PD. In response to the turn off, the voltage of the transmitting node NT is pulled up. The maximum output voltage of the transmit driver 350 at the transmit node NT is limited to VDDQ-Vth. Where Vth is the threshold voltage of the pull-up NMOS transistor (NMU). In the pull-up operation, the pull-up NMOS transistor performs a function of a current source. At this time, the pull-up current Ipu flowing through the pull-up NMOS transistor NMU is determined according to the difference of (VDDQ-VOH) as shown in Equation (1).

[Equation 1]

Ipu = k1 * (VDDQ-VOH) ^r1 => k1 * (Vth) ^r1

Where k1 is a constant and r1 may be a real number between 1 and 2. The pullup current Ipu converges to k1 * (Vth) ^r1 as the high voltage level VOH rises. The voltage level of the receiving node NR of the receiving circuit RX, that is, the high voltage level VOH of the input signal DIN is applied to the pull-up current Ipu and the termination resistor Rt flowing through the pull-up NMOS transistor NMU. Can be determined accordingly. Increasing at least one of the pull-up current Ipu and the termination resistor Rt increases the high voltage level VOH of the receiving node NR of the receiving circuit RX. The amount of pull-up current Ipu and / or the resistance value of the termination resistor Rt may be appropriately determined according to the signal integrity characteristics of the data on the channel TL.

Since the amount of pull-up current Ipu may change according to changes in process, voltage, and / or temperature, the current is controlled by adjusting the width of the pull-up NMOS transistor NMU. A suitable value of (Ipu) can be determined.

4 and 5, in the pull-down operation, the pull-up NMOS transistor NMU is turned off in response to the logic low-level pull-up signal PU, and the pull-down NMOS transistor NMD is turned off at a logic-high level pull-down signal ( It is turned on in response to PD) to pull down the voltage of the transmitting node NT.

When the pull-down NMOS transistor NMD is turned on, the termination resistance current Irt is sinked to the ground voltage VSSQ through the termination resistor Rt, and at the same time, the pull-down current Ipd is pull-down NMOS transistor NMD. Through the ground voltage VSSQ. As a result, the voltage at the receiving node NR converges to the ground voltage VSSQ. At this time, the pull-down current Ipd flowing through the pull-down NMOS transistor NMD is the same as Equation 2 and converges to zero while the low voltage level VOL of the input signal DIN decreases.

&Quot; (2) "

Ipd = k2 * (VOL-VSSQ) ^r2 => 0

Where k2 is a constant and r2 may be a real number between 1 and 2. When the low voltage level VOL is smaller than the threshold voltage Vth of the pull-down NMOS transistor NMD, the pull-down current Ipd becomes 0, but the termination resistor current Irt causes the voltage at the receiving node NR to be terminal. Converges to the ground voltage (VSSQ).

The reference voltage VREF may have a high voltage level VOH of the input signal DIN and an average voltage level VA of the low voltage level VOL.

6 is a circuit diagram illustrating an example of an amplifier included in the receiver circuit of FIG. 1.

Referring to FIG. 6, the amplifier 150a may include a pull-down unit 151, a voltage-current converter 152, a latch unit 153, and a switching unit 154.

The latch unit 153 is connected between the power supply voltage VDDQ and the ground node NG, and generates a latch node NQ and an inverted latch node that respectively generate a first output signal Q and a second output signal QB. (NQB). The latch unit 153 may include two inverters formed of PMOS transistors PM3 and PM4 and n-channel metal oxide semiconductor (NMOS) transistors NM3 and NM4. The output can be implemented in a cross-coupled form.

The switching unit 154 may include a switching NMOS transistor (NMS). The switching NMOS transistor NMS applies the ground voltage VSSQ to the ground node NG in response to the inverted clock signal CLKB. The switching NMOS transistor NMS is turned off during the first half cycle period in which the inverted clock signal CLKB is logic low to float the ground node NG, and the inverted clock signal CLKB is logic high. It is turned on for two half cycles to apply the ground voltage VSSQ to the ground node NG. Therefore, the P-type sense amplifier 100 repeats the sensing operation during the first half period and the floating operation during the second half period.

The pull-down unit 151 may include a first NMOS transistor NM1 and a second NMOS transistor NM2. The first NMOS transistor NM1 is connected between the first node N1 receiving the first sensing signal DI and the ground voltage VSSQ, and a clock signal CLK is applied to the gate. The second NMOS transistor NM2 is connected between the second node N2 receiving the second sensing signal DIB and the ground voltage VSSQ, and a clock signal CLK is applied to the gate.

The voltage-current converter 152 may include a first PMOS transistor PM1 and a second PMOS transistor PM2. The first PMOS transistor PM1 is connected between the power supply voltage VDDQ and the latch node Q, and the first sensing signal DI is applied to the gate. The first PMOS transistor PM2 is connected between the power supply voltage VDDQ and the inverting latch node QB, and the second sensing signal DIB is applied to the gate. The voltage-current converter 152 applies currents corresponding to the first sensing signal DI and the second sensing signal DIB to the latch node Q and the inverted latch node QB, respectively.

7 is a diagram illustrating a receiving circuit according to embodiments of the present invention.

Referring to FIG. 7, the reception circuit RX includes an P-type sense amplifier 100 and a rear stage amplifier 170. The P-type sense amplifier 100 may include a switching unit 110, an input unit 130, and an amplifier 150, as described with reference to FIG. 1.

The rear end amplifier 170 amplifies the first output signal Q and the second output signal QB from the P-type sense amplifier 100 to full swing between the power supply voltage VDDQ and the ground voltage VSSQ. The third output signal OUT is generated. As the frequency of the clock signal CLK increases, the first output signal Q and the second output signal QB may be incompletely swinging signals as shown in FIG. 8. In this case, the rear end amplifier 170 further amplifies the first output signal Q and the second output signal QB, which are incompletely swinging, and performs a third full swing between the power supply voltage VDDQ and the ground voltage VSSQ. Generate the output signal OUT.

The rear stage amplifier 170 may include a driving unit 171, a latch unit 172, and an output unit 173. The driver 171 may include the transistors NM1, NM2, PM1, and PM2 and the MOS capacitor MC coupled as shown in FIG. 7. The latch unit 172 may include two inverters INV1 and INV2 having an output and an input cross-coupled with each other, and the node voltages O1 and O2 of the latch unit 172 are complementary voltage levels. The output unit 173 may be implemented as an inverter and drives the third output signal OUT with a signal line at a later stage.

8 illustrates an operation of a receiving circuit according to embodiments of the present invention.

1, 6, and 8, the input unit 130 of the P-type sense amplifier 100 may include a first sensing signal DI and a first sensing signal DI based on an input signal DIN and one reference voltage VREF. The second sensing signal DIB is generated. The P-type sense amplifier 100 may perform a sensing operation during the second half cycle in which the clock signal CLK is logic high and the second half cycle in which the clock signal CLK is logic low. The first sensing signal DI and the second sensing signal DIB may be provided to the voltage-current converter 152 as voltage signals, and output current of the voltage-current converter 152 of the amplifier 150. As a result, voltage levels of the first output signal Q and the second output signal QB of the latch unit 153 are formed. As described above, the first output signal Q and the second output signal QB may be incompletely swinging signals, and the rear end amplifier 170 may include the first output signal Q and the second output signal QB. ) Is gradually amplified to generate a third output signal OUT swinging between the power supply voltage VDDQ and the ground voltage VSSQ via the node voltages O1 and O2 of the latch unit 172.

9 is a circuit diagram illustrating another example of an amplifier included in the receiver circuit of FIG. 1.

9, the amplifier 150b may include a latch unit 156 and a pull-down unit 157.

The latch unit 156 is connected between the first node N1 receiving the first sensing signal DI and the second node N2 receiving the second sensing signal DIB and the ground voltage VSSQ. And a latch node NQ and an inverted latch node NQB for generating a first output signal Q and a second output signal QB, respectively. The latch unit 156 may include two inverters formed of PMOS transistors PM1 and PM2 and NMOS transistors NM1 and NM2, and an input and an output of the inverters may be cross-coupled to each other. Can be.

The pull-down unit 157 may include a first NMOS transistor NM3 and a second NMOS transistor NM4. The first NMOS transistor NM3 is connected between the latch node NQ and the ground voltage VSSQ, and a clock signal CLK is applied to the gate. The second NMOS transistor NM4 is connected between the inverting latch node NQB and the ground voltage VSSQ, and a clock signal CLK is applied to the gate.

10 illustrates a p-type sense amplifier according to embodiments of the present invention.

Referring to FIG. 10, the P-type sense amplifier 100a may include a switching unit 110, an input unit 130a, and an amplifier 150.

The switching unit 110 may include a switching PMOS transistor (PMS). The switching PMOS transistor PMS applies the power supply voltage VDDQ to the power supply node NP in response to the clock signal CLK. The switching PMOS transistor PMS is turned off during the first half cycle period in which the clock signal CLK is logic high to float the power supply node NP, and the second half cycle in which the clock signal CLK is logic low. During the operation, the power supply voltage VDDQ is applied to the power supply node NP. Therefore, the P-type sense amplifier 100a repeats the sensing operation during the first half period and the floating operation during the second half period.

The input unit 130a is connected to the power supply node NP to receive power through the switching PMOS transistor PMS, and responds to the input signal DIN, the first reference voltage VREF1, and the second reference voltage VREF2. PMOS transistors PMI1, PMI2, PMR1, and PMR2 generating the first sensing signal DI corresponding to the input signal DIN and the second sensing signal DIB corresponding to the reference voltages VREF1 and VREF2. ).

The amplifier 150 amplifies the first sensing signal DI and the second sensing signal DIB to generate a first output signal Q and a second output signal QB.

As described above, the ground termination resistor 200 connected between the receiving node NR receiving the input signal DIN and the ground voltage VSSQ may be formed. The ground termination resistor unit 200 may include at least one termination resistor Rt. In this case, the input signal DIN may be a signal swinging between the low voltage level VOL corresponding to the ground voltage VSSQ and the high voltage level VOH smaller than the power supply voltage VDDQ.

When the second sensing signal DIB is generated based on the two reference voltages VREF1 and VREF2, the input unit 130 may include the first input PMOS transistor PMI1, the first reference PMOS transistor PMR1, It may include a second input PMOS transistor PMI2 and a second reference PMOS transistor PMR2.

The first input PMOS transistor PMI1 is connected between the power supply node NP and the first node N1 generating the first sensing signal DI, and an input signal DIN is applied to the gate. The first reference PMOS transistor PMR1 is connected between the power supply node NP1 and the second node N2 generating the second sensing signal DIB, and the first reference voltage VREF1 is applied to the gate. The second input PMOS transistor PMI2 is connected between the power supply node NP and the first node N1, and an input signal DIN is applied to the gate. The second reference PMOS transistor PMR2 is connected between the power supply node NP and the second node N2, and the second reference voltage VREF2 is applied to the gate.

In this case, the first reference voltage VREF1 has a voltage level greater than the average voltage level VA of the low voltage level VOL and the high voltage level VOH of the input signal DIN, and the second reference voltage VREF2. ) Has a voltage level less than the average voltage level VA. In one embodiment, the first reference voltage VREF1 may have a high voltage level VOH of the input signal DIN, and the second reference voltage VREF2 may have a low voltage level VOL of the input signal DIN. Can have

10 illustrates an embodiment in which the input signal DIN is sensed using two reference voltages VREF1 and VREF2, but the reference voltage may include three or more voltages. For example, the reference voltage may include the three reference voltages VREF1, VREF2 and VREF (= VA) described above, in which case the input unit 110 receives the input signal DIN and the power node NP. ) And three input PMOS transistors and three reference voltages VREF1, VREF2 and VREF (= VA) coupled in parallel between the first node N1 and the power node NP and the second node, respectively. Three reference PMOS transistors coupled in parallel between the nodes N2 may be included. Similarly, the input signal DIN may be sensed using four reference voltages including two reference voltages larger than the average voltage level VA and two reference voltages smaller than the average voltage level VA.

11 illustrates an operation of a receiver circuit according to embodiments of the present invention.

6, 10, and 11, the input unit 130a of the P-type sense amplifier 100a may include a first sensing signal based on an input signal DIN and two reference voltages VREF1 and VREF2. And a second sensing signal DIB.

For example, the first reference voltage VREF1 may have a high voltage level VOH of the input signal DIN, and the second reference voltage VREF2 may have a low voltage level VOL of the input signal DIN. Can have

In this case, when the input signal DIN has the low voltage level VOL, since the voltage level of the input signal DIN and the second reference voltage VREF2 is the same, it passes through the second input PMOS transistor PMI2. The current passing through the second reference PMOS transistor PMR2 is the same. As a result, when the input signal DIN has the low voltage level VOL, the input unit 130a may input the input signal DIN applied to the first input PMOS transistor PMI1 and the first reference PMOS transistor PMR1. The first sensing signal DI and the second sensing signal DIB are generated based on the first reference voltage VREF1 applied to the first reference voltage VREF1.

In addition, when the input signal DIN has the high voltage level VOH, the current passing through the first input PMOS transistor PMI1 since the voltage level of the input signal DIN and the first reference voltage VREF1 are the same. And the current passing through the first reference PMOS transistor PMR1 are the same. As a result, when the input signal DIN has the high voltage level VOH, the input unit 130a may include the input signal DIN applied to the second input PMOS transistor PMI2 and the second reference PMOS transistor PMR2. The first sensing signal DI and the second sensing signal DIB are generated based on the second reference voltage VREF2.

The P-type sense amplifier 100a may float during a first half cycle in which the clock signal CLK is logic high and perform a sensing operation during the second half cycle in which the clock signal CLK is logic low. The first sensing signal DI and the second sensing signal DIB may be provided to the voltage-current converter 152 as voltage signals, and output current of the voltage-current converter 152 of the amplifier 150. As a result, voltage levels of the first output signal Q and the second output signal QB of the latch unit 153 are formed. As described above, the first output signal Q and the second output signal QB may be incompletely swinging signals, and the rear end amplifier 170 may include the first output signal Q and the second output signal QB. ) Is gradually amplified to generate a third output signal OUT swinging between the power supply voltage VDDQ and the ground voltage VSSQ via the node voltages O1 and O2 of the latch unit 172.

12 illustrates a sensing margin of a receiving circuit according to embodiments of the present invention.

In the upper part of FIG. 12, as shown in FIG. 1, when one reference voltage VREF having a high voltage level VOH of the input signal DIN and an average voltage level VA of the low voltage level VOL is used. The sensing margin SM of is indicated. In this case, the sensing margin SM is the same as the average voltage level VA for the case where the input signal DIN is the low voltage level VOL and the high voltage level VOH.

12, sensing margins when the first reference voltage VREF1 larger than the average voltage level VA and the second reference voltage VREF2 smaller than the average voltage level VA are used as shown in FIG. 10. (SM1, SM2) is displayed. In this case, when the input signal DIN has the low voltage level VOL, since the first reference voltage VREF1 and the low voltage level VOL are substantially compared, the first sensing margin SM1 is secured and the input signal is obtained. When DIN is the high voltage level VOL, since the second reference voltage VREF1 is substantially compared with the high voltage level VOH, the second sensing margin SM2 is secured. Both the first sensing margin SM1 and the second sensing margin SM2 are greater than the average voltage level VA. As a result, the sensing margin of the input signal may be further improved by increasing the sensing margin using the plurality of reference voltages.

13 and 14 are diagrams illustrating a system for performing bidirectional communication according to embodiments of the present invention.

FIG. 13 illustrates a bi-lateral communication using two uni-lateral lines TL1 and TL2, and FIG. 14 illustrates a common transmission line TL. An embodiment for performing bidirectional communication is shown.

Referring to FIG. 13, the system 11 includes a first device DEV1 and a second device DEV2 connected through two unidirectional transmission lines TL1 and TL2. The first device DEV1 includes a first transmit circuit TX1 and a first receive circuit RX1, and the second device DEV2 includes a second transmit circuit TX2 and a second receive circuit RX2. do. The transmission circuits TX1 and TX2 may include predrivers 311 and 312 and transmission drivers 351 and 352, respectively. The receiving circuits RX1 and RX2 may include ground termination resistors 201 and 202 and P-type sense amplifiers 101 and 102, respectively. The transmit drivers 351 and 352 may include pull-up NMOS transistors NMU1 and NMU2 and pull-down NMOS transistors NMD1 and NMD2 coupled between a power supply voltage VDDQ and a ground voltage VSSQ, respectively. have. The P-type sense amplifiers 101 and 102 may include a switching unit, an input unit, and an amplifier unit as described above.

The predriver 311 of the first device DEV1 outputs the pull-up signal PU1 and the pull-down signal PD1 corresponding to the first transmission signal DT1, and the transmission driver 351 transmits the pull-up signal PU1 and the pull-down. The first transmission line TL1 is driven in response to the signal PD1. The second P-type sense amplifier 102 of the second device DEV2 senses the first input signal DIN1 transmitted through the first transmission line TL1 to generate output signals Q1 and QB1. .

The predriver 312 of the second device DEV2 outputs a pull-up signal PU2 and a pull-down signal PD2 corresponding to the second transmit signal DT2, and the transmit driver 352 transmits a pull-up signal PU2 and a pull-down. The second transmission line TL2 is driven in response to the signal PD2. The first P-type sense amplifier 101 of the first device DEV1 senses the second input signal DIN2 transmitted through the second transmission line TL2 to generate output signals Q2 and QB2. .

As such, the system 11 may perform bidirectional communication using two unidirectional transmission lines TL1 and TL2. According to embodiments of the present invention, an NMOS transistor is used as a pull-up driver to increase the integration density and transmission speed of a circuit, and to efficiently receive an input signal small swing near a ground voltage using a P-type sense amplifier. have.

Referring to FIG. 14, the system 12 includes a first device DEV1 and a second device DEV2 connected through one bidirectional transmission line TL. The first device DEV1 includes a first transmit circuit TX1 and a first receive circuit RX1, and the second device DEV2 includes a second transmit circuit TX2 and a second receive circuit RX2. do. The transmission circuits TX1 and TX2 may include predrivers 311 and 312 and transmission drivers 351 and 352, respectively. Receive circuits RX1 and RX2 may include ground termination resistors 203 and 204 and P-type sense amplifiers 101 and 102, respectively. The transmit drivers 351 and 352 may include pull-up NMOS transistors NMU1 and NMU2 and pull-down NMOS transistors NMD1 and NMD2 coupled between a power supply voltage VDDQ and a ground voltage VSSQ, respectively. have. The P-type sense amplifiers 101 and 102 may include a switching unit, an input unit, and an amplifier unit as described above.

Compared to the ground termination resistors 201 and 202 included in the system 11 of FIG. 13, the ground termination resistors 203 and 204 included in the system 12 of FIG. 14 are respectively terminated resistors Rt1,. It may further include switches TS1 and TS2 coupled between Rt2) and ground voltage VSSQ. The first switch TS1 is turned on in response to the first end enable signal TEN1, and the second switch TS2 is turned on in response to the second end enable signal TEN2. The first end enable signal TEN1 and the second end enable signal TEN2 are complementarily activated.

The predriver 311 of the first device DEV1 outputs the pull-up signal PU1 and the pull-down signal PD1 corresponding to the first transmission signal DT1, and the transmission driver 351 transmits the pull-up signal PU1 and the pull-down. The transmission line TL is driven in response to the signal PD1. The second P-type sense amplifier 102 of the second device DEV2 senses the first input signal DIN1 transmitted through the transmission line TL to generate output signals Q1 and QB1.

The predriver 312 of the second device DEV2 outputs a pull-up signal PU2 and a pull-down signal PD2 corresponding to the second transmit signal DT2, and the transmit driver 352 transmits a pull-up signal PU2 and a pull-down. The transmission line TL is driven in response to the signal PD2. The first P-type sense amplifier 101 of the first device DEV1 senses the second input signal DIN2 transmitted through the transmission line TL to generate output signals Q2 and QB2.

In the case of signal transmission from the first device DEV1 to the second device DEV2, the first transmission circuit TX1 and the second reception circuit RX2 are enabled and the second transmission circuit TX2 and the first reception circuit are provided. (RX1) is disabled. In this case, the first ground termination resistor unit 203 is disabled in response to the deactivated first termination enable signal TEN1, and the second ground termination resistor in response to the activated second termination enable signal TEN2. Unit 204 is enabled.

In the case of signal transmission from the second device DEV2 to the first device DEV1, the second transmission circuit TX2 and the first receiving circuit RX1 are enabled and the first transmission circuit TX1 and the second receiving circuit are (RX2) is disabled. In this case, the second ground termination resistor unit 204 is disabled in response to the deactivated second termination enable signal TEN2, and the first ground termination resistor in response to the activated first termination enable signal TEN1. Part 203 is enabled.

As such, the system 12 may perform bidirectional communication using one bidirectional transmission line TL. According to embodiments of the present invention, an NMOS transistor is used as a pull-up driver to increase the integration density and transmission speed of a circuit, and to efficiently receive an input signal small swing near a ground voltage using a P-type sense amplifier. have.

15 illustrates a multi-channel system according to embodiments of the present invention.

Referring to FIG. 15, the system 13 includes a first device DEV1 and a second device DEV2 connected through a plurality of transmission lines TL1, TL2, and TL3. The first device DEV1 includes a plurality of transmit circuits TX1, TX2, and TX3, and the second device DEV2 includes a plurality of receive circuits RX1, RX2, and RX3. The transmitting circuits TX1, TX2, TX3 may have the same configuration, and the receiving circuits RX1, RX2, RX3 may have the same configuration. For example, the first transmitting circuit TX1 may include a predriver 311 and a transmitting driver 351, and the first receiving circuit RX1 may include a ground termination resistor 201 and a P-type sense amplifier. 101 may be included. The transmit driver 351 may include a pull-up NMOS transistor NMU and a pull-down NMOS transistor NMD coupled between a power supply voltage VDDQ and a ground voltage VSSQ. The P-type sense amplifier 101 may include a switching unit, an input unit, and an amplifier unit as described above.

The predriver 311 of the first transmission circuit TX1 outputs a pull-up signal PU1 and a pull-down signal PD1 corresponding to the first transmission signal DT1, and the transmission driver 351 transmits a pull-up signal PU1 and The first transmission line TL1 is driven in response to the pull-down signal PD1. The P-type sense amplifier 101 of the first receiving circuit RX1 senses the first input signal DIN1 transmitted through the first transmission line TL1 to generate output signals Q1 and QB1. Similarly, the second transmission circuit TX2 drives the second transmission line TL2 based on the second transmission signal DT2 and the second reception circuit RX2 is transmitted through the second transmission line TL2. It generates output signals Q2 and QB2 corresponding to the two input signals DIN2. The third input circuit TX3 drives the third transmission line TL3 based on the third transmission signal DT3 and the third receiving circuit RX3 is the third input transmitted through the third transmission line TL3. Generate output signals Q3 and QB3 corresponding to signal DIN3.

13 and 14 show systems 11 and 12 comprising one bidirectional channel, and in FIG. 15 a multi-channel for unidirectional communication from the first device DEV1 to the second device DEV2. Although system 13 is shown, it can be combined to implement a bidirectional multi-channel system comprising a plurality of bidirectional channels.

16 and 17 illustrate systems for providing a plurality of reference voltages according to embodiments of the present invention.

Referring to FIG. 16, the system 14 includes a first device DEV1 and a second device DEV2 connected through a transmission line TL. The first device DEV1 may operate as a transmitter and include a predriver 310 and a transmit driver 350 as described above. The second device DEV2 may operate as a receiver and may include the P-type sense amplifier 100 and the ground termination resistor 200 as described above.

As shown in FIG. 16, the second device DEV2 operating as a receiver may further include a reference voltage generator 500. The reference voltage generator 500 may have a first reference voltage VREF1 that is greater than an average voltage level of the low voltage level VOL and the high voltage level VOH of the input signal DIN based on at least one input signal DIN. And a second reference voltage REF2 smaller than the average voltage level. For example, the reference voltage generator 500 measures the low voltage level VOL and the high voltage level VOH of the input signal DIN through an initialization operation of the system 14, and based on the measured value, Voltage levels of the reference voltage VREF1 and the second reference voltage REF2 may be determined.

The P-type sense amplifier 100a may have a configuration as shown in FIG. 10 and increase the sensing margin of the input signal DIN using the first reference voltage VREF1 and the second reference voltage VREF2. By doing so, the sensing sensitivity of the input signal DIN can be further improved.

Referring to FIG. 17, the system 15 includes a first device DEV1 and a second device DEV2 connected through transmission lines TL, RTL1, and RTL2. The first device DEV1 may operate as a transmitter and include a predriver 310 and a transmit driver 350 as described above. The second device DEV2 may operate as a receiver and may include the P-type sense amplifier 100 and the ground termination resistor 200 as described above.

As illustrated in FIG. 17, the first device DEV1 operating as a transmitter may further include a first reference driver 361 and a second reference driver 362. The first reference driver 361 has the same configuration as the transmission driver 350 and operates the first reference voltage VREF1 having the high voltage level VOH of the input signal DIN as the receiver DEV2. ) The second reference driver 362 has the same configuration as the transmission driver 350 and operates the second reference voltage VREF2 having the low voltage level VOL of the input signal DIN as a receiver. ) The first reference voltage VREF1 and the second reference voltage VREF are provided to the second device DEV2 through the reference voltage transmission lines RTL1 and RTL2, respectively. The reference voltage transmission lines RTL1 and RTL2 are terminated with ground termination resistors 211 and 212 having the same configuration as the ground termination resistor 200 of the signal transmission line TL. In addition, the first device DEV1 may include a first reference predriver 321 and a first reference predriver 321 which provide signals PU1, PU2, PD1, and PD2 for controlling the first reference driver 361 and the second reference driver 362. A second reference predriver 322 may be further included.

The first device DEV1 may be integrated by the same process and formed of one chip. In this case, the components 321, 322, 361, and 362 for providing the reference voltages VREF1 and VREF2 have the same operating characteristics as the components 310 and 350 for signal transmission. Therefore, the deviations due to the manufacturing process and variations in temperature, voltage, etc. are commonly reflected in the signal transmission and the reference voltage transmission. Therefore, the reference voltages VREF1 and VREF2 are the high and low voltage levels of the input signal DIN (VOL) can be provided accurately.

The P-type sense amplifier 100a may have a configuration as shown in FIG. 10 and increase the sensing margin of the input signal DIN using the first reference voltage VREF1 and the second reference voltage VREF2. By doing so, the sensing sensitivity of the input signal DIN can be further improved.

18 is a diagram illustrating operation of the system of FIG. 17.

Referring to FIG. 18, the pull-up signal PU and the pull-down signal PD output from the predriver 310 complementarily transition between the first voltage V1 and the second voltage V2 according to the transmission signal. . The first voltage V1 and the second voltage V2 may be ground voltages and power supply voltages of the first device DEV1 operating as a transmitter, respectively.

The first reference predriver 321 is implemented to output the pull-up signal PU1 fixed to the first voltage V1 and the pull-down signal PD1 fixed to the second voltage V2. Accordingly, the pull-up NMOS transistor NMU of the first reference driver 361 is always turned on and the pull-down NMOS transistor NMD is always turned off. As a result, the first reference voltage VREF1 received by the second device DEV2 through the first reference voltage transmission line RTL1 has the high voltage level VOH of the input signal DIN.

The second reference predriver 322 is implemented to output the pull-up signal PU2 fixed to the second voltage V2 and the pull-down signal PD2 fixed to the first voltage V1. Accordingly, the pull-up NMOS transistor NMU of the second reference driver 362 is always turned off and the pull-down NMOS transistor NMD is always turned on. As a result, the second reference voltage VREF2 received by the second device DEV2 through the second reference voltage transmission line RTL2 has a low voltage level VOH of the input signal DIN.

19 is a diagram illustrating a system for performing another DL transmission in embodiments of the present invention.

Referring to FIG. 19, the system 16 includes a first device DEV1 and a second device DEV2 connected via a transmission line TL. The first device DEV1 may operate as a transmitter and may include a predriver 310 and a transmit driver 35 as described above. The second device DEV2 may operate as a receiver and include a first P-type sense amplifier 111, a second P-type sense amplifier 112, and a ground termination resistor 200 as described above. have.

The system 16 may perform a double data rate (DDR) transmission that transmits a 2-bit signal during one period of the clock signal CLK. The first device DEV1 acting as a transmitter has a configuration corresponding to the dial transmission. For example, the predriver 310 generates a pull-up signal PU and a pull-down signal PD to transmit one even bit and one odd bit of the transmission signal during one clock period.

The clock signal CLK is applied to the gate of the switching PMOS transistor PMS1 of the first P-type sense amplifier 111, and the gate of the switching PMOS transistor PMS2 of the second P-type sense amplifier 112 is applied. The inverted clock signal CLKB is applied to it. The second P-type sense amplifier 112 performs a sensing operation during the first half cycle in which the clock signal CLK is logic high and from the power supply voltage during the second half cycle in which the clock signal CLK is logic low. Blocked and floated. On the other hand, the first P-type sense amplifier 111 is disconnected from the power supply voltage during the first half period in which the clock signal CLK is logic high and is floated, and performs the sensing operation during the second half period in which the clock signal CLK is logic low. do. As a result, the first P-type sense amplifier 111 senses even-numbered bits included in the input signal DIN to generate even output signals QE and QEB, and the second P-type sense amplifier 112. ) Senses odd bits included in the input signal DIN to generate odd output signals QO and QOB.

As such, by using the two P-type sense amplifiers 111 and 112 to support the digital transmission, the operating frequency can be increased and the operating speed of the system 16 can be improved.

20 and 21 are diagrams illustrating a semiconductor package including a semiconductor memory system according to example embodiments.

Referring to FIG. 20, the semiconductor package 800 is disposed on a base substrate BASE 810, a controller chip CTRL 820 disposed on the base substrate 810, and a controller chip 820. At least one semiconductor memory chip (MEM) 840 is included. The base substrate 810 may be a printed circuit board (PCB), and the controller chip 820 may include a microprocessor unit (MPU). After the chips are stacked, an upper portion of the semiconductor package 800 may be coated with a resin 870 or the like. The semiconductor memory chip 840 and the controller chip 820 may perform signal transmission according to the embodiments described with reference to FIGS. 1 to 19.

20, the semiconductor memory chip 840 and the controller chip 820 are electrically connected to each other through the input / output bumps 830 of the semiconductor memory chip 840, and the controller chip 820 and the printed circuit board ( 810 may be electrically connected by a bonding method using a wire 860. A bump 811 may be formed on the bottom surface of the printed circuit board 810 for electrical connection with an external device.

Referring to FIG. 21, a semiconductor package 900 may be disposed on a base substrate (BASE) 910, a controller chip (CTRL) 920 disposed on the base substrate 910, and a controller chip 920. At least one semiconductor memory chip (MEM) 940 is included. After the chips are stacked, an upper portion of the semiconductor package 900 may be coated with a resin 970 or the like. The semiconductor memory chip 940 and the controller chip 920 may perform signal transmission according to the embodiments described with reference to FIGS. 1 to 19.

In the embodiment of FIG. 21, the semiconductor memory chip 940 and the controller chip 920 are electrically connected through the input / output bumps 930 of the semiconductor memory chip 940, and the controller chip 920 and the printed circuit board ( 910 may be electrically connected through bump 921. The controller chip 920 may include a substrate through via 955. In this case, the interface load resistance between the printed circuit board 910 and the semiconductor memory chip 940 may be reduced, thereby facilitating smooth signal transmission. A bump 911 for electrical connection with an external device may be formed on the bottom surface of the printed circuit board 910.

22 is a block diagram illustrating an example in which a system according to embodiments of the present disclosure is applied to an electronic device.

Referring to FIG. 22, the electronic device 1000 includes a system on chip 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and an image sensor 1060. can do. Although not shown in FIG. 22, the electronic device 1000 may further include ports for communicating with a video card, a sound card, a memory card, a USB device, or the like, or communicating with other electronic devices. .

The system on chip 1010 may be an application processor system on chip (AP SOC) and include an interconnect device INT and a plurality of intelligent elements (or functional blocks) connected thereto. For example, the intelligent devices may include a memory controller (MC), a central processing unit, a display controller (DIS), a file system block (FSYS), and a graphics processor. (GPU), an image signal processor (ISP), a multi-format codec block (MFC), and the like.

The memory controller MC and the memory device 1020 may perform signal transmission according to the embodiments described with reference to FIGS. 1 to 19.

The system on chip 1010 may include a memory device 1020, a storage device 1030, an input / output device 1040, and an image sensor through an address bus, a control bus, and a data bus. 2060). In some embodiments, the system on chip 1010 may also be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 1020 may store data and program codes necessary for the operation of the electronic device 2000. For example, the memory device 1020 can be implemented as a DRAM, a mobile DRAM, an SRAM, a PRAM, an FRAM, an RRAM, and / or an MRAM have. Storage device 1030 may include a solid state drive, a hard disk drive, a CD-ROM, and the like. The input / output device 1040 may include input means such as a keyboard, a keypad, a mouse, and the like, and output means such as a printer or a display. The power supply 1050 can supply the operating voltage required for operation of the electronic device 1000. [

The image sensor 1060 may be connected to the system on chip 1010 through the buses or other communication links to perform communication. The image sensor 1060 may be integrated on one chip together with the system on chip 1010, or may be integrated on different chips, respectively.

At least some of the components of the electronic device 1000 illustrated in FIG. 22 may be implemented in various types of packages. For example, at least some of the configurations include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP) It may be implemented using packages such as.

Meanwhile, the electronic device 1000 should be interpreted as all devices and systems for performing signal transmission according to embodiments of the present invention. For example, the electronic device 1000 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smartphone, or the like.

23 is a block diagram showing an example of an interface used in the electronic apparatus of Fig.

Referring to FIG. 23, the electronic device 1100 may be embodied as a data processing apparatus capable of using or supporting a MIPI interface, and includes an application processor chip (AP SOC) 1110 and an image sensor 1140. And a display 1150 and the like.

The CSI host 1112 of the system on chip 1110 can perform serial communication with the CSI device 1141 of the image sensor 1140 through a camera serial interface (CSI). In one embodiment, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER). The DSI host 1111 of the system on chip 1110 may perform serial communication with the DSI device 1151 of the display 1150 through a display serial interface (DSI).

In one embodiment, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). In addition, the electronic device 1100 may further include a radio frequency (RF) chip 1160 that may communicate with the system on chip 1110. The PHY 1113 of the electronic device 1100 and the PHY 1161 of the RF chip 1160 can perform data transmission and reception according to a Mobile Industry Processor Interface (MIPI) DigRF. In addition, the system on chip 1110 may further include a DigRF MASTER 1114 for controlling data transmission and reception according to the MIPI DigRF of the PHY 1161.

The electronic device 1100 includes a GPS (Global Positioning System) 1120, a storage 1170, a microphone 1180, a dynamic random access memory (DRAM) 1185, and a speaker 1190 . In addition, the electronic device 1100 may use an ultra wideband (UWB) 1210, a wireless local area network (WLAN) 1220, a worldwide interoperability for microwave access (WIMAX) 1230, or the like. Communication can be performed. The structure and interface of the electronic device 1100 illustrated in FIG. 22 are merely examples and are not limited thereto.

Embodiments of the present invention may be used in any device and system requiring signal transmission, and may be particularly useful in portable devices and systems requiring miniaturization, high speed operation, and low power.

While the present invention has been described with reference to the preferred embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined in the appended claims. It will be understood.

100: P-type sense amplifier 110: switching unit
130: input unit 150: amplification unit
170: rear end amplifier 200: ground termination resistor
310: Predriver 350: Send Driver
DIN: input signal VREF: reference voltage
VOH: high voltage level of the input signal
VOL: Low voltage level of the input signal

Claims (10)

A switching PMOS transistor that applies a power supply voltage to a power supply node in response to a clock signal;
PMOS transistors connected to the power node to receive power and generate a first sensing signal corresponding to the input signal and a second sensing signal corresponding to the reference voltage in response to an input signal and at least one reference voltage. An input unit including; And
And an amplifier configured to amplify the first sensing signal and the second sensing signal to generate a first output signal and a second output signal. The method according to claim 1,
And a ground termination resistor connected between the receiving node receiving the input signal and a ground voltage,
And the input signal is a signal swinging between a low voltage level corresponding to the ground voltage and a high voltage level less than the power supply voltage. The method of claim 2, wherein the input unit,
An input PMOS transistor coupled between the power node and a first node generating the first sensing signal, the input PMOS transistor being applied to a gate; And
A reference PMOS connected between the power node and a second node generating the second sensing signal, the reference voltage having an average voltage level of the low voltage level and the high voltage level of the input signal applied to a gate; A receiving circuit comprising a transistor. The method of claim 2,
And the at least one reference voltage comprises a plurality of reference voltages having different voltage levels. The method of claim 2,
The at least one reference voltage includes a first reference voltage greater than the average voltage level of the low voltage level and the high voltage level of the input signal and a second reference voltage less than the average voltage level . The method of claim 5, wherein the input unit,
When the input signal has the low voltage level, the first sensing signal and the second sensing signal are generated based on the input signal and the first reference voltage.
And when the input signal has the high voltage level, generating the first sensing signal and the second sensing signal based on the input signal and the second reference voltage. The method of claim 2,
And the at least one reference voltage comprises a first reference voltage having the high voltage level of the input signal and a second reference voltage having the low voltage level of the input signal. The method of claim 7, wherein the input unit,
A first input PMOS transistor connected between the power node and a first node generating the first sensing signal, and having the input signal applied to a gate;
A first reference PMOS transistor connected between the power node and a second node generating the second sensing signal, and the first reference voltage being applied to a gate;
A second input PMOS transistor connected between the power supply node and the first node and to which the input signal is applied to a gate; And
And a second reference PMOS transistor coupled between the power supply node and the second node, the second reference voltage being applied to a gate. The method of claim 2,
And a rear end amplifier for amplifying the first output signal and the second output signal to generate a third output signal that swings between the power supply voltage and the ground voltage. A transmission circuit comprising a transmission driver for driving a transmission node in response to a pull-up signal and a pull-down signal;
A receiving circuit which receives an input signal through a receiving node connected to the transmitting node by a transmission line,
The receiving circuit,
A switching PMOS transistor that applies a power supply voltage to a power supply node in response to a clock signal;
A PMOS transistor connected to the power node to receive power and to generate a first sensing signal corresponding to the input signal and a second sensing signal corresponding to the reference voltage in response to the input signal and at least one reference voltage. Input unit comprising a; And
And an amplifier configured to amplify the first sensing signal and the second sensing signal to generate a first output signal and a second output signal.

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