KR20130044051A - Method manufacturing of semiconductoer packagehe - Google Patents

Method manufacturing of semiconductoer packagehe Download PDF

Info

Publication number
KR20130044051A
KR20130044051A KR1020110108308A KR20110108308A KR20130044051A KR 20130044051 A KR20130044051 A KR 20130044051A KR 1020110108308 A KR1020110108308 A KR 1020110108308A KR 20110108308 A KR20110108308 A KR 20110108308A KR 20130044051 A KR20130044051 A KR 20130044051A
Authority
KR
South Korea
Prior art keywords
mold
level substrate
strip level
molding resin
substrate
Prior art date
Application number
KR1020110108308A
Other languages
Korean (ko)
Inventor
김기채
김진용
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110108308A priority Critical patent/KR20130044051A/en
Publication of KR20130044051A publication Critical patent/KR20130044051A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The present invention relates to a method for manufacturing a semiconductor package, which has a rectangular shape in plan view, and includes a plurality of unit substrates each having a semiconductor chip mounted thereon, and a strip level substrate having via holes provided at one edge of a long side. Preparing; Placing the strip level substrate in a mold having cavities and vacuum holes such that each via hole of the strip level substrate is located in each vacuum hole of the mold; And molding the mounted semiconductor chips by injecting a molding resin into a cavity of the mold in which the strip level substrate is disposed, and when the molding resin is introduced, a via hole and the mold provided in the strip level substrate. It is characterized in that the air in the mold (Air) is completely discharged through the vacuum hole provided in the.

Description

Manufacturing method of semiconductor package {METHOD MANUFACTURING OF SEMICONDUCTOER PACKAGEHE}

The present invention relates to a method of manufacturing a semiconductor package.

In general, a semiconductor package is packaged in a form that can be mounted on an electronic device required by packaging the semiconductor chip to protect it safely from an external environment, and various kinds of semiconductor packages have been developed.

The method of manufacturing a semiconductor package includes a die attach process for attaching a semiconductor chip through an adhesive to a chip attaching region of the upper surface of the substrate and a semiconductor resin to protect the semiconductor chip from an external environment by covering the upper surface of the substrate with a molding resin. Manufacturing of the semiconductor package is completed by performing a molding process for forming a seal.

In general, molding is a process for protecting a semiconductor chip from an external environment and an impact, and the molding process is performed by a mold apparatus for supplying a viscous liquid molding resin to a substrate to which the semiconductor chip is attached.

However, in the molding process, since the entire upper surface of the substrate on which the semiconductor chips are arranged must be wrapped with the molding resin, voids are generated near the edge of the substrate adjacent to the air outlet of the mold apparatus.

This problem is more likely to occur in a substrate in which two or more semiconductor chips are vertically stacked in a chip attaching region than in a single chip attached to each chip attaching region, and the number of semiconductor chips stacked in each chip attaching region. The more, the more severe the occurrence of voids.

This problem occurs because the flow rate of the molding resin in the semiconductor chip region and the gap region in the upper surface of the substrate is different. Here, the semiconductor chip region is a region where semiconductor chips are attached, and the gap region is a region where semiconductor chips between the semiconductor chip regions are not attached.

That is, in the semiconductor chip region, the flow rate of the molding resin is slow because the gap between the upper surface of the semiconductor chip and the cavity upper surface is narrow and the width of the semiconductor chip region is wide.

On the other hand, in the gap region, since the gap between the upper surface of the substrate and the cavity upper surface is wider and the width of the gap region is wider than that of the semiconductor chip region, the molding resin is filled first in the gap region because of the faster flow rate of the molding resin.

This causes the molding resin to flow backward from the fast gap region of the molding resin to the slow semiconductor chip region, and voids are caused by a space in which air pushed by the molding resin to be filled later cannot escape to the outside and cannot be gap-filled. There is a problem that occurs. When heat is applied to the voids, the air inside the voids expands and cracks are generated, thereby lowering the reliability of the product.

An object of the present invention is to provide a method for manufacturing a semiconductor package in which a void is not generated by preventing the backflow of the molding resin in the molding step, thereby improving mold defects.

The method of manufacturing a semiconductor package according to the present invention includes a plurality of unit substrates each having a rectangular shape when viewed in plan view, and each of which a semiconductor chip is mounted, and providing a strip level substrate having via holes provided at one edge of a long side. step; Placing the strip level substrate in a mold having cavities and vacuum holes such that each via hole of the strip level substrate is located in each vacuum hole of the mold; And molding the mounted semiconductor chips by injecting a molding resin into a cavity of the mold in which the strip level substrate is disposed, and when the molding resin is introduced, a via hole and the mold provided in the strip level substrate. It is characterized in that the air in the mold (Air) is completely discharged through the vacuum hole provided in the.

In addition, the via holes may be provided at a long side edge portion of the strip level substrate facing the inflow portion of the molding resin.

Further, the via holes may be respectively provided at edge portions of the strip level substrate, which are perpendicular to the portion where the semiconductor chip is mounted.

Further, the molding may be performed by mounting a vacuum unit in the vacuum hole so that the air in the mold may quickly exit through the via hole of the strip level substrate and the vacuum hole of the mold.

According to the present invention, in the molding process of a semiconductor package, after forming a via hole which is an air release hole in a substrate and a vacuum hole in a loading part of a molding apparatus, by placing the via hole in the vacuum hole, the via hole Since the and the vacuum hole serves as an air outlet of the semiconductor chip region, it is possible to prevent the backflow of the molding resin to prevent voids and improve mold defects, thereby improving the reliability of the product and the productivity of the product.

1 is a plan view illustrating a strip level substrate for manufacturing a semiconductor package according to an embodiment of the present invention.
2 is a plan view illustrating a mold apparatus for manufacturing a semiconductor package according to an embodiment of the present invention.
3 is a perspective view illustrating an electronic device having a semiconductor package according to the present invention.
4 is a system block diagram of an electronic device to which the semiconductor package according to the present invention is applied.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The semiconductor package includes a strip level substrate on which a plurality of unit substrates as chip attaching regions are provided, a semiconductor chip attached to each unit substrate, and the like.

The mold apparatus for sealing a semiconductor package includes an upper mold having a first space accommodating a molding resin therein; A strip part having a second space accommodating a semiconductor chip mounting the semiconductor chip facing the first space, and a loading portion on which the strip level substrate is placed at the bottom of the second space, and an aligned and loaded strip level when the strip level substrate is loaded A lower mold having a tip configured to perform vacuum pumping for packaging of the substrate; And a vacuum pump connected to the tip and the pipe of the lower mold and performing pumping for packaging.

In the method of sealing a semiconductor package, when the upper mold and the lower mold are loaded after the substrate is loaded, one surface of the substrate in the second space of the lower mold 32 is covered with molding resin of the first space of the upper mold, thereby adhering them. This is induced and then the substrate is packaged with molding resin by pumping of a vacuum pump.

<Examples>

1 is a plan view illustrating a strip level substrate for manufacturing a semiconductor package according to an embodiment of the present invention.

As shown in FIG. 1, a strip level substrate 100 for manufacturing a semiconductor package according to an embodiment of the present invention includes a unit substrate 10 arranged in a matrix form; A semiconductor chip region 10-a which is a region where semiconductor chips are attached to the unit substrate 10; And a gap region 10-b which is a region where the semiconductor chips between the semiconductor chip regions 10-a are not attached.

The strip level substrate 100 for manufacturing a semiconductor package according to an embodiment of the present invention is a via hole, which is one or more air discharge holes formed on an end portion of a semiconductor chip region 10-a in a flow direction of a molding resin used in a molding process of a semiconductor package. It further includes (30).

Here, the strip level substrate 100 has a rectangular plate shape.

The reason for arranging the unit substrate 10 in a matrix form, ie, with a plurality of species, is to improve the efficiency of mass production and operation of the semiconductor package.

The via hole 30 serves as an air outlet of the semiconductor chip region 10-a in the molding process of the semiconductor package.

The via hole 30 is formed above the end portion of the semiconductor chip region 10-a in the flow direction of the molding resin so as to serve as an air outlet of the semiconductor chip region 10-a. In detail, the via hole 30 is formed through the edge of the strip level substrate 100 along a long side a of one strip level substrate 100 having a rectangular shape.

2 is a plan view illustrating a mold apparatus for manufacturing a semiconductor package according to an embodiment of the present invention.

And a mold apparatus for manufacturing a semiconductor package according to an embodiment of the present invention, as shown in Figure 2, the port (PT) is supplied with a molding resin for sealing the semiconductor package; A runner (RN) which serves as a path through which the molding resin flows; A loading part 200 connected to the runner RN and on which the strip level substrate 100 is placed; And at least one vacuum formed in the loading part 200 corresponding to the via hole 30 in the loading part 200 above the portion where the semiconductor chip region 10-a in the flow direction of the molding resin is placed. And a hole 220.

 Here, the vacuum hole 220 is formed at the edge of the loading part 200 on the upper side of each unit substrate 10 disposed at the outermost part of the matrix and positioned to correspond to the via hole 30.

The vacuum hole 220 serves as an air outlet of the semiconductor chip region 10-a in the molding process of the semiconductor package.

In detail, in the molding process of the semiconductor package, by placing the via hole 30 in the vacuum hole 220, the via hole 30 and the vacuum hole 220 are formed in the semiconductor chip region 10-a. It will act as an air outlet.

The molding resin is an epoxy mold compound.

A method of manufacturing a semiconductor package according to an embodiment of the present invention will be described.

First, a semiconductor chip is mounted on each unit substrate 10 of the strip level substrate 100. Here, only one semiconductor chip may be attached to each unit substrate 10 of the strip level substrate 100, or two or more semiconductor chips may be vertically stacked on each unit substrate 10 in order to double the capacity, and may be stacked. A semiconductor package can also be formed.

The strip level substrate 100 on which the semiconductor chip is mounted is loaded on the loading unit 200.

Thereafter, the upper mold and the lower mold are moved up and down so that the coupling is fastened to seal the inside of the mold die. Here, the upper mold and the lower mold may be loaded together, or any one of the upper mold and the lower mold may be loaded.

The upper mold is lowered so that the molding resin seated in the first space of the upper mold is positioned on the side of the strip level substrate 100.

Next, when the vacuum pump connected to the tip of the lower mold is operated, the internal air pressure of the closed mold die is lowered, and the molding resin seated in the first space of the upper mold while the outside air is sucked into the mold die. Is separated through the port (PT), runner (RN) in the upper mold. The separated molding resin forms a film while accommodating a semiconductor chip mounted on the strip level substrate 100.

At this time, by placing the via hole 30 in the vacuum hole 220, the air pushed out by the molding resin of the semiconductor chip region 10-a having a slow flow rate of the molding resin is the via hole 30 and the vacuum hole ( Through 220).

That is, when the molding resin flows in, air in the mold die is completely discharged through the via hole 30 provided in the strip level substrate 100 and the vacuum hole 220 provided in the mold mold.

Finally, the semiconductor package sealed with the molding resin is completed by separating the upper mold and the lower mold up and down.

As described above, in the semiconductor package molding process of the semiconductor package according to the embodiment of the present invention, the via hole 30 is positioned in the vacuum hole 220 so that the flow rate of the molding resin has a low semiconductor chip region ( Since the air pushed out by the molding resin of 10-a escapes through the via hole 30 and the vacuum hole 220 serving as the air outlet of the semiconductor chip region 10-a, the backflow of the molding resin By preventing the voids are not generated can improve the mold defect.

In addition, the semiconductor package described above may be applied to various package modules.

3 is a perspective view illustrating an electronic device having a semiconductor package according to an embodiment of the present disclosure. Referring to FIG. 3, the multilayer semiconductor package according to an embodiment of the present disclosure may be applied to an electronic device 1000 such as a mobile phone. Since the semiconductor package according to the present exemplary embodiment is excellent in terms of size reduction and electrical characteristics, it is advantageous to reduce the thickness of the electronic device 1000 that simultaneously implements various functions. The electronic device is not limited to the mobile phone illustrated in FIG. 3, for example, a mobile electronic device, a laptop computer, a portable computer, a portable multimedia player (PMP), an MP3 player, a camcorder, a web tablet. ), A wireless telephone, navigation, and a personal digital assistant (PDA).

4 is a block diagram illustrating an example of an electronic device including a semiconductor package according to the present disclosure. Referring to FIG. 4, the electronic system 1300 may include a controller 1310, an input / output device 1320, and a memory device 1330. The controller 1310, the input / output device 1320, and the memory device 1330 may be coupled through a bus 1350. The bus 1350 may be a path through which data flows. For example, the controller 1310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing the same functions. The controller 1310 and the memory device 1330 may include a semiconductor package according to the present invention. The input / output device 1320 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 1330 is a device for storing data. The storage device 1330 may store data and / or instructions that may be executed by the controller 1310. The storage device 1330 may include a volatile storage element and / or a non-volatile storage element. Alternatively, the storage device 1330 may be formed of a flash memory. For example, a flash memory to which the technique of the present invention is applied can be mounted on an information processing system such as a mobile device or a desktop computer. Such a flash memory may consist of a semiconductor disk device (SSD). In this case, the electronic system 1300 can stably store a large amount of data in the flash memory system. The electronic system 1300 may further include an interface 1340 for transferring data to or receiving data from the communication network. The interface 1340 may be in a wired or wireless form. For example, the interface 1340 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1300 may be further provided with an application chip set, a camera image processor (CIS), and an input / output device. Self-explanatory to those who have learned.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to the drawing.

10: unit substrate 30: via hole
100: strip level substrate 200: loading portion
220: vacuum hole

Claims (4)

Providing a strip level substrate having a rectangular shape in plan view and including a plurality of unit substrates each having a semiconductor chip mounted thereon, and having via holes installed at one edge of a long side thereof;
Placing the strip level substrate in a mold having cavities and vacuum holes such that each via hole of the strip level substrate is located in each vacuum hole of the mold; And
Molding the mounted semiconductor chips by introducing a molding resin into a cavity of the mold in which the strip level substrate is disposed;
The method of manufacturing a semiconductor package, characterized in that the air in the mold is completely discharged through the via hole provided in the strip level substrate and the vacuum hole provided in the mold when the molding resin is introduced. The method of claim 1,
And the via holes are provided at a long side edge portion of the strip level substrate facing the inflow portion of the molding resin. 3. The method of claim 2,
And the via holes are provided at edge portions of the strip-level substrate, each of which is perpendicular to a portion where the semiconductor chip is mounted. The method of claim 1,
The molding may include mounting a vacuum unit in the vacuum hole so that air in the mold may quickly exit through the via hole of the strip level substrate and the vacuum hole of the mold. .
KR1020110108308A 2011-10-21 2011-10-21 Method manufacturing of semiconductoer packagehe KR20130044051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110108308A KR20130044051A (en) 2011-10-21 2011-10-21 Method manufacturing of semiconductoer packagehe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110108308A KR20130044051A (en) 2011-10-21 2011-10-21 Method manufacturing of semiconductoer packagehe

Publications (1)

Publication Number Publication Date
KR20130044051A true KR20130044051A (en) 2013-05-02

Family

ID=48656668

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110108308A KR20130044051A (en) 2011-10-21 2011-10-21 Method manufacturing of semiconductoer packagehe

Country Status (1)

Country Link
KR (1) KR20130044051A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9818703B2 (en) 2015-11-17 2017-11-14 Samsung Electronics Co., Ltd. Printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9818703B2 (en) 2015-11-17 2017-11-14 Samsung Electronics Co., Ltd. Printed circuit board

Similar Documents

Publication Publication Date Title
US9832860B2 (en) Panel level fabrication of package substrates with integrated stiffeners
US6969640B1 (en) Air pocket resistant semiconductor package system
TWI520232B (en) Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8273607B2 (en) Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereof
US20070187839A1 (en) Integrated circuit package system with heat sink
US20220157678A1 (en) Integrated circuit packages with cavities and methods of manufacturing the same
WO2011150879A2 (en) Method for encapsulating semiconductor and structure thereof
US8941245B2 (en) Semiconductor package including semiconductor chip with through opening
JP6598642B2 (en) Resin sealing device and resin sealing method
TW201517216A (en) Module with stack package components
KR20130044052A (en) Stacked semiconductor package
KR20130044051A (en) Method manufacturing of semiconductoer packagehe
KR20110124064A (en) Stack type semiconductor package
KR102647213B1 (en) electronic device package
US11552051B2 (en) Electronic device package
US8981548B2 (en) Integrated circuit package system with relief
US8513801B2 (en) Integrated circuit package system
CN103354226B (en) Stack packaged device
US8957509B2 (en) Integrated circuit packaging system with thermal emission and method of manufacture thereof
Zhang et al. Low cost high performance bare die PoP with embedded trace coreless technology and “coreless cored” build up substrate manufacture process
KR102653763B1 (en) Electronic package assembly with stiffeners
US8524538B2 (en) Integrated circuit packaging system with film assistance mold and method of manufacture thereof
US20100072630A1 (en) Integrated circuit package system with adhesive segment spacer
US7863761B2 (en) Integrated circuit package system with molding vents
KR20150003507A (en) Semiconductor package and method of maunfacturing the same

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination