KR20130028530A - Multi chip package and operating method thereof - Google Patents

Multi chip package and operating method thereof Download PDF

Info

Publication number
KR20130028530A
KR20130028530A KR1020110092149A KR20110092149A KR20130028530A KR 20130028530 A KR20130028530 A KR 20130028530A KR 1020110092149 A KR1020110092149 A KR 1020110092149A KR 20110092149 A KR20110092149 A KR 20110092149A KR 20130028530 A KR20130028530 A KR 20130028530A
Authority
KR
South Korea
Prior art keywords
clock signal
semiconductor memory
internal clock
memory devices
memory device
Prior art date
Application number
KR1020110092149A
Other languages
Korean (ko)
Inventor
이현우
권대한
김기한
구자범
김철우
임수빈
Original Assignee
에스케이하이닉스 주식회사
고려대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사, 고려대학교 산학협력단 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110092149A priority Critical patent/KR20130028530A/en
Publication of KR20130028530A publication Critical patent/KR20130028530A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects

Landscapes

  • Dram (AREA)

Abstract

PURPOSE: A multichip package and an operating method thereof are provided to maximally secure a data valid period by outputting data without an overlap. CONSTITUTION: A first through via(TSV1) transmits an external clock signal generated in a central processing unit(310) to a plurality of semiconductor memory devices(320,330,340). A second through via(TSV2) is connected to the plurality of semiconductor memory devices and transmits a common internal clock signal generated in one semiconductor memory device to the remaining semiconductor memory devices. A third through via(TSV3) transmits data outputted from the plurality of semiconductor devices to a central processing unit. [Reference numerals] (310) Central processing unit; (320) First semiconductor memory device; (330) Second semiconductor memory device; (340) Third semiconductor memory device

Description

MULTI CHIP PACKAGE AND OPERATING METHOD THEREOF

The present invention relates to semiconductor design technology, and more particularly, to a multi-chip package including a plurality of semiconductor memory devices and a method of operating the same.

In general, semiconductor memory devices including DDR SDRAM (Double DAT_OUTa Rate Synchronous DRAM) are changing in order to satisfy various demands. Among these changes can be structural changes, such as Multi Chip Package (MCP). The multi chip package is configured to use a semiconductor chip such as a semiconductor memory device as a single chip, and may be divided into a single layer multi chip package and a multi layer multi chip package. The single-layered multi-chip package has a structure in which a plurality of semiconductor chips are arranged side by side on a plane, and the multi-layered multi-chip package has a structure in which a plurality of semiconductor chips are stacked.

Meanwhile, when a plurality of semiconductor memory devices are implemented in a multi-layer multi-chip package, conventionally, input / output terminals of each semiconductor memory device are wire-bonded. However, since wire bonding is vulnerable to various noises, a through silicon via (TSV) is used instead of wire bonding these days.

1 is a block diagram illustrating a general multi-chip package.

Referring to FIG. 1, a multi-chip package includes first to third semiconductor memory devices 110, 120, and 130, and a central processing unit 140.

The first to third semiconductor memory devices 110, 120, and 130 output data DAT_OUT in response to the read command RD transmitted from the CPU 140. Here, the first to third semiconductor memory devices 110, 120, and 130 receive the external clock signal CLK_EXT from the central processing unit 140, and use the external clock signal CLK_EXT as a source to perform data DAT_OUT. Outputs In this case, an internal clock signal generation circuit for generating an internal clock signal using the external clock signal CLK_EXT as a source is provided in each of the first to third semiconductor memory devices 110, 120, and 130. The data DAT_OUT is synchronized and output using a clock signal.

FIG. 2 is an operation waveform diagram for describing a data output operation of the first to third semiconductor memory devices 110, 120, and 130 of FIG. 1.

2 illustrates an external clock signal CLK_EXT, in which data is normally output (OUT_DAT1) and abnormally output (OUT_DAT2) in the first to third semiconductor memory devices 110, 120, and 130. It is. For reference, the sections 'A', 'B', and 'C' mean data output sections of each of the first to third semiconductor memory devices 110, 120, and 130.

As shown in FIG. 2, when data is normally output (OUT_DAT1), data does not overlap each other in the output periods A, B, and C of the first to third semiconductor memory devices 110, 120, and 130. However, when data is abnormally output (OUT_DAT2), a portion where data overlaps between the data output section B of the second semiconductor memory device 120 and the data output section C of the third semiconductor memory device 130 ( A dashed line) occurs.

Such overlapping data occurs when the data output time points of the first to third semiconductor memory devices 110, 120, and 130 are inconsistent with each other, and such a mismatch phenomenon is largely caused by a process change of each semiconductor memory device. Occurs. Subsequently, this inconsistency reduces the data validity period, causing data loss, and causing unnecessary current consumption due to unwanted data collision.

The present invention is to provide a multi-chip package for generating a common internal clock signal in any one of a plurality of semiconductor memory devices, the remaining plurality of semiconductor memory devices to output the data using the common internal clock signal as a source do.

According to an aspect of the present invention, a multi-chip package includes a plurality of semiconductor memory devices for outputting data to a central processing unit according to a read command, the external chip signal generated by the central processing unit A first through via for transferring a to a plurality of semiconductor memory devices; And a second through via connected to the plurality of semiconductor memory devices to transfer a common internal clock signal generated in the semiconductor memory device generated by any one of the plurality of semiconductor memory devices to the remaining semiconductor memory devices.

The semiconductor device may further include a third through via for transferring the data output from the plurality of semiconductor devices to the central processing unit.

According to another aspect of the present invention, a multi-chip package may include a first semiconductor memory device generating a first internal clock signal and synchronizing and outputting its data in response to the first internal clock signal; A signal transmission line for transmitting the first internal clock signal; And receiving the first internal clock signal from the signal transmission line, compensating for the delay amount reflected in the signal transmission line to generate a second internal clock signal, and output its own data in response to the second internal clock signal. A second semiconductor memory device for synchronizing and outputting is provided.

Preferably, the first semiconductor memory device further includes an output buffering unit for buffering and outputting the first internal clock signal, and the second semiconductor memory device includes an input buffering for receiving and buffering the first internal clock signal. It further comprises a wealth.

According to another aspect of the present invention, a method of operating a multi-chip package includes generating a common internal clock signal for synchronizing data in one of a plurality of semiconductor memory devices; And performing an operation corresponding to an external clock signal by using the common internal clock signal as a source in the remaining semiconductor memory devices of the plurality of semiconductor memory devices.

The method may further include compensating the common internal clock signal by the delay amount reflected in the through via in the remaining semiconductor memory device.

According to another aspect of the invention, the multi-chip package is a multi-chip package having a plurality of semiconductor memory devices, each of the plurality of semiconductor memory devices, in any one of the plurality of semiconductor memory devices An input buffering unit configured to receive the generated common internal clock signal through the through via; A phase comparator for comparing an output signal of the input buffering part and a feedback clock signal; A variable delay unit for generating an internal clock signal by reflecting a delay amount corresponding to an output signal of the phase comparator to an external clock signal; A delay replication modeling unit for generating the feedback clock signal by reflecting the delay amount of the through via to the internal clock signal; A common internal clock signal generator for generating the common internal clock signal; An output buffering unit for outputting the common internal clock signal through the through via; And a data synchronizer configured to synchronize and output data in response to the common internal clock signal or the internal clock signal.

Preferably, the semiconductor memory device generating a common internal clock signal among the plurality of semiconductor memory devices activates its output buffering unit, and the remaining semiconductor memory devices activate its input buffering unit.

According to another aspect of the invention, the multi-chip package is a multi-chip package having a plurality of semiconductor memory devices, each of the plurality of semiconductor memory devices, the external clock signal reflects the delay amount corresponding to the delay control signal A common variable delay unit for outputting the same; An output buffering unit for outputting an internal clock signal output from the variable delay unit through the through via; A common data synchronizer for synchronizing and outputting data in response to the internal clock signal; A DLL delay copy modeling unit configured to generate a first feedback clock signal by reflecting the internal clock signal as much as a modeled time; A TSV delay copy modeling unit for generating a second feedback clock signal by reflecting a delay amount of the through via to a common internal clock signal generated by one of the plurality of semiconductor memory devices; And a delay for generating the delay control signal by comparing a phase difference between the external clock signal and the first feedback clock signal or a phase difference between the common internal clock signal and the second feedback clock signal in response to a read command. And a control signal generator.

Preferably, the first buffering unit for buffering the external clock signal; And a second buffering unit for buffering the common clock signal, wherein the first and second buffering units are determined to be activated according to the read command.

According to another aspect of the present invention, a method of operating a multi-chip package includes: performing a first locking operation of generating an internal clock signal using an external clock signal as a source in each of a plurality of semiconductor memory devices; Inputting an internal clock signal generated by one of the plurality of semiconductor memory devices into each of the remaining semiconductor memory devices through a through via as a common internal clock signal; And performing a second locking operation of compensating the common internal clock signal by a delay amount reflected by the through via in the remaining semiconductor memory device, and generating a corresponding internal clock signal by using the common internal clock signal as a source. do.

Preferably, the one semiconductor memory device outputs data in response to the internal clock signal generated through the first locking operation, and each of the remaining semiconductor memory devices is configured to lock the second lock in the first locking operation state. The data may be output in response to a corresponding internal clock signal generated by reflecting the operation.

In the multi-chip package according to an embodiment of the present invention, a plurality of semiconductor memory devices perform a read operation by using a common internal clock signal generated by one of the plurality of semiconductor memory devices. It is possible to cause the data to be synchronized and output in response to one common internal clock signal.

Data output from a plurality of semiconductor memory devices is output in response to one common internal clock signal so that data transmitted to the central processing unit does not overlap each other, thereby obtaining an effect of maximizing a data valid period.

In addition, it is possible to obtain an effect that can prevent the unnecessary current consumption caused by the existing data collision.

1 is a block diagram illustrating a general multi-chip package.
FIG. 2 is an operation waveform diagram for describing a data output operation of the first to third semiconductor memory devices 110, 120, and 130 of FIG. 1.
3 is a block diagram illustrating a multi-chip package according to an embodiment of the present invention.
FIG. 4 is a block diagram illustrating the first and second semiconductor memory devices 320 and 330 of FIG. 3.
5 is a block diagram illustrating a multi-chip package according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

3 is a block diagram illustrating a multi-chip package according to an embodiment of the present invention.

Referring to FIG. 3, the multi-chip package includes a central processing unit 310 and first to third semiconductor memory devices 320, 330, and 340.

The CPU 310 transmits an external command such as a read command and an external clock signal CLK_EXT to the first to third semiconductor memory devices 320, 330, and 340. The external clock signal CLK_EXT is a clock signal generated by the central processing unit 210. The external clock signal CLK_EXT is a clock signal generated by the central processing unit 210. The first to third semiconductor memory devices 320, 330, 340.

The first to third semiconductor memory devices 320, 330, and 340 output data DAT_OUT according to a read command transmitted from the central processing unit 310. The multi-chip package according to an embodiment of the present invention generates a common internal clock signal CLK_CM in one of the first to third semiconductor memory devices 320, 330, and 340, and generates the remaining internal clock signal CLK_CM. The common internal clock signal CLK_CM may be received.

Hereinafter, for convenience of description, the common internal clock signal CLK_CM is generated in the first semiconductor memory device 320 as an example. That is, the common internal clock signal CLK_CM generated by the first semiconductor memory device 320 is input to the second and third semiconductor memory devices 330 and 340, and the second and third semiconductor memory devices 330 and 340. ) Uses the common internal clock signal CLK_CM as a source to synchronize and output the data DAT_OUT. In relation to the through silicon via, the external clock signal CLK_EXT is transferred from the central processing unit 310 to the first semiconductor memory device 320 through the first through silicon via TSV1 and the common internal clock signal CLK_CM. ) Is transferred from the first semiconductor memory device 320 to the second and third semiconductor memory devices 330 and 340 through the second through silicon via TSV2, and the data DAT_OUT is transferred to the third through silicon via TSV3. ) May be transferred from the first to third semiconductor memory devices 320, 330, and 340 to the central processing unit 310.

Hereinafter, a brief operation of the multi-chip package according to the embodiment of the present invention will be described.

First, the first semiconductor memory device 320 generates an internal clock signal through an internal clock signal generation circuit disposed therein. In the embodiment of the present invention, this internal clock signal is the common internal clock signal CLK_CM. Subsequently, the generated common internal clock signal CLK_CM is transmitted to the second and third semiconductor memory devices 330 and 340 through the second through silicon via TSV2. As will be described later, the second and third semiconductor memory devices 330 and 340 compensate the common internal clock signal CLK_CM by the amount of delay reflected in the second through silicon via TSV2, and use the second and third semiconductor memory devices 330 and 340 to compensate for the second and third semiconductor memory devices 330 and 340. A corresponding internal clock signal for synchronizing data output from the third semiconductor memory devices 330 and 340 is generated. Accordingly, the first semiconductor memory device 320 synchronizes and outputs data in response to the common internal clock signal CLK_CM, and the second and second semiconductor memory devices 330 and 340 output the common internal clock signal CLK_CM. Data is synchronized and output in response to each internal clock signal generated by the source.

FIG. 4 is a block diagram illustrating the first and second semiconductor memory devices 320 and 330 of FIG. 3, and an internal configuration of the first semiconductor memory device 320 and the second semiconductor memory device 330 is disclosed. have.

Referring to FIG. 4, the first semiconductor memory device 320 generates a first internal clock signal CLK1 and synchronizes and outputs the first internal data DAT_IN1 in response to the first internal clock signal CLK1. The external clock buffering unit 411 includes a common internal clock signal generator 412, an actual clock path 413, a data synchronization unit 414, and an output buffering unit 415.

The external clock buffering unit 411 buffers the external clock signal CLK_EXT input through the first through silicon via TSV1, and the common internal clock signal generator 412 outputs the output signal of the external clock buffering unit 411. Receives and generates an internal clock signal. Here, the common internal clock signal generator 412 may use a delay locked loop DLL. The internal clock signal generated as described above is transferred to the first internal clock signal CLK1 through the actual clock path 413 of the first semiconductor memory device 320. The data synchronizer 414 synchronizes the first internal data DAT_IN1 to the first internal clock signal CLK1 thus transmitted and outputs the same through the third through silicon via TSV3. Subsequently, the output buffering unit 415 buffers the first internal clock signal CLK1, and the buffered first internal clock signal CLK1 is a common internal clock through the second through silicon via TSV2, which is a signal transmission line. It is delivered as a signal CLK_CM.

Next, the second semiconductor memory device 330 receives the common internal clock signal CLK_CM and generates the second internal clock signal CLK2 by compensating for the delay amount reflected in the second through silicon via TSV2. The second internal data DAT_IN2 is synchronized and output in response to the second internal clock signal CLK2. The external clock buffering unit 421, the variable delay unit 422, and the actual clock path ( 423, a data synchronization unit 424, a common clock input buffering unit 425, a delay replica modeling unit 426, and a phase comparison unit 427.

The external clock buffering unit 421 buffers the external clock signal CLK_EXT input through the first through silicon via TSV1, and the variable delay unit 422 externally outputs a delay amount corresponding to the delay control signal CTR_DL. Reflected on the clock signal CLK_EXT. The delayed external clock signal CLK_EXT becomes the second internal clock signal CLK2 via the actual clock path 423 of the second semiconductor memory device 330. The data synchronizer 424 synchronizes the second internal data DAT_IN2 to the second internal clock signal CLK2 thus transmitted and outputs the same through the third through silicon via TSV3.

Meanwhile, the second semiconductor memory device 330 according to an exemplary embodiment of the present invention may compensate the common internal clock signal CLK_CM by the amount of delay reflected in the second through silicon via TSV2 and buffer the common clock input. The unit 425, the delay replica modeling unit 426, and the phase comparison unit 427 are configured for this purpose.

First, the common clock input buffering unit 425 buffers the common internal clock signal CLK_CM input through the second through silicon via TSV2, and the delay replica modeling unit 426 performs the second internal clock signal CLK2. ) To generate the feedback clock signal CLK_FD by reflecting the delay amount of the second through silicon via TSV2. The phase comparison unit 427 detects phases of the buffered common internal clock signal CLK_CM and the feedback clock signal CLK_FD to generate the delay control signal CTR_DL.

Through this configuration, the external clock signal CLK_EXT is delayed by the delay time of the common internal clock signal CLK_CM compared to the external clock signal CLK_EXT, and further delayed by the delay amount reflected in the second through silicon via TSV2. . That is, the second internal clock signal CLK2 is a signal obtained by compensating the common internal clock signal CLK_CM by a delay amount reflected by the second through silicon via TSV2. Accordingly, the common internal clock signal CLK_CM becomes a source signal for generating the second clock signal CLK2, and as a result, the second semiconductor memory device 330 uses the common internal clock signal CLK_CM as a source to determine the external clock signal ( Performs an operation corresponding to CLK_EXT).

4, the multi-chip package according to the exemplary embodiment of FIG. 4 generates a common internal clock signal CLK_CM from the first semiconductor memory device 320 and receives the same from the second semiconductor memory device 330. However, the multi-chip package according to the embodiment of the present invention generates a common internal clock signal CLK_CM in any one of a plurality of semiconductor memory devices, and the other semiconductor memory device receives the common internal clock signal CLK_CM from an external device. An operation corresponding to the clock signal CLK_EXT is performed. Therefore, each of the plurality of semiconductor memory devices must include a configuration for generating a common internal clock signal CLK_CM and a configuration for operating by receiving the common internal clock signal CLK_CM. That is, each of the plurality of semiconductor memory devices according to the exemplary embodiment of the present invention may include all components of the first and second semiconductor memory devices 320 and 330 of FIG. 4.

An operation when each of the plurality of semiconductor memory devices includes each component of the first and second semiconductor memory devices 320 and 330 is as follows.

First, the semiconductor memory device to which the first read command is applied generates a common internal clock signal CLK_CM and synchronizes data, and then outputs the data. Then, the remaining semiconductor memory device receiving the common internal clock signal CLK_CM receives the corresponding internal clock signal. Create and synchronize the data to output. At this time, the semiconductor memory device generating the common internal clock signal CLK_CM activates its output buffering unit for outputting the common internal clock signal CLK_CM, and each of the remaining semiconductor memory devices inputs the common internal clock signal CLK_CM. Activate your input buffering section for receiving.

As described above, the internal clock signal corresponding to each of the plurality of semiconductor memory devices is a clock signal that compensates for the delay amount reflected in the second through silicon via TSV2 to the common internal clock signal CLK_CM. As a result, the plurality of semiconductor memory devices synchronize and output data in response to one common internal clock signal CLK_CM.

5 is a block diagram illustrating a multi-chip package according to another embodiment of the present invention. For convenience of description, any one of a plurality of semiconductor memory devices provided in a multi-chip package will be described as a representative.

Referring to FIG. 5, the multi-chip package includes an external clock buffering unit 511, a common variable delay unit 512, an actual clock path 513, an output buffering unit 514, and a common data synchronization unit 515. ), A common clock input buffering unit 516, a delay control signal generation unit 517, a DLL delay replication modeling unit 518, and a TSV delay replication modeling unit 519.

The external clock buffering unit 511 buffers the external clock signal CLK_EXT transmitted through the first through silicon via TSV1 to generate the first buffered clock signal CLK_BF1, and the common variable delay unit 512 delays the delay. The delay amount corresponding to the control signal CTR_DL is reflected to the first buffering clock signal CLK_BF1 and output. The output signal is transferred to the internal clock signal CLK_INN through the actual clock path 513, and the output buffering unit 514 buffers the internal clock signal CLK_INN and passes through the second through silicon via TSV2. Output Subsequently, the common data synchronizer 515 synchronizes the data DAT_IN in response to the internal clock signal CLK_INN and outputs the same through the third through silicon via TSV3. The common clock input buffering unit 516 receives and buffers the common internal clock signal CLK_CM transmitted through the second through silicon via TSV2 from another semiconductor memory device to generate a second buffered clock signal CLK_BF2. do.

As described above, the common variable delay unit 512 delays the first buffered clock signal CLK_BF1 by a delay amount corresponding to the delay control signal CTR_DL, and the delay control signal CTR_DL is a delay control signal generator. Generated at 517.

The delay control signal generator 517 compares the phase difference between the external clock signal and the first feedback clock signal CLK_FD1 in response to the read command RD, or the common internal clock signal CLK_CM and the second feedback clock signal ( The phase difference of CLK_FD2 is compared to generate a delay control signal CTR_DL. Here, the first feedback clock signal CLK_FD1 is a signal reflecting the signal output from the common variable delay unit 512 as much as the time of modeling the actual clock path 513, and is generated by the DLL delay replication modeling unit 518. The second feedback clock signal CLK_FD2 is a signal in which the internal clock signal CLK_INN reflects the delay amount of the second through silicon via TSV2 and is generated by the TSV delay replica modeling unit 519.

Subsequently, the delay control signal generator 517 may include a first phase comparator 517_1 and a second buffered clock signal for comparing phases of the first buffered clock signal CLK_BF1 and the first feedback clock signal CLK_FD1. A second phase comparator 517_2 for comparing the phases of the CLKBF_2 and the second feedback clock signal CLK_FD2, and output signals of the first and second phase comparators 517_1 and 517_2 according to the read command RD. And a multiplexing unit 517_3 for multiplexing and outputting the delay control signal CTR_DL.

Hereinafter, the operation of the multichip package according to an embodiment of the present invention will be described. For convenience of description, each of the first and second semiconductor memory devices has a configuration as shown in FIG. 5, and generates a common internal clock signal CLK_CM in the first semiconductor memory device.

First, before the read command RD is applied to the plurality of semiconductor memory devices, each of the first and second semiconductor memory devices generates the internal clock signal CLK_INN using the first phase comparator 517_1. That is, the first semiconductor memory device generates its own internal clock signal (hereinafter referred to as 'first internal clock signal'), and the second semiconductor memory device also refers to its own internal clock signal (hereinafter referred to as 'second internal clock signal'). 'Is called.

Meanwhile, when a read command RD for a read operation of the first semiconductor memory device is activated, the first semiconductor memory device synchronizes and outputs the data DAT_IN using the first internal clock signal. The output buffering unit 514 of the memory device is activated. Therefore, the first internal clock signal is output as the common internal clock signal CLK_CM through the second through silicon via TSV2.

Subsequently, the second semiconductor memory device activates the common clock input buffering unit 516 of the second semiconductor memory device according to the read command RD, and transmits the common internal clock signal transmitted through the second through silicon via TSV2. It receives (CLK_CM). In this case, the second semiconductor memory device generates a second internal clock signal using the second phase comparator 517_2. Subsequently, when a read command RD for a read operation of the second semiconductor memory device is activated, the second semiconductor memory device synchronizes and outputs the data DAT_IN in response to the generated second internal clock signal.

As described above, the second internal clock signal of the second semiconductor memory device is an internal clock signal generated by using the first phase comparator 517_1 before the read command RD is applied and the read command RD. This is an internal clock signal generated using the second phase comparator 517_2 after it is applied.

In other words, in the method of operating the multi-chip package according to the exemplary embodiment of FIG. 5, the first locking operation is performed by using the first phase comparator 517_1 comparing the phase of the external clock signal CLK_EXT. The second locking operation is performed by using the second phase comparator 517_2 comparing the phases of the common internal clock signal CLK_CM. Since the first locking operation is slightly out of the desired locking state, in the embodiment of the present invention, it is possible to shorten the completion time of the locking by performing the second locking operation in the first locking operation state.

As described above, the multi-chip package according to the embodiment of the present invention generates the common internal clock signal CLK_CM in one of the semiconductor memory devices, and the common internal clock signal in the remaining semiconductor memory devices. By generating the internal clock signal using the CLK_CM, data is output from a plurality of semiconductor memory devices so that they do not overlap each other. As a result, it is possible to secure the data valid period as much as possible, and it is possible to prevent unnecessary current consumption caused by the collision of data.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

On the other hand, the through-silicon vias disclosed in the embodiment of the present invention have passed through a plurality of semiconductor memory devices as an example. However, in the present invention, a bump connected between each of the through silicon vias provided in each of the plurality of semiconductor memory devices and each of the through silicon vias may be regarded as the same configuration as that of one through silicon via as in the embodiment. .

310: multi-chip package the central processing unit
320: first semiconductor memory device
330: second semiconductor memory device
340: third semiconductor memory device

Claims (26)

In a multi-chip package having a plurality of semiconductor memory devices for outputting data to the central processing unit according to the read command,
First through vias configured to transfer external clock signals generated by the central processing unit to a plurality of semiconductor memory devices; And
A second through via connected to the plurality of semiconductor memory devices to transfer a common internal clock signal generated in the semiconductor memory device generated by any one of the plurality of semiconductor memory devices to the remaining semiconductor memory devices;
Multi chip package having a.
The method of claim 1,
And a third through via for transferring the data output from the plurality of semiconductor devices to the central processing unit.
A first semiconductor memory device generating a first internal clock signal and synchronizing and outputting its data in response to the first internal clock signal;
A signal transmission line for transmitting the first internal clock signal; And
The first internal clock signal is received from the signal transmission line, a second internal clock signal is generated by compensating for the delay amount reflected in the signal transmission line, and the own data is synchronized in response to the second internal clock signal. Second semiconductor memory device for outputting
Multi chip package having a.
The method of claim 3,
The first semiconductor memory device further includes an output buffering unit configured to buffer and output the first internal clock signal.
The second semiconductor memory device may further include an input buffering unit configured to receive and buffer the first internal clock signal.
The method of claim 3,
The second semiconductor memory device,
A delay replication modeling unit for generating a feedback clock signal by reflecting a delay amount of the signal transmission line in the second internal clock signal;
A phase comparator for comparing phases of the first internal clock signal and the feedback clock signal;
A variable delay unit configured to generate the second internal clock signal by reflecting a delay amount corresponding to an output signal of the phase comparator to an external clock signal; And
And a data synchronization unit for synchronizing and outputting its data in response to the second internal clock signal.
The method of claim 5,
The second internal clock signal may include a delay amount corresponding to an actual clock path of the second semiconductor memory device.
The method of claim 5,
And outputting data synchronized with the first internal clock signal in the first semiconductor memory device and output signals of the data synchronization unit through through vias.
The method of claim 3,
And the signal transmission line is a through via connected to the first and second semiconductor memory devices.
Generating a common internal clock signal for synchronizing data in any one of the plurality of semiconductor memory devices; And
Performing an operation corresponding to an external clock signal using the common internal clock signal as a source in the remaining semiconductor memory devices among the plurality of semiconductor memory devices;
Method of operation of a multi-chip package comprising a.
10. The method of claim 9,
The common internal clock signal is transmitted through a through via connected to the plurality of semiconductor memory devices.
The method of claim 10,
And compensating for the common internal clock signal by the delay amount reflected in the through via in the remaining semiconductor memory device.
10. The method of claim 9,
And generating a corresponding internal clock signal using the common internal clock signal as a source in the remaining semiconductor memory device.
The method of claim 12,
The one semiconductor memory device outputs data in response to the common internal clock signal, and the remaining semiconductor memory device outputs data in response to a corresponding internal clock signal.
In a multi-chip package having a plurality of semiconductor memory devices,
Each of the plurality of semiconductor memory devices,
An input buffering unit configured to receive a common internal clock signal generated by one of the plurality of semiconductor memory devices through a through via;
A phase comparator for comparing an output signal of the input buffering part and a feedback clock signal;
A variable delay unit for generating an internal clock signal by reflecting a delay amount corresponding to an output signal of the phase comparator to an external clock signal;
A delay replication modeling unit for generating the feedback clock signal by reflecting the delay amount of the through via to the internal clock signal;
A common internal clock signal generator for generating the common internal clock signal;
An output buffering unit for outputting the common internal clock signal through the through via; And
A data synchronizer for synchronizing and outputting data in response to the common internal clock signal or an internal clock signal
Multi-chip package comprising the.
15. The method of claim 14,
And a semiconductor memory device generating a common internal clock signal among the plurality of semiconductor memory devices to activate its output buffering unit, and the remaining semiconductor memory devices to activate their input buffering unit.
In a multi-chip package having a plurality of semiconductor memory devices,
Each of the plurality of semiconductor memory devices,
A common variable delay unit configured to reflect the delay amount corresponding to the delay control signal and output the external clock signal;
An output buffering unit for outputting an internal clock signal output from the variable delay unit through the through via;
A common data synchronizer for synchronizing and outputting data in response to the internal clock signal;
A DLL delay copy modeling unit configured to generate a first feedback clock signal by reflecting the internal clock signal as much as a modeled time;
A TSV delay copy modeling unit for generating a second feedback clock signal by reflecting a delay amount of the through via to a common internal clock signal generated by one of the plurality of semiconductor memory devices; And
A delay control for generating the delay control signal by comparing a phase difference between the external clock signal and the first feedback clock signal or comparing a phase difference between the common internal clock signal and the second feedback clock signal in response to a read command; Signal generator
Multi chip package having a.
17. The method of claim 16,
A first buffering unit for buffering the external clock signal; And
And a second buffering unit configured to buffer the common clock signal.
18. The method of claim 17,
The first and second buffering unit is a multi-chip package, characterized in that the activation is determined according to the read command.
17. The method of claim 16,
The read command is activated corresponding to each of the plurality of semiconductor memory devices.
17. The method of claim 16,
Wherein the delay control signal generator comprises:
A first phase comparator for comparing a phase difference between the external clock signal and the first feedback clock signal;
A second phase comparator for comparing a phase difference between the common internal clock signal and the second feedback clock signal; And
And a multiplexer for multiplexing output signals of the first and second phase comparators according to the read command and outputting the delayed control signals.
17. The method of claim 16,
And the internal clock signal reflects a delay amount corresponding to an actual clock path of a corresponding semiconductor memory device.
Performing a first locking operation of generating an internal clock signal using an external clock signal as a source in each of the plurality of semiconductor memory devices;
Inputting an internal clock signal generated by one of the plurality of semiconductor memory devices into each of the remaining semiconductor memory devices through a through via as a common internal clock signal; And
Performing a second locking operation of compensating the common internal clock signal by a delay amount reflected by the through via in the remaining semiconductor memory device, and generating a corresponding internal clock signal using the common internal clock signal as a source;
Method of operation of a multi-chip package comprising a.
The method of claim 22,
The performing of the first locking operation may include:
Comparing phases of the first feedback clock signal and the external clock signal reflected by a time of modeling an actual clock path of a corresponding semiconductor memory device; And
Generating the internal clock signal by delaying the external clock signal by a time corresponding to an output signal of the comparing phases.
The method of claim 22,
The performing of the second locking operation may include:
Comparing a phase of the second feedback clock signal reflected by the delay amount reflected in the through via and the common internal clock signal; And
Generating the corresponding internal clock signal by delaying the external clock signal by a time corresponding to the output signal of the comparing phases.
25. The method of claim 24,
The second feedback clock signal is a method of operating a multi-chip package, characterized in that the delay amount corresponding to the actual clock path of the semiconductor memory device is reflected.
The method of claim 22,
The one semiconductor memory device outputs data in response to the internal clock signal generated through the first locking operation, and each of the remaining semiconductor memory devices reflects the second locking operation in the first locking operation state. And outputting data in response to a corresponding internal clock signal generated by the corresponding method.
KR1020110092149A 2011-09-09 2011-09-09 Multi chip package and operating method thereof KR20130028530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110092149A KR20130028530A (en) 2011-09-09 2011-09-09 Multi chip package and operating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110092149A KR20130028530A (en) 2011-09-09 2011-09-09 Multi chip package and operating method thereof

Publications (1)

Publication Number Publication Date
KR20130028530A true KR20130028530A (en) 2013-03-19

Family

ID=48179022

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110092149A KR20130028530A (en) 2011-09-09 2011-09-09 Multi chip package and operating method thereof

Country Status (1)

Country Link
KR (1) KR20130028530A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140120033A (en) * 2013-04-02 2014-10-13 에스케이하이닉스 주식회사 Semiconductor device and semiconductor system having the semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140120033A (en) * 2013-04-02 2014-10-13 에스케이하이닉스 주식회사 Semiconductor device and semiconductor system having the semiconductor device

Similar Documents

Publication Publication Date Title
US9948310B2 (en) Methods and systems for clocking a physical layer interface
TWI472213B (en) Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
KR100273082B1 (en) Clock generator having dll and semiconductor device having clock generator
US20120242382A1 (en) Phase adjuster and semiconductor apparatus
US7868648B2 (en) On-die termination circuit, method of controlling the same, and ODT synchronous buffer
TW200407893A (en) Circuit and method for generating output control signal in synchronous semiconductor memory device
KR20130011355A (en) Semiconductor integrated circuit and method of transmitting signal thereof
KR101699787B1 (en) Delay-locked-loop circuit, semiconductor device and memory system having the delay-locked-loop circuit
TW201225542A (en) Apparatus for clock skew compensation
JP2008065884A (en) Semiconductor memory device and semiconductor device
US7050352B2 (en) Data input apparatus of DDR SDRAM and method thereof
US7605624B2 (en) Delay locked loop (DLL) circuit for generating clock signal for memory device
US8941425B2 (en) Semiconductor device compensating for internal skew and operating method thereof
TWI553779B (en) Integrated circuit system and memory system
KR20170075473A (en) Circuit for shifting signal, base chip and semiconductor system including same
KR20130028530A (en) Multi chip package and operating method thereof
Ke et al. Die-to-die clock synchronization for 3-D IC using dual locking mechanism
US6810486B2 (en) Method and apparatus for de-skewing a clock using a first and second phase locked loop and a clock tree
US8531896B2 (en) Semiconductor system, semiconductor memory apparatus, and method for input/output of data using the same
JP2003167778A (en) Control and address clock non-distributed memory system
US9300282B2 (en) Semiconductor device and semiconductor system including the same
US9251877B2 (en) Semiconductor apparatus for controlling phase difference between input signal and strobe signal
TWI816577B (en) Interface device and signal transceiving method thereof
KR20170108454A (en) Latency control device ans semiconductor device including the same
US9584106B2 (en) Semiconductor integrated circuit apparatus

Legal Events

Date Code Title Description
E902 Notification of reason for refusal
E601 Decision to refuse application