KR20130027851A - Semiconductor apparatus and semiconductor system using the same - Google Patents
Semiconductor apparatus and semiconductor system using the same Download PDFInfo
- Publication number
- KR20130027851A KR20130027851A KR1020110091337A KR20110091337A KR20130027851A KR 20130027851 A KR20130027851 A KR 20130027851A KR 1020110091337 A KR1020110091337 A KR 1020110091337A KR 20110091337 A KR20110091337 A KR 20110091337A KR 20130027851 A KR20130027851 A KR 20130027851A
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- South Korea
- Prior art keywords
- memory
- control signal
- controller
- relay
- group
- Prior art date
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
Abstract
The semiconductor device includes a first chip that receives a control signal from a controller and operates based on the control signal in response to a device selection signal or transmits the control signal to one or more other semiconductor devices.
Description
The present invention relates to a semiconductor device and a semiconductor system including the same.
As processing capacity and processing speed of semiconductor devices increase, a system in package for packaging a plurality of semiconductor devices into a single package has been developed. The system-in-package is externally recognized as a single semiconductor device, but internally, a plurality of semiconductor devices are connected to each other to operate as a system. In the case of a memory, a system in package may be manufactured by connecting a plurality of memory chips and a controller to configure a system.
1 is a view schematically showing the configuration of a system in a package according to the prior art. In FIG. 1, the semiconductor system includes a controller 10 (CPU) and a plurality of memories. The plurality of memories are directly connected to the
There is a method of mounting another memory in the empty space inside the package PKG, but this has to have a wire having a physical length different from that of the eight memories. The wiring as described above can not only generate a time difference when the
An object of the present invention is to provide a semiconductor device which communicates directly with a controller and which can relay communication between another semiconductor device and the controller, and a semiconductor system including the same.
A semiconductor device according to an embodiment of the present invention includes a first chip that receives a control signal from a controller and operates based on the control signal in response to a device selection signal or transmits the control signal to one or more other semiconductor devices. do.
A semiconductor device according to another embodiment of the present invention receives a control signal from a controller, transmits the control signal to one or more other semiconductor devices, and operates a first chip operating based on the control signal in response to a device selection signal. Include.
In addition, according to another embodiment of the present invention, a semiconductor device may include: a main port configured to communicate with a controller; A relay port connected to the main port and configured to communicate with another semiconductor device; And a relay unit transmitting a signal received from the main port to an internal circuit in response to a device selection signal.
In addition, according to another embodiment of the present invention, a semiconductor device may include: a main port configured to communicate with a controller; A relay port configured to communicate with another semiconductor device; And a relay unit connecting the main port to one of an internal circuit and the relay port in response to a device selection signal.
In addition, according to another embodiment of the present invention, a semiconductor device may include: a main port configured to communicate with a controller; A first relay port configured to communicate with a first semiconductor device; A second relay port configured to communicate with a second semiconductor device; And a relay unit transmitting a signal received from the main port to an internal circuit in response to a device selection signal.
A semiconductor system according to an embodiment of the present invention includes a controller; A first memory connected to the controller and operating by receiving a control signal from the controller; And a second memory connected to the first memory and operating by receiving the control signal from the first memory.
In addition, a semiconductor system according to another embodiment of the present invention is a controller; A first memory connected to the controller and operating by receiving a control signal from the controller; At least one second memory connected to the first memory and receiving the control signal from the first memory; And at least one third memory connected to the second memory and receiving the control signal from the second memory.
According to the present invention, the processing capacity of a semiconductor system can be improved regardless of the position where the semiconductor device is disposed. In addition, high speed operation of the semiconductor system can be realized.
1 is a view schematically showing the configuration of a system in a package according to the prior art,
2 is a view schematically showing a configuration of a semiconductor system according to an embodiment of the present invention;
FIG. 3 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 2;
4 is a block diagram showing a configuration of an embodiment of the relay unit of FIG. 3;
5 is a block diagram showing the configuration of another embodiment of the relay of FIG. 3;
6 schematically illustrates a configuration of a semiconductor system in accordance with another embodiment of the present invention;
FIG. 7 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 6;
8 is a schematic view showing the configuration of a semiconductor system in accordance with another embodiment of the present invention;
FIG. 9 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 8.
2 is a view schematically illustrating a configuration of a semiconductor system according to an embodiment of the present invention. In FIG. 2, the
The plurality of memories may be classified into a first group of memories MEMORY1 and a second group of memories MEMORY2. The memory MEMORY1 of the first group includes a bus (or channel BUS1) directly connected to the
The first memory group MEMORY1 is configured to have a relay function to enable communication between the
The memory of the first group MEMORY1 may be configured to transmit the control signal to the memory of the second group MEMORY2 as soon as the control signal is received, or in response to the device selection signal. The control signal may be transmitted to the memory MEMORY2 of the second group only when (MEMORY1) is not operated. The first and second groups of memories MEMORY1 and MEMORY2 perform data input / output operations in response to the control signal when they are instructed to operate in response to a device selection signal. The configuration of the first and second groups of memories MEMORY1 and MEMORY2 will be described in more detail below.
In an embodiment of the present disclosure, the second group of memories MEMORY2 may receive the control signal later than a predetermined time interval from the first group of memories MEMORY1. Accordingly, a problem may occur in that operation times of the first group of memories MEMORY1 and the second group of memories MEMORY2 may be different from each other. In an embodiment of the present invention, the
In an embodiment of the present invention, the physical length of the bus BUS1 between the
The
FIG. 3 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 2. In FIG. 3, the memory MEMORY1 includes a
The
In one embodiment, the
In one embodiment, the first group of memory includes a
4 is a block diagram schematically illustrating a configuration of an embodiment of the relay of FIG. 3. In FIG. 4, the
FIG. 5 is a block diagram schematically illustrating a configuration of another embodiment of the relay unit of FIG. 3. In the
6 is a diagram schematically showing the configuration of a
In FIG. 6, since the first and second groups of memories MEMORY1 and MEMORY2 are connected through a parallel bus, the first group of memories MEMORY1 and the second group of memories MEMORY2 are connected to each other. It may have a different structure. FIG. 7 is a diagram schematically illustrating a configuration of an embodiment of the
8 is a diagram schematically illustrating a configuration of a semiconductor system in accordance with another embodiment of the present invention. In FIG. 8, the
FIG. 9 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 8. In FIG. 9, the first group of memories MEMORY1 includes a
Any disclosed embodiment may be modified to include any structure or method disclosed in connection with other embodiments. In addition, the spirit of the present invention can be applied to various semiconductor systems that are not packaged as one, as well as a system in a package including a controller and a memory.
It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.
10/100:
310/710/910:
330/730/930: control
Claims (27)
And a plurality of chips, wherein the plurality of chips are stacked with the first chip to constitute the semiconductor device, and the plurality of chips are controlled by the first chip.
The first chip may include a control logic unit controlling the plurality of chips; And
And a relay unit which transmits the control signal to one of the control logic unit and the other semiconductor device in response to the device selection signal.
And a plurality of chips, wherein the plurality of chips are stacked with the first chip to constitute the semiconductor device, and the plurality of chips are controlled by the first chip.
The first chip may include a control logic unit controlling the plurality of chips; And
And a relay unit which transmits the control signal to the control logic unit in response to the device selection signal.
A relay port connected to the main port and configured to communicate with another semiconductor device; And
And a relay unit which transmits a signal received from the main port to an internal circuit in response to a device selection signal.
The repeater may include a repeater for buffering the control signal and outputting the control signal to the relay port; And
And a switch unit configured to output the control signal to the internal circuit in response to the device selection signal.
And a delay unit configured to delay an output of the switch unit by a predetermined time and output the delay unit to the internal circuit.
A relay port configured to communicate with another semiconductor device; And
And a relay unit connecting the main port with one of an internal circuit and the relay port in response to a device selection signal.
The relay unit may include a switch unit for outputting the control signal to one of the internal circuit and the relay port in response to the device selection signal; And
And a repeater which buffers an output of the switch unit and provides the buffer port to the relay port.
And a delay unit configured to delay an output of the switch unit for a predetermined time and output the delay unit to the internal circuit.
A first relay port configured to communicate with a first semiconductor device;
A second relay port configured to communicate with a second semiconductor device; And
And a relay unit which transmits a signal received from the main port to an internal circuit in response to a device selection signal.
The repeater may include a repeater for buffering the control signal and outputting the control signal to the first and second relay ports; And
And a switch unit configured to output the control signal to the internal circuit in response to the device selection signal.
And a delay unit configured to delay an output of the switch unit for a predetermined time and output the delay unit to the internal circuit.
A first memory connected to the controller and operating by receiving a control signal from the controller; And
And a second memory connected to the first memory and operating by receiving the control signal from the first memory.
And the first memory relays the control signal to the second memory and operates based on the control signal in response to a device selection signal.
And the first memory operates based on the control signal in response to a device selection signal or relays the control signal to the second memory.
And the first memory delays the control signal for a predetermined time and operates based on the delayed control signal.
And said predetermined time is substantially equal to a time interval until said control signal is relayed from said first memory and received by said second memory.
And the first memory converts the control signal communicated in series into a parallel control signal.
And the first memory is connected to the controller via a serial bus and to the second memory via a parallel bus.
The controller has location information of the first and second memories and communicates with the first and second memories by adjusting a latency according to the location information.
And a latency for communicating with the second memory is shorter than a latency for communicating with the first memory.
A first memory connected to the controller and operating by receiving a control signal from the controller;
At least one second memory connected to the first memory and receiving the control signal from the first memory; And
And at least one third memory connected to the second memory and receiving the control signal from the second memory.
The first memory may include a main port for receiving the control signal from the controller; And
And one or more relay ports for transmitting the control signal to the one or more second memories.
The at least one second memory may include a main port configured to receive the control signal from the first memory; And
At least one relay port for transmitting the control signal to the at least one third memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020110091337A KR20130027851A (en) | 2011-09-08 | 2011-09-08 | Semiconductor apparatus and semiconductor system using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020110091337A KR20130027851A (en) | 2011-09-08 | 2011-09-08 | Semiconductor apparatus and semiconductor system using the same |
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KR20130027851A true KR20130027851A (en) | 2013-03-18 |
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KR1020110091337A KR20130027851A (en) | 2011-09-08 | 2011-09-08 | Semiconductor apparatus and semiconductor system using the same |
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2011
- 2011-09-08 KR KR1020110091337A patent/KR20130027851A/en not_active Application Discontinuation
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