KR20130027851A - Semiconductor apparatus and semiconductor system using the same - Google Patents

Semiconductor apparatus and semiconductor system using the same Download PDF

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Publication number
KR20130027851A
KR20130027851A KR1020110091337A KR20110091337A KR20130027851A KR 20130027851 A KR20130027851 A KR 20130027851A KR 1020110091337 A KR1020110091337 A KR 1020110091337A KR 20110091337 A KR20110091337 A KR 20110091337A KR 20130027851 A KR20130027851 A KR 20130027851A
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South Korea
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memory
control signal
controller
relay
group
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KR1020110091337A
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Korean (ko)
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정춘석
이종천
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에스케이하이닉스 주식회사
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Publication of KR20130027851A publication Critical patent/KR20130027851A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

The semiconductor device includes a first chip that receives a control signal from a controller and operates based on the control signal in response to a device selection signal or transmits the control signal to one or more other semiconductor devices.

Description

Semiconductor device and semiconductor system using same {SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME}

The present invention relates to a semiconductor device and a semiconductor system including the same.

As processing capacity and processing speed of semiconductor devices increase, a system in package for packaging a plurality of semiconductor devices into a single package has been developed. The system-in-package is externally recognized as a single semiconductor device, but internally, a plurality of semiconductor devices are connected to each other to operate as a system. In the case of a memory, a system in package may be manufactured by connecting a plurality of memory chips and a controller to configure a system.

1 is a view schematically showing the configuration of a system in a package according to the prior art. In FIG. 1, the semiconductor system includes a controller 10 (CPU) and a plurality of memories. The plurality of memories are directly connected to the controller 10 through electrical wiring means. FIG. 1 shows that eight memories MEMORY are directly connected to the controller around the controller 10. However, the number of memories that can be connected to the controller 10 at physically the same distance is limited. Thus, a conventional system-in-package cannot increase processing capacity.

There is a method of mounting another memory in the empty space inside the package PKG, but this has to have a wire having a physical length different from that of the eight memories. The wiring as described above can not only generate a time difference when the controller 10 accesses each memory, but also makes it very difficult to adjust the time difference. Thus, the high speed operation of the system-in-package is created.

An object of the present invention is to provide a semiconductor device which communicates directly with a controller and which can relay communication between another semiconductor device and the controller, and a semiconductor system including the same.

A semiconductor device according to an embodiment of the present invention includes a first chip that receives a control signal from a controller and operates based on the control signal in response to a device selection signal or transmits the control signal to one or more other semiconductor devices. do.

A semiconductor device according to another embodiment of the present invention receives a control signal from a controller, transmits the control signal to one or more other semiconductor devices, and operates a first chip operating based on the control signal in response to a device selection signal. Include.

In addition, according to another embodiment of the present invention, a semiconductor device may include: a main port configured to communicate with a controller; A relay port connected to the main port and configured to communicate with another semiconductor device; And a relay unit transmitting a signal received from the main port to an internal circuit in response to a device selection signal.

In addition, according to another embodiment of the present invention, a semiconductor device may include: a main port configured to communicate with a controller; A relay port configured to communicate with another semiconductor device; And a relay unit connecting the main port to one of an internal circuit and the relay port in response to a device selection signal.

In addition, according to another embodiment of the present invention, a semiconductor device may include: a main port configured to communicate with a controller; A first relay port configured to communicate with a first semiconductor device; A second relay port configured to communicate with a second semiconductor device; And a relay unit transmitting a signal received from the main port to an internal circuit in response to a device selection signal.

A semiconductor system according to an embodiment of the present invention includes a controller; A first memory connected to the controller and operating by receiving a control signal from the controller; And a second memory connected to the first memory and operating by receiving the control signal from the first memory.

In addition, a semiconductor system according to another embodiment of the present invention is a controller; A first memory connected to the controller and operating by receiving a control signal from the controller; At least one second memory connected to the first memory and receiving the control signal from the first memory; And at least one third memory connected to the second memory and receiving the control signal from the second memory.

According to the present invention, the processing capacity of a semiconductor system can be improved regardless of the position where the semiconductor device is disposed. In addition, high speed operation of the semiconductor system can be realized.

1 is a view schematically showing the configuration of a system in a package according to the prior art,
2 is a view schematically showing a configuration of a semiconductor system according to an embodiment of the present invention;
FIG. 3 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 2;
4 is a block diagram showing a configuration of an embodiment of the relay unit of FIG. 3;
5 is a block diagram showing the configuration of another embodiment of the relay of FIG. 3;
6 schematically illustrates a configuration of a semiconductor system in accordance with another embodiment of the present invention;
FIG. 7 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 6;
8 is a schematic view showing the configuration of a semiconductor system in accordance with another embodiment of the present invention;
FIG. 9 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 8.

2 is a view schematically illustrating a configuration of a semiconductor system according to an embodiment of the present invention. In FIG. 2, the semiconductor system 1 includes a controller 100 and a plurality of memories. The memory includes, for example, memory chips such as DRAM, FLASH memory, but is not limited thereto, and may be any other type of memory chip. The memory chip may be a memory formed of a single chip, or a multi-chip memory formed by stacking a plurality of chips.

The plurality of memories may be classified into a first group of memories MEMORY1 and a second group of memories MEMORY2. The memory MEMORY1 of the first group includes a bus (or channel BUS1) directly connected to the controller 10, and directly communicates with the controller 100 through the bus BUS1. The second group of memories MEMORY2 does not include a bus that is directly connected to the controller 100. The second group of memory MEMORY2 communicates with the controller 100 through the first group of memory MEMORY1. That is, the memory MEMORY2 of the second group includes a bus BUS2 connected to the first memory group MEMORY1, and the controller (B) through the first memory group MEMORY1 and the bus BUS2. And indirectly communicate with 100).

The first memory group MEMORY1 is configured to have a relay function to enable communication between the controller 100 and the memory MEMORY2 of the second group. The memory MEMORY1 of the first group operates by receiving a control signal from the controller 10 through the bus BUS1. The control signal may include a command signal, data, an address signal, a device selection signal, and the like. The memory MEMORY1 of the first group transmits the control signal to the memory MEMORY2 of the second group.

The memory of the first group MEMORY1 may be configured to transmit the control signal to the memory of the second group MEMORY2 as soon as the control signal is received, or in response to the device selection signal. The control signal may be transmitted to the memory MEMORY2 of the second group only when (MEMORY1) is not operated. The first and second groups of memories MEMORY1 and MEMORY2 perform data input / output operations in response to the control signal when they are instructed to operate in response to a device selection signal. The configuration of the first and second groups of memories MEMORY1 and MEMORY2 will be described in more detail below.

In an embodiment of the present disclosure, the second group of memories MEMORY2 may receive the control signal later than a predetermined time interval from the first group of memories MEMORY1. Accordingly, a problem may occur in that operation times of the first group of memories MEMORY1 and the second group of memories MEMORY2 may be different from each other. In an embodiment of the present invention, the controller 100 preferably stores location information of the first and second groups of memories MEMORY1 and MEMORY2. That is, the controller 100 indicates, via the device selection signal, which memory of the first and second groups of memories MEMORY1 and MEMORY2 should be operated. Accordingly, when the device selection signal selects the memory MEMORY1 of the first group, the controller 100 may select the memory of the first group based on a general time interval, for example, a predetermined latency. Communicate with (MEMORY1). When the device selection signal selects the memory MEMORY2 of the second group, the controller 100 adjusts the latency in consideration of the location of the memory MEMORY2 of the second group. Accordingly, the controller MEMORY2 of the second group receives a control signal later than the memory MEMORY2 of the first group by a predetermined time and the data output from the memory MEMORY2 of the second group is also delayed by a predetermined time. Even if it reaches 100, the second group of memory MEMORY2 may communicate with the controller 100 substantially the same as the first group of memory MEMORY1.

In an embodiment of the present invention, the physical length of the bus BUS1 between the controller 100 and the memory MEMORY1 of the first group is the memory MEMORY1 of the first group and the memory MEMORY2 of the second group. Preferably equal to the physical length of the bus BUS2 between Accordingly, the time when the first group of memory MEMORY1 receives the control signal from the controller 100 and the control signal are relayed by the first group of memory MEMORY to allow the second group of memory ( The time at which MEMORY2) receives the control signal may be set substantially the same. If the time is equal to one period of the clock, the clock 1 is divided between the time when the first group of memory MEMORY1 receives the control signal and the time when the second group of memory MEMORY2 receives the control signal. There is a difference by period. At this time, when the controller 100 communicates with the memory of the first group MEMORY1 based on the latency corresponding to 10, the controller 100 determines that the second group of the second group is based on the latency corresponding to 9; Communicate with memory MEMORY2. Therefore, the communication time with the first and second groups of memories MEMORY1 and MEMORY2 can be adjusted more easily, and stable operation can be supported even when the semiconductor system 1 operates at high speed.

The semiconductor system 1 includes a first group of memory MEMORY1 that directly communicates with the controller 100 and relays communication between the controller 100 and the second group of memory MEMORY2. The number of memories included in the semiconductor system 1 may be increased without limitation. In addition, since there is no limitation of wiring between memories included in the semiconductor system, high-speed operation between the controller and the memory can be guaranteed. In particular, when the semiconductor system 1 is manufactured in a system-in-package, the configuration of the present invention may have further advantages.

FIG. 3 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 2. In FIG. 3, the memory MEMORY1 includes a first chip 300. The first chip 300 includes a main port 310, a relay port 320, a control logic unit 330, and a relay unit 340. The main port 310 is a channel for the first chip 300 to communicate with the controller 100. The relay port 320 is a channel through which the first chip 300 communicates with the memory MEMORY2 of the second group of FIG. 2. The control logic unit 330 is a circuit for receiving a control signal from the controller 100 to perform a data input / output operation. That is, the control logic unit 330 is an internal circuit of the memory MEMORY1. The logic controller 330 may include, but is not limited to, a circuit such as a command decoder, an address decoder, a data alignment unit, and a data processor such as a pipe latch. In addition, although the logic control circuit is representatively illustrated as a data input / output operation, the present invention is not limited thereto and is intended to include all kinds of operations that may be performed between the controller and the memory.

The relay unit 340 outputs the control signal received through the main port 310 to the relay port 320. The relay unit 340 also outputs the control signal to the control logic unit 330 in response to the device selection signal. When the device selection signal is a signal for selecting the first chip 300, the relay unit 340 outputs the control signal to the control logic unit 330 so that the first chip 300 performs data input / output operation. To do this. When the device selection signal is not a signal for selecting the first chip 300, the relay unit 340 does not output the control signal to the control logic unit 330. Therefore, in this case, another memory selected by the device selection signal will receive a control signal output from the relay port 320 to perform a data input / output operation.

In one embodiment, the relay unit 340 may be configured not to transmit the control signal to the relay port 320 when the device selection signal is a signal for selecting the first chip 300. In this case, when the memory MEMORY1 of the first group operates and the memory MEMORY2 of the second group does not operate, a control signal is transmitted from the memory MEMORY1 of the first group to the second memory group MEMORY2. It is possible to reduce the current consumption in the bus connecting the memory of the first group (MEMORY1) and the memory of the second group (MEMORY2) so as not to be transmitted.

In one embodiment, the first group of memory includes a first chip 300 and a plurality of stacked dies stacked with the first chip 300. In FIG. 3, the memory MEMORY1 is a multi-chip memory in which a plurality of chips are stacked. The first chip 300 and the stack die may be electrically connected to each other through a through via TSV. The first chip 300 may be a master chip that controls the stack dies. The first chip 300 may control the stack dies through the control logic unit 330. In this case, the first chip 300 may have the same structure as the stack dies, and may generally have a configuration that does not include a memory array in which data is actually stored. However, the present invention is not limited thereto, and the memory may have a configuration of various types of multi-chip memories. The memory of the second group MEMORY2 may have the same structure as the memory of the first group MEMORY1.

4 is a block diagram schematically illustrating a configuration of an embodiment of the relay of FIG. 3. In FIG. 4, the relay unit 340A includes a repeater 341A and a switch unit 342A. The repeater 341A buffers the control signal received through the main port 310 and outputs the buffered signal to the relay port 320. The switch unit 342A outputs the control signal to the control logic unit 330 in response to the device selection signal DS. In an alternative embodiment, the switch unit 342A may be commonly connected to an input terminal of the repeater 341A and an input terminal of the control logic unit 330. In the above configuration, the switch unit 342A does not output the control signal to the repeater 341A when the first chip 300 is selected by the device selection signal DS, thereby preventing the control signal. May not be transmitted to the memory MEMORY2 of the second group.

FIG. 5 is a block diagram schematically illustrating a configuration of another embodiment of the relay unit of FIG. 3. In the semiconductor system 1 of FIG. 3, it is illustrated that the controller 100 stores position information so that the latency can be adjusted in consideration of the positions of the first and second groups of memories MEMORY1 and MEMORY2. . The configuration of the relay unit 340B shown in FIG. 5 prevents the controller 100 from storing the location information of each memory to adjust the latency. In FIG. 5, the relay unit 340B includes a repeater 341B, a switch unit 342B, and a delay unit 343. The configuration and operation of the repeater 341B and the switch unit 342B are the same as in FIG. 4. The delay unit 343 delays the control signal output from the switch unit 342B for a predetermined time. The predetermined time is preferably a time until the control signal reaches the memory MEMORY2 of the second group through the memory MEMORY1 of the first group. That is, the delay unit 343 may substantially match the timing at which the control logic unit 330 of the first group of memory MEMORY1 and the control logic unit of the second group of memory MEMORY2 receive a control signal. Can be. The time at which the data output from the first and second groups of memories MEMORY1 and MEMORY2 arrive at the controller 100 may also substantially match.

6 is a diagram schematically showing the configuration of a semiconductor system 2 according to another embodiment of the present invention. In FIG. 6, one of the controller 100, one of the memory MEMORY1 of the first group, and one of the memory MEMORY2 of the second group is schematically illustrated. In the semiconductor system 2, the controller 100 and the memory MEMORY1 of the first group communicate with each other via a serial bus. In addition, the first group of memory MEMORY1 communicates with the second group of memory MEMORY2 via a parallel bus. The serial bus connecting the controller 100 and the memory MEMORY 1 of the first group is the same as the bus connection of a general semiconductor system. In the semiconductor system 2 according to the exemplary embodiment of the present invention, the first group of memory MEMORY1 and the second group of memory MEMORY2 are connected through a parallel bus. Communication speed between the controller 100 and the memory MEMORY2 of the second group when the memory of the first group MEMORY1 and the memory of the second group MEMORY2 communicate through a parallel bus. Can improve. In general, the controller and memory communicate over a serial bus. For example, in the case of data input, the controller sequentially transmits a plurality of data to the memory through a serial bus, and the memory internally converts the sequentially input data into parallel data and stores the data. Therefore, when the memory MEMORY1 of the first group converts data serially transmitted from the controller 100 into parallel data and transmits the data to the memory MEMORY2 of the second group, the operation of the semiconductor system 2 is performed. Can improve speed.

In FIG. 6, since the first and second groups of memories MEMORY1 and MEMORY2 are connected through a parallel bus, the first group of memories MEMORY1 and the second group of memories MEMORY2 are connected to each other. It may have a different structure. FIG. 7 is a diagram schematically illustrating a configuration of an embodiment of the memory MEMORY 1 of the first group of FIG. 6. In FIG. 7, the memory MEMORY1 of the first group includes the first chip 700 as in FIG. 3. However, unlike the first chip 700 of FIG. 7, the control logic unit 730 receives a control signal from the main port 710, and the relay unit 740 is the control logic unit 730. ) Is placed at the output stage. Therefore, the control signal transmitted through the serial bus (SERIAL BUS) is converted through the control logic unit 730 of the first chip 700, the converted control signal is the relay port 720 and the parallel bus ( The data may be transmitted to the memory MEMORY2 of the second group through the PARALLEL BUS. In one embodiment of the present invention, the second group of memories MEMORY2 need not include the same configuration as the control logic unit 730 of the first chip 700. Since the memory MEMORY2 of the second group receives the control signal converted by the control logic unit 730 of the first chip 700 through the parallel bus, the memory MEMORY2 does not have to have a separate control logic unit. do. Therefore, the second group of memory (MEMORY2) may be composed of a multi-chip memory including a chip 700 having a configuration of the relay unit in response to the device selection signal, stacked without having a chip operating as a master chip It may be composed of a multi-chip memory composed only of chips.

8 is a diagram schematically illustrating a configuration of a semiconductor system in accordance with another embodiment of the present invention. In FIG. 8, the semiconductor system 3 includes a controller 100, a first group of memory MEMORY1, and a second group of memory MEMORY2. The memory MEMORY1 of the first group communicates directly with the controller 100. The first group of memories MEMORY1 also relays communication between the controller 100 and a plurality of second groups of memories MEMORY2. The first group of memories MEMORY1 may transmit control signals received from the controller 100 to at least two or more second groups of memories MEMORY2. The second group of memories MEMORY2 may similarly transmit control signals received from the first group of memories MEMORY1 to the plurality of third groups of memories MEMORY3. In this case, while the relay of the first group of memories MEMORY1 and the second group of memories MEMORY2 are relayed, the number of memories that can communicate with the controller 100 may increase significantly.

FIG. 9 is a diagram schematically illustrating a configuration of an embodiment of a memory of a first group of FIG. 8. In FIG. 9, the first group of memories MEMORY1 includes a first chip 900. The first chip 900 includes a main port 910, first and second relay ports 921 and 922, a control logic unit 930, and a relay unit 940. Unlike FIG. 3, the first chip 900 of FIG. 9 has a plurality of relay ports. Accordingly, the first group of memories MEMORY1 may relay the control signal to a plurality of second groups of memories MEMORY2. Of course, the number of the relay ports is not limited to two, and a greater number of relay ports may be provided to transmit the control signals to a greater number of second groups of memories MEMORY2. The memory of the second group MEMORY2 and the memory of the third group MEMORY3 may also have the same configuration as the memory of the first group MEMORY1. Therefore, the processing capacity can be greatly increased while ensuring the high speed operation of the semiconductor system.

Any disclosed embodiment may be modified to include any structure or method disclosed in connection with other embodiments. In addition, the spirit of the present invention can be applied to various semiconductor systems that are not packaged as one, as well as a system in a package including a controller and a memory.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10/100: controller 300/700/900: first chip
310/710/910: main port 320/720/921/922: relay port
330/730/930: control logic section 340/740/940: relay section

Claims (27)

And a first chip that receives a control signal from a controller and operates based on the control signal in response to a device selection signal or transmits the control signal to one or more other semiconductor devices. The method of claim 1,
And a plurality of chips, wherein the plurality of chips are stacked with the first chip to constitute the semiconductor device, and the plurality of chips are controlled by the first chip. The method of claim 2,
The first chip may include a control logic unit controlling the plurality of chips; And
And a relay unit which transmits the control signal to one of the control logic unit and the other semiconductor device in response to the device selection signal. And a first chip that receives a control signal from a controller, transmits the control signal to one or more other semiconductor devices, and operates based on the control signal in response to a device selection signal. The method of claim 4, wherein
And a plurality of chips, wherein the plurality of chips are stacked with the first chip to constitute the semiconductor device, and the plurality of chips are controlled by the first chip. The method of claim 2,
The first chip may include a control logic unit controlling the plurality of chips; And
And a relay unit which transmits the control signal to the control logic unit in response to the device selection signal. A main port configured to communicate with a controller;
A relay port connected to the main port and configured to communicate with another semiconductor device; And
And a relay unit which transmits a signal received from the main port to an internal circuit in response to a device selection signal. The method of claim 7, wherein
The repeater may include a repeater for buffering the control signal and outputting the control signal to the relay port; And
And a switch unit configured to output the control signal to the internal circuit in response to the device selection signal. The method of claim 8,
And a delay unit configured to delay an output of the switch unit by a predetermined time and output the delay unit to the internal circuit. A main port configured to communicate with a controller;
A relay port configured to communicate with another semiconductor device; And
And a relay unit connecting the main port with one of an internal circuit and the relay port in response to a device selection signal. 11. The method of claim 10,
The relay unit may include a switch unit for outputting the control signal to one of the internal circuit and the relay port in response to the device selection signal; And
And a repeater which buffers an output of the switch unit and provides the buffer port to the relay port. The method of claim 11,
And a delay unit configured to delay an output of the switch unit for a predetermined time and output the delay unit to the internal circuit. A main port configured to communicate with a controller;
A first relay port configured to communicate with a first semiconductor device;
A second relay port configured to communicate with a second semiconductor device; And
And a relay unit which transmits a signal received from the main port to an internal circuit in response to a device selection signal. The method of claim 13,
The repeater may include a repeater for buffering the control signal and outputting the control signal to the first and second relay ports; And
And a switch unit configured to output the control signal to the internal circuit in response to the device selection signal. 15. The method of claim 14,
And a delay unit configured to delay an output of the switch unit for a predetermined time and output the delay unit to the internal circuit. controller;
A first memory connected to the controller and operating by receiving a control signal from the controller; And
And a second memory connected to the first memory and operating by receiving the control signal from the first memory. 17. The method of claim 16,
And the first memory relays the control signal to the second memory and operates based on the control signal in response to a device selection signal. 17. The method of claim 16,
And the first memory operates based on the control signal in response to a device selection signal or relays the control signal to the second memory. 17. The method of claim 16,
And the first memory delays the control signal for a predetermined time and operates based on the delayed control signal. The method of claim 19,
And said predetermined time is substantially equal to a time interval until said control signal is relayed from said first memory and received by said second memory. 17. The method of claim 16,
And the first memory converts the control signal communicated in series into a parallel control signal. 22. The method of claim 21,
And the first memory is connected to the controller via a serial bus and to the second memory via a parallel bus. 17. The method of claim 16,
The controller has location information of the first and second memories and communicates with the first and second memories by adjusting a latency according to the location information. 24. The method of claim 23,
And a latency for communicating with the second memory is shorter than a latency for communicating with the first memory. controller;
A first memory connected to the controller and operating by receiving a control signal from the controller;
At least one second memory connected to the first memory and receiving the control signal from the first memory; And
And at least one third memory connected to the second memory and receiving the control signal from the second memory. The method of claim 25,
The first memory may include a main port for receiving the control signal from the controller; And
And one or more relay ports for transmitting the control signal to the one or more second memories. The method of claim 25,
The at least one second memory may include a main port configured to receive the control signal from the first memory; And
At least one relay port for transmitting the control signal to the at least one third memory.
KR1020110091337A 2011-09-08 2011-09-08 Semiconductor apparatus and semiconductor system using the same KR20130027851A (en)

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