KR20130022433A - Post-ash sidewall healing - Google Patents
Post-ash sidewall healing Download PDFInfo
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- KR20130022433A KR20130022433A KR1020110083389A KR20110083389A KR20130022433A KR 20130022433 A KR20130022433 A KR 20130022433A KR 1020110083389 A KR1020110083389 A KR 1020110083389A KR 20110083389 A KR20110083389 A KR 20110083389A KR 20130022433 A KR20130022433 A KR 20130022433A
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- dielectric constant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Abstract
Description
The present invention relates to a method of manufacturing a semiconductor electronic device.
Integrated circuit fabrication methods have typically reached the point where hundreds of millions of transistors are formed on a single chip. Each new next-generation fabrication technique and equipment allows for commercial scale fabrication of much smaller and faster transistors, but increases the difficulty of fabricating much smaller and faster circuit elements. The shrinking dimensions of circuit elements far below the threshold of 50 nm now allow chip designers to develop new low-resistance conductive materials and new low-dielectric materials to improve (or simply maintain) the electrical performance of integrated circuits. Constant (ie low-k) insulating materials have been found.
Parasitic capacitance has become a major obstacle to transistor switching rates as the number of transistors per area increases. Capacitance is present between all adjacent electrically insulated conductors in an integrated circuit, switching whether or not the conductive portions are at the "front end" or "back end" of the manufacturing process flow. You can limit the speed.
Thus, new techniques and materials are needed to form low-k materials between adjacent conductors. One type of materials used to provide low-k separation between conductors is oxidized organo-silane films, such as Black Diamond ™ films commercially available from Applied Materials, Inc. of Santa Clara, California. . Such films have lower dielectric constants (eg, about 3.5 or less) than conventional spacer materials such as silicon oxides and nitrides. Unfortunately, some new processes include exposing low-k films to environments that can increase the effective dielectric constant and limit device performance.
Thus, new processes are needed to maintain a lower effective dielectric constant after exposure of low-k films to these environments.
Methods of reducing the effective dielectric constant present between two conductive components of an integrated circuit are described. The methods include the use of selective gas phase etch towards the oxygen-rich portion of the low-k dielectric layer. The etching rate is attenuated as the etching process reaches the low-k portion through the relatively high-k oxygen-rich portion. The etching process can be easily timed because the vapor phase etching process does not easily remove the desired low-k portion.
Embodiments of the present invention include methods of reducing the effective dielectric constant of a low-k dielectric material between two trenches on a patterned substrate in a substrate processing region. The low-k dielectric material forms the walls of the two trenches. The method includes transferring a patterned substrate into a substrate processing region. The method further includes vapor phase etching the patterned substrate to reduce the average dielectric constant of the low-k dielectric material by removing the outer dielectric layer from the low-k dielectric material.
Additional embodiments and features are set forth in part in the description that follows, and in part may be learned by practice of the embodiments apparent or presented to those skilled in the art upon examination of the present specification. The features and advantages of the presented embodiments can be realized and attained by the means, combinations, and methods described herein.
Further understanding of the features and advantages of the presented embodiments can be achieved with reference to the remaining parts and figures of this specification.
1A-1B are cross-sectional views of gaps during processing in accordance with the presented embodiments.
2 is a flow chart of a gapfill photoresist removal process in accordance with the presented embodiments.
3 is a cross-sectional view of a processing chamber in accordance with the presented embodiments.
4 is a processing system according to the presented embodiments.
In the appended figures, similar components and / or features may have the same reference label. Additionally, various components of the same type can be distinguished by following a reference label by a dashed line and a second label that distinguishes similar components. Where only the first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
Methods of increasing the effective dielectric constant present between two conductive components of an integrated circuit are described. The methods include the use of vapor phase etching selectively directed towards the oxygen-rich portion of the low-k dielectric layer. The etching rate is attenuated as the etching process reaches the low-k portion through the relatively high-k oxygen-rich portion. The etching process can be easily timed because the vapor phase etching process does not easily remove the desired low-k portion. Gas phase etchings are particularly desirable for liquid buffered oxide etchings for processing patterned substrates. Gas phase etchants are more easily removed from confined structures than liquid etchant.
Embodiments of the present invention are directed to methods of etching low-k materials on a patterned substrate to increase the effective dielectric constant and thus improve device performance. An exemplary process flow with the advantages of the methods presented herein includes two separate litho-etch patterns that are transferred to a substrate. These processes can be designed to pattern the substrate twice to achieve the desired step in the via structure rather than the traditional via with relatively straight vertical walls. Such process sequences may require coating the patterned substrate with the photoresist such that the photoresist penetrates vias and other gaps of the low-k material. Removing the photoresist typically involves ashing, ie, exposing the structure to an oxidizing precursor. While removing the gapfill photoresist, the ashing step also changes the sidewalls of the gap in a manner that increases the dielectric constant in the outer thin layer of low-k material. Some ashes include exposure to oxygen-containing compounds that are excited in the plasma. In such cases, oxygen treatment oxidizes the surface of the low-k material and increases the oxygen content relative to the carbon content. The methods presented herein remove this thin layer of relatively higher-k material to again reduce the dielectric constant near the pre-ash level.
In order to better understand and recognize the present invention, reference is made to FIGS. 1-2, which are cross-sectional views of gaps during processing and flowcharts for processing gaps in accordance with the presented embodiments. The structure shown in FIG. 1A is formed by a lithography-etch-lithography-etching sequence in which the second lithography-etching step opens a wider trench in the low dielectric constant material 110-1. The second etch penetrates only a portion of the direction of the trench to the bottom, leaving a step in the low-k material 110-1. Above and below the step are substantially vertical walls formed of low-k material. The walls may deviate from the theoretical vertical lines shown in FIGS. 1A-1B in the embodiments shown, but may be within 10 °, 5 ° or 2 ° of the vertical line. After the second etch, some
The reduced dielectric constant low-k material 110 can be restored to near the pre-ash level using the following steps. The patterned substrate is transferred to a substrate etching region of the processing chamber for further processing (operation 220). Flows of ammonia and nitrogen trifluoride are initiated in a plasma region separate from the treatment region (operation 222). The separated plasma region may be referred to herein as a remote plasma region and may be a compartment within the processing chamber or a module separate from the processing chamber. Remote plasma emissions (products from the remote plasma) are allowed to flow within the processing region and interact with the substrate surface (operation 225). The flow of plasma emissions reacts with the surface to produce a solid residue comprising material from the walls of the low-k material 110 that is affected and material from the plasma emissions. Detailed chemical reactions that may be useful in understanding this process will be provided in the exemplary equipment section. The solid residue is then removed by heating the patterned substrate above its sublimation point (operation 240). The process is completed by removing the patterned substrate from the substrate etch region (operation 245), and the resulting structure is shown in FIG. 1B.
The etch rate of the outer dielectric layer is greater than the relatively low-k dielectric material inside the outer dielectric layer. In embodiments of the present invention, the vapor phase etch rate of the outer dielectric layer exceeds the vapor phase etch rate of the remaining low-k dielectric material by a multiplicative factor greater than 25, 50, or 100. The thickness of the outer dielectric layer is, in embodiments, about 150 microns or less, about 100 microns or less, or about 50 microns or less.
The example process just described is a subset of the family of SiConi ™ etches, which generally comprise simultaneous flows of fluorine-containing precursor and hydrogen-containing precursor. Fluorine-containing precursors include, in different embodiments, nitrogen trifluoride, hydrogen fluoride, diatomic fluorine, monatomic fluorine, and fluorine-substituted hydrocarbons or combinations thereof. Hydrogen-containing precursors, in different embodiments, include atomic hydrogen, diatomic hydrogen, ammonia, hydrocarbons, incompletely halogen-substituted hydrocarbons, or combinations thereof. For simplicity, some discussions included herein may refer to exemplary SiConi ™ etching using a combination of nitrogen trifluoride and ammonia. Any SiConi ™ etch can be used in place of the example shown and described in FIG. 2. All SiConi ™ etching containing fluorine and hydrogen (but containing little or essentially no oxygen) shows a significant selectivity to the silicon oxide to be etched. These etching processes remove very slowly silicon, polysilicon and silicon oxycarbide. As a result, SiConi ™ has the additional advantage of leaving the desired silicon oxycarbide low-k material 110 essentially intact, even though the etching continues after silicon oxide is consumed from the walls of the low-k material 110. Have This selectivity allows the process to be timed rather than using any other form of endpoint determination.
Although the examples described herein relate to double patterning (LELE) of a low-k dielectric layer, other process flows may be possible that require a photoresist to be deposited in a gap in the low-k layer. As a result, the methods presented and claimed have utility in any application, including ashing of any gapfill material that provides itself with removal by oxidation treatment. Ashable gapfill materials include various photoresists and other similar carbon-containing materials as well as bottom or top anti-reflective coatings (BARC or TARC). Ashable gapfill materials are essentially oxygen free in the embodiments shown. The oxidation treatment removes the ashable gapfill material but undesirably deforms the walls, increasing the dielectric constant in the modified surface layer. The increased dielectric constant can be reduced using the methods described herein. The profile of the trenches may include a step structure on the trench wall as shown in FIGS. 1A-1B, but in other presented embodiments there is essentially no step.
As described above, the gaps and trenches are formed of a low-k material. The exemplary gap described has a step between two approximately vertical walls of low-k material (see FIG. 1). In other embodiments, no step is formed and one approximately vertical wall is formed of a low-k material. One vertical wall may be within 10 °, 5 ° or 2 ° of the vertical line in the presented embodiments. Before ashing (or after the treatments presented herein), the dielectric constant of the low-k material may be less than 3.9, 3.7, 3.5, 3.3 or 3.1 in the presented embodiments. The dielectric constant is mainly determined by the concentration of carbon in the silicon oxycarbide low-k layer. After ashing, the outer dielectric layer may have a dielectric constant greater than 3.0, 3.2 or 3.5, while the remainder of the low-k dielectric material is less than 3.0, 3.2 or 3.5, respectively, in accordance with embodiments of the present invention. Has a constant.
Optional steps may be used after gas phase etching. The vapor etching just described may leave post-etch residues containing portions of the vapor etchant. The presence of post-etch residues can lead to electrical leakage between adjacent conducting lines. The leakage can be caused, for example, by residues after fluorine-containing etching. Thus, the etched substrate is subsequently followed by plasma emissions from a plasma containing one or more of Ar, N 2 , NH 3 , and H 2 to remove some of the post-etch residues and mitigate any electrical leakage seen. Can be processed.
Oxygen radicals are used to remove the
Separate chambers are detailed for use in ashing and SiConi ™ etching. In an alternative embodiment, these processes are performed in the same chamber in a sequence of processing steps without removing the patterned substrate from the processing chamber.
Additional vapor etching process parameters and process details are presented in the course of describing the exemplary processing system.
Example Processing System
3 is a partial cross-sectional view illustrating an
In one embodiment, the
In one or more embodiments,
The
The vacuum system may include a
The
A gas supply panel (not shown) is typically used to provide process gas (s) to the
The
The temperatures of the substrate and
Other methods can be used to control the substrate temperature. The substrate may be heated by heating the support assembly 310 (or a portion thereof, such as a pedestal) by a resistive heater or some other means. In another configuration, the
During the etching processes described herein, the
Plasma emissions include various molecules, molecular fragments and ionized species. Currently welcomed theoretical mechanisms of SiConi ™ etching may or may not be accurate overall, but plasma emissions include NH 4 F and NH 4 F.HF which readily react with the low temperature substrates described herein. I think that. Plasma emissions can react with the silicon oxide surface to form (NH 4 ) 2 SiF 6 , NH 3 , and H 2 O products. NH 3 and H 2 O are vapors under the processing conditions described herein and may be removed from the treatment region 340 by the
After exposure to the plasma emissions and associated accumulation of solid byproducts on the vertical walls of the trenches (including stepped trenches) as a relatively higher-k thin film, the substrate may be heated to remove the byproducts. In embodiments, the
Ammonia (or hydrogen-containing precursors in general) has a flow rate of about 50 sccm to about 300 sccm, about 75 sccm to about 250 sccm, about 100 sccm to about 200 sccm or about 120 sccm to about 170 sccm in different embodiments. To the
Generation of plasma emissions occurs in
During the ashing process, reactive oxygen may be formed within the same chambers 361-362 or outside the processing chamber used to excite the etchant gases. Reactive oxygen may, in embodiments, contain atomic oxygen (O) and ozone (O 3 ) that flow with more stable molecular oxygen (O 2 ), a combination of which will be referred to herein as reactive oxygen. The flow rate of the reactive oxygen can be about 1 slm to about 50 slm, about 2 slm to about 30 slm, or about 5 slm to about 10 slm in different embodiments. The flow of reactive oxygen may be coupled with additional flow of relatively inert gas (eg, He, Ar) prior to entering the treatment region 340 through the aperture (s) 352. Relatively inert carrier gas may be included for various advantages including an increase in plasma density.
Treatment region 340 may be maintained at various pressures during the flow of ozone, oxygen, carrier gases and / or plasma emissions into treatment region 340. The pressure may be maintained at about 500 mTorr to about 30 Torr, about 1 Torr to about 10 Torr, or about 3 Torr to about 6 Torr in different embodiments. Lower pressures may also be used within the treatment region 340. The pressure may be maintained at about 500 mTorr or less, about 250 mTorr or less, about 100 mTorr or less, about 50 mTorr or less or about 20 mTorr or less in different embodiments.
In one or more embodiments, the
4 is a schematic top view of an exemplary
The
In an exemplary embodiment,
The process for depositing the film on the substrate or the process for cleaning the chamber 15 may be implemented using a computer program product executed by a controller. The computer program code may be written in any conventional computer readable programming language: for example, 68000 assembly language, C, C ++, Pascal, Fortran or others. Appropriate program code is entered into a single file or multiple files using a conventional text editor and stored or embedded in a computer usable medium, such as a memory system of a computer. If the code text entered is a high-level language, the code is compiled, and the resulting compiler code is then pre-compiled Microsoft Windows? Linked with the object code of the library routines. To execute the linked compilation object code, the system user calls the object code, causing the computer system to load the code in memory. The CPU then reads and executes the code to perform the tasks identified in the program.
The interface between the user and the controller may be via an inductive-touch monitor and may include a mouse and keyboard. In one embodiment two monitors are used, one mounted on a clean room wall for operators and the other behind the wall for service technicians. Two monitors can display the same information simultaneously, in which case only one is configured to accept input at a time. To select a particular screen or function, the operator touches a designated area on the display screen with a finger or a mouse. The touched area changes its highlighted color, or a new menu or screen is displayed, confirming the operator's selection.
As used herein, a “substrate” may be a support substrate with or without layers formed thereon. The support substrate can be a semiconductor or insulator of various doping concentrations and profiles, and can be, for example, a semiconductor substrate of the type used in the manufacture of integrated circuits. The layer of "silicon substrate" is used interchangeably and as an abbreviation for silicon- and oxygen-containing materials. Thus, silicon oxide may include concentrations of other basic components such as nitrogen, oxygen, carbon, and the like. In some embodiments, silicon oxide consists essentially of silicon and oxygen. A gas in an "excited state" details a gas in which at least some of the gas molecules are in vibrationally-excited, dissociated and / or ionized states. The gas may be a combination of two or more gases. The terms "trench" and "gap" are used throughout without implying that the etched geometry has a wide horizontal aspect ratio. When viewed from above the surface, the trenches and gaps may appear round, oval, polygonal, square, or various other shapes. The term "via" is used to refer to a low horizontal aspect ratio trench (viewed from above) that may or may not be filled with metal to form a vertical electrical connection.
Several embodiments have been presented, and it will be appreciated by those skilled in the art that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the presented embodiments. In addition, numerous known processes and elements have not been described in order to avoid unnecessarily obscuring the present invention. Accordingly, the foregoing description should not be considered as limiting the scope of the invention.
Where a range of values is provided, it is understood that the values intervening between each of the upper and lower limits of the range, as well as intervening values, are also specified unless the context clearly indicates otherwise. do. Each smaller range is included between any of the above-described values or values in between the above-mentioned ranges and any other above-mentioned or intervening values of the above-mentioned ranges. The upper and lower limits of these smaller ranges may be independently included or excluded in the range, and each range in which either or both of the limits are included in the smaller ranges or none is included in the present invention. , It is subject to any specifically excluded limit in the above-mentioned range. Where the above-mentioned range includes one or both of the limits, ranges excluding either or both of such included limits are also included.
As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "process" includes a plurality of such processes, and a reference to "dielectric material" refers to examples of one or more dielectric materials and their equivalents known to those of ordinary skill in the art, and the like. Include.
Also, the words "comprises" and "comprising" ("comprise", "comprising", "including" and "includes") are used in the specification and the claims below when used in the features, integers, Although intended to specify the presence of components, or steps, they do not disable the presence or addition of one or more other features, integers, components, steps, actions, or groups.
Claims (15)
The low-k dielectric material forms walls of the two trenches, the method comprising:
Transferring the patterned substrate into the substrate processing region; And
Gas phase etching the patterned substrate to reduce the average dielectric constant of the low-k dielectric material by removing an external dielectric layer from the low-k dielectric material
A method of reducing the effective dielectric constant of a low-k dielectric material comprising.
The vapor phase etching,
A fluorine-containing precursor and a hydrogen-containing precursor into the first remote plasma region fluidly connected to the substrate processing region, forming a plasma in the first remote plasma region to form plasma effluents Flowing the precursor;
Etching the patterned substrate by flowing the plasma emissions into the substrate processing region, forming solid byproducts on the surface of the substrate; And
Sublimating the solid by-products by increasing the temperature of the substrate above the sublimation temperature of the solid by-products,
A method of reducing the effective dielectric constant of low-k dielectric materials.
The fluorine-containing precursor comprises at least one precursor selected from the group consisting of nitrogen trifluoride, hydrogen fluoride, diatomic fluorine, monoatomic fluorine, and fluorine-substituted hydrocarbons.
A method of reducing the effective dielectric constant of low-k dielectric materials.
The hydrogen-containing precursor comprises at least one precursor selected from the group consisting of atomic hydrogen, molecular hydrogen, ammonia, hydrocarbons, and incomplete halogen-substituted hydrocarbons,
A method of reducing the effective dielectric constant of low-k dielectric materials.
Wherein the temperature of the substrate is raised above about 100 ° C. during the operation of subliming the solid by-products,
A method of reducing the effective dielectric constant of low-k dielectric materials.
The outer dielectric layer has a dielectric constant greater than 3.0, and the remaining low-k dielectric material has a dielectric constant of less than 3.0,
A method of reducing the effective dielectric constant of low-k dielectric materials.
The relatively high dielectric constant of the outer dielectric layer is caused by plasma ashing,
A method of reducing the effective dielectric constant of low-k dielectric materials.
Further ashing the patterned substrate prior to the operation of the vapor phase etching;
A method of reducing the effective dielectric constant of low-k dielectric materials.
The outer dielectric layer is removed from the walls of the two trenches,
A method of reducing the effective dielectric constant of low-k dielectric materials.
Ashing the patterned substrate is performed after the operation of transferring the patterned substrate into the substrate processing region;
A method of reducing the effective dielectric constant of low-k dielectric materials.
Plasma ashing the patterned substrate is performed prior to transferring the patterned substrate into the substrate processing region;
A method of reducing the effective dielectric constant of low-k dielectric materials.
The thickness of the outer dielectric layer is less than about 150 GPa,
A method of reducing the effective dielectric constant of low-k dielectric materials.
The etch rate of the outer dielectric layer during gas phase etching exceeds the etch rate of the remaining low-k dielectric material by a multiplicative factor greater than 50,
A method of reducing the effective dielectric constant of low-k dielectric materials.
After the gas phase etching of the patterned substrate, at least one of argon, nitrogen (N 2 ), ammonia (NH 3 ) or hydrogen (H 2 ) to remove post-etch residues Plasma-processing the patterned substrate in an atmosphere containing
A method of reducing the effective dielectric constant of low-k dielectric materials.
The post-etch residue contains fluorine,
A method of reducing the effective dielectric constant of low-k dielectric materials.
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KR1020110083389A KR20130022433A (en) | 2011-08-22 | 2011-08-22 | Post-ash sidewall healing |
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KR1020110083389A KR20130022433A (en) | 2011-08-22 | 2011-08-22 | Post-ash sidewall healing |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2015105673A1 (en) * | 2014-01-10 | 2015-07-16 | Applied Materials, Inc. | Recessing ultra-low k dielectric using remote plasma source |
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Publication number | Priority date | Publication date | Assignee | Title |
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WO2015105673A1 (en) * | 2014-01-10 | 2015-07-16 | Applied Materials, Inc. | Recessing ultra-low k dielectric using remote plasma source |
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