KR20130016696A - Thin film transistor substrate and method of fabricating the same - Google Patents

Thin film transistor substrate and method of fabricating the same Download PDF

Info

Publication number
KR20130016696A
KR20130016696A KR1020110078787A KR20110078787A KR20130016696A KR 20130016696 A KR20130016696 A KR 20130016696A KR 1020110078787 A KR1020110078787 A KR 1020110078787A KR 20110078787 A KR20110078787 A KR 20110078787A KR 20130016696 A KR20130016696 A KR 20130016696A
Authority
KR
South Korea
Prior art keywords
layer
thin film
film transistor
substrate
conductive
Prior art date
Application number
KR1020110078787A
Other languages
Korean (ko)
Inventor
홍기상
이재균
안용수
남경진
Original Assignee
엘지디스플레이 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지디스플레이 주식회사 filed Critical 엘지디스플레이 주식회사
Priority to KR1020110078787A priority Critical patent/KR20130016696A/en
Publication of KR20130016696A publication Critical patent/KR20130016696A/en

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

A thin film transistor substrate and a method of manufacturing the same are disclosed.
A thin film transistor substrate according to an embodiment of the present invention includes a thin film transistor formed on the substrate, a pixel electrode connected to the thin film transistor, and a common electrode forming a horizontal electric field with the pixel electrode, wherein the pixel electrode and the common electrode are conductive. A metal layer, a transparent conductive layer formed on the conductive metal layer, and a haze layer having a faster etching rate than the conductive metal layer and the transparent conductive layer on the transparent conductive layer.

Description

Thin film transistor substrate and manufacturing method therefor {THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a thin film transistor substrate, and to a thin film transistor substrate capable of forming a thin line pattern having a fine line width, and a manufacturing method thereof.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel for displaying an image through a liquid crystal cell matrix, and a driving circuit for driving the liquid crystal display panel.

The liquid crystal display is classified into a vertical electric field type and a horizontal electric field type according to the direction of the electric field for driving the liquid crystal.

The vertical field liquid crystal display drives a liquid crystal in twisted nematic (TN) mode by a vertical electric field formed between a pixel electrode and a common electrode disposed to face the upper and lower substrates. The vertical field liquid crystal display device has a large aperture ratio, but has a narrow viewing angle of about 90 degrees.

The horizontal field liquid crystal display drives liquid crystal in In Plane Switching (IPS) mode by a horizontal electric field between the pixel electrode and the common electrode arranged side by side on the lower substrate. The horizontal electric field liquid crystal display has an advantage that a viewing angle is about 160 degrees.

However, the horizontal field liquid crystal display has a disadvantage in that the aperture ratio between the pixel electrode and the common electrode is small because the pixel electrode and the common electrode are formed in a plurality of finger shapes in each pixel area. In order to increase the aperture ratio, line widths of the pixel electrode and the common electrode need to be reduced, but are limited by the exposure resolution in the photolithography process.

A general electrode forming method in a horizontal field liquid crystal display device is as follows.

A conductive layer is formed on the substrate, and a photoresist pattern is formed on the conductive layer. The photoresist pattern is formed by transferring the pattern of the mask to the photoresist in an exposure process, followed by a developing and baking process.

At this time, the minimum line width of the photoresist pattern is difficult to form smaller than the exposure resolution of the exposure equipment.

The conductive layer is etched by an etching process to form an electrode overlapping the photoresist pattern, and the photoresist pattern is removed by a stripping process.

At this time, when the conductive layer is over-etched due to the nature of the wet etching process and the electrode is formed to be smaller than the line width of the photoresist pattern, the minimum line width of the photoresist pattern is 4 μm. it's difficult.

As a result, since the minimum line widths of the pixel electrode and the common electrode of the horizontal field liquid crystal display are limited by the exposure resolution, there is a limit to improve the aperture ratio.

In addition, in the horizontal field liquid crystal display, the liquid crystal is driven by a horizontal electric field between the pixel electrode and the common electrode, but the liquid crystal positioned on the pixel electrode and the common electrode is not driven. The aperture ratio is reduced by the area of the pixel electrode and the common electrode.

An object of the present invention is to provide a thin film transistor substrate and a method of manufacturing the same to form a thin film pattern having a fine line width.

A thin film transistor substrate according to an embodiment of the present invention includes a thin film transistor formed on the substrate, a pixel electrode connected to the thin film transistor, and a common electrode forming a horizontal electric field with the pixel electrode, wherein the pixel electrode and the common electrode are conductive. A metal layer, a transparent conductive layer formed on the conductive metal layer, and a haze layer having a faster etching rate than the conductive metal layer and the transparent conductive layer on the transparent conductive layer.

According to an embodiment of the present invention, a method of manufacturing a thin film transistor substrate includes providing a substrate, forming a first conductive layer on the substrate, and a transparent second conductive layer on the entire surface of the substrate on which the first conductive layer is formed. Forming a haze layer on the transparent second conductive layer by performing hydrogen plasma treatment on the substrate on which the transparent second conductive layer is formed, and forming a photoresist pattern on the substrate on which the haze layer is formed. And etching the haze layer and the first and second conductive layers exposed by the photoresist pattern using the photoresist pattern as a mask to form one of a common electrode and a pixel electrode having a forward diagonal taper. And removing the photoresist pattern.

According to an embodiment of the present invention, a thin film transistor substrate and a method of manufacturing the same may include a pixel electrode including first and second conductive layers sequentially formed on the substrate, and a haze layer formed on the second conductive layer through plasma treatment; A common electrode is formed.

Therefore, the thin film transistor substrate and the method of manufacturing the same according to the embodiment of the present invention can improve the aperture ratio by forming a pixel electrode and a common electrode having a fine line width.

1 is a plan view schematically illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate obtained by cutting through I ′ and I ′ of FIG. 1.
3A and 3B are plan views and cross-sectional views illustrating a method of manufacturing the thin film transistor TFT shown in FIGS. 1 and 2.
4A and 4B are a plan view and a cross-sectional view for describing a method of manufacturing a protective film having a contact hole shown in FIGS. 1 and 2.
5A and 5B are plan and cross-sectional views illustrating a method of manufacturing the common electrode and the pixel electrode illustrated in FIGS. 1 and 2.
6A through 6F are cross-sectional views illustrating in detail a method of manufacturing the common electrode and the pixel electrode illustrated in FIGS. 5A and 5B.
7 is a flowchart sequentially illustrating a method of forming a fine pattern according to an embodiment of the present invention.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a plan view schematically illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate cut along lines I to I ′ of FIG. 1.

As shown in FIGS. 1 and 2, the thin film transistor substrate according to the embodiment of the present invention has a gate line GL and a data line DL formed to intersect with the gate insulating layer 103 therebetween on the insulating substrate 101. And a thin film transistor (TFT) adjacent to the intersection thereof.

In addition, the thin film transistor substrate according to the embodiment of the present invention further includes a pixel electrode 110 electrically connected to the thin film transistor TFT and a common electrode 120 forming a horizontal electric field with the pixel electrode 110. do.

The gate insulating layer 103 may include a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx). The gate insulating layer 103 may be formed not only as a single layer but also as a multilayer such as a silicon nitride layer covering the gate line GL and a silicon oxide layer formed on the silicon nitride layer.

The thin film transistor TFT provides the pixel electrode 110 with a data voltage supplied to the data line DL in response to a scan signal supplied to the gate line GL. As a result, the pixel electrode 110 charges and maintains the data voltage for a predetermined time.

To this end, the thin film transistor TFT includes a gate electrode 102, a source electrode 106, a drain electrode 108, an active layer 104a, and an ohmic contact layer 104b.

The gate electrode 102 is electrically connected to the gate line GL to supply a scan signal from the gate line GL. The gate line GL and the gate electrode 102 include aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and ITO ( Although it may be a single film made of Indium-Tin-Oxide), IZO (Indium-Zinc-Oxide), or an alloy thereof or the like, or a combination thereof, the present invention is not limited to the above examples.

The source electrode 106 is electrically connected to the data line DL to supply a data voltage from the data line DL. The drain electrode 108 is positioned to face the source electrode 106 and the active layer 104a to be electrically connected to the pixel electrode 110.

The drain electrode 108 supplies the data voltage from the data line DL to the pixel electrode 110.

The source and drain electrodes 106 and 108 and the data line DL may include aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), and tantalum ( Ta), ITO (Indium-Tin-Oxide), IZO (Indium-Zinc-Oxide) or a single film made of an alloy thereof or the like may be composed of a multi-layer consisting of a combination thereof.

The active layer 104a is formed to overlap the gate electrode 102 with the gate insulating layer 103 therebetween to form a channel between the source electrode 106 and the drain electrode 110.

The ohmic contact layer 104b is formed on the active layer 104a for ohmic contact with the source electrode 106 and the drain electrode 108 to form an active layer with each of the source and drain electrodes 106 and 108. Serves to reduce electrical contact resistance between the 104a.

In this case, the active layer 104a and the ohmic contact layer 104b constitute a semiconductor layer 104.

The pixel electrode 110 is formed in the pixel area defined by the intersection of the gate line GL and the data line DL.

The pixel electrode 110 includes a horizontal portion 113 arranged in parallel with the gate line GL, and a vertical portion 111 extending in the vertical direction from the horizontal portion 113.

The common electrode 120 is formed of the same material on the same plane as the pixel electrode 110 or of a different material or the same material on a different plane from the pixel electrode 110.

In this case, the vertical portion 111 and the common electrode 120 of the pixel electrode 110 may cross each other and may be formed in a zigzag shape or a stripe together with the data line DL.

For convenience, in the present invention, a case in which the common electrode 120 is formed of the same material on the passivation layer 105 that is the same plane as the pixel electrode 110 will be described as an example.

The common electrode 120 is electrically connected to the common line 130 to supply a common voltage through the common line 130.

Accordingly, a horizontal electric field is formed between the pixel electrode 110 supplied with the data voltage and the common electrode 120 supplied with the common voltage. The horizontal electric field causes liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate (not shown) to rotate by dielectric anisotropy. The light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing an image.

The pixel electrode 110 may include a first conductive pattern 110a made of a titanium-molybdenum alloy (MoTi), a second conductive pattern 110b formed on the first conductive pattern 110a, and made of a transparent conductive material. It includes a haze layer (110c) formed on the second conductive pattern (110b).

In this case, the haze layer 110c is formed to have a lower density than the first and second conductive patterns 110a and 110b so that the etching rate by the etching solution is faster than that of the first and second conductive patterns 110a and 110b. .

Similarly, the common electrode 120 includes a first conductive pattern 120a made of titanium molybdenum alloy (MoTi) and a second conductive pattern 120b formed on the first conductive pattern 120a and made of a transparent conductive material. And a haze layer 120c formed on the second conductive pattern 120b.

The haze layer 120c is formed to have a lower density than the first and second conductive patterns 120a and 120b such that the etching rate of the haze layer 120c is faster than that of the first and second conductive patterns 120a and 120b.

The pixel electrode 110 and the common electrode 120 are formed to form a forward oblique taper and have a fine line width, thereby reducing the area in which the liquid crystals on the common electrode 120 and the pixel electrode 110 are not driven, thereby improving the aperture ratio. .

Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention illustrated in FIGS. 1 and 2 will be described as an example.

3A and 3B are plan views and cross-sectional views illustrating a method of manufacturing the thin film transistor TFT shown in FIGS. 1 and 2.

3A and 3B, a first metal pattern including a gate line GL and a gate electrode 102 on the insulating substrate 101, an active layer 104a, and an ohmic contact layer 104b. A second metal pattern including a semiconductor pattern 104 and a data line DL and source and drain electrodes 106 and 108 is formed.

Specifically, the gate metal layer is sequentially formed on the insulating substrate 101 through a deposition method such as a sputtering method. The gate metal layer is formed of a metal such as aluminum-based metals (Al, AlNd), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), and the like.

Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a mask to form a first metal pattern including the gate line GL and the gate electrode 102.

Thereafter, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is entirely formed on the insulating substrate 101 on which the first metal pattern is formed, thereby forming the gate insulating layer 103.

Subsequently, an amorphous silicon layer and an amorphous silicon layer n + or p + implanted with impurities are sequentially formed on the insulating substrate 101 on which the gate insulating layer 103 is formed.

Subsequently, the semiconductor layer 104 including the active layer 104a and the ohmic contact layer 104b is formed by patterning the amorphous silicon layer and the amorphous silicon layer into which the impurities are implanted.

Subsequently, a source / drain metal layer is deposited on the insulating substrate 101 on which the semiconductor layer 104 is formed, and then the source / drain metal layer is patterned by a photolithography process to form the data line DL, the source and drain electrodes 106. , 108 to form a second metal pattern.

Subsequently, the ohmic contact layer 104b between the source electrode 106 and the drain electrode 108 is removed by using the source electrode 106 and the drain electrode 108 as a mask, thereby the active layer 104a. The channel region of is exposed.

The semiconductor layer 104 and the second metal pattern may be simultaneously formed through a photolithography process and an etching process using a slit mask or a diffraction mask.

4A and 4B are a plan view and a cross-sectional view for describing a method of manufacturing a protective film having a contact hole shown in FIGS. 1 and 2.

4A and 4B, a passivation layer 105 having a contact hole H is formed on an insulating substrate 101 on which the second metal pattern is formed.

Specifically, the protective film 105 is formed by forming an entire surface of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) or an organic insulating material such as BCB on the insulating substrate 101 on which the second metal pattern is formed. do.

Thereafter, the passivation layer 105 is patterned by a photolithography process and an etching process to form a contact hole H exposing the drain electrode 108 of the thin film transistor TFT.

5A and 5B are plan and cross-sectional views illustrating a method of manufacturing the common electrode and the pixel electrode illustrated in FIGS. 1 and 2.

5A and 5B, a third metal pattern including the pixel electrode 110 and the common electrode 120 is formed on the insulating substrate 101 on which the passivation layer 105 is formed.

Specifically, as illustrated in FIG. 6A, the first conductive layer 126a is formed on the insulating substrate 101 on which the protective film 105 is formed through a deposition method such as a sputtering method.

In this case, titanium molybdenum alloy is used as the first conductive layer 126a.

Subsequently, a transparent second conductive layer 126b is formed on the insulating substrate 101 on which the titanium molybdenum alloy conductive layer 126a is formed.

The second conductive layer 126b may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (ITO), SnO 2, and amorphous-indium tin oxide (a-). ITO) and the like are used.

Subsequently, as illustrated in FIG. 6B, the entire surface of the insulating substrate 101 on which the first and second conductive layers 126a and 126b are sequentially formed is subjected to hydrogen plasma treatment. Accordingly, indium oxide (In 2 O 3), which is a main component of the second conductive layer 126 b, and the hydrogen plasma are reacted to reduce indium oxide (In 2 O 3) as shown in Chemical Formulas 1 to 3 to haze the entire surface of the second conductive layer 126 b. Layer 126c is formed.

[Formula 1]

In 2 O 3 + 3H = 2In + 3H 2 O

[Formula 2]

In 2 O 3 + H 2 = 2 InO + H 2 O

(3)

In 2 O 3 + 2H 2 = 2InO + 2H 2 O

6C, the photoresist layer 180 is formed by applying photoresist to the entire surface of the insulating substrate 101 on which the haze layer 126c is formed.

In this case, the photoresist layer 180 will be described by using a positive type (Positive type) having a characteristic that the portion that receives the light is removed during development.

However, in the case where the light-receiving part is a negative type that is left during development, the position of the transmission area TA and the blocking area BA in the mask 200 will be described later. The same result can be achieved by using the modified mask type.

Subsequently, the mask 200 is positioned on the insulating substrate 101 on which the photoresist layer 180 is formed. The mask 200 includes a transmission area TA that transmits light and a blocking area BA that blocks light.

The blocking area BA of the mask 200 corresponds to the portion where the pixel electrode 110 (in FIG. 1) and the common electrode 120 (FIG. 1) are to be formed, and the transmission area TA corresponds to the remaining area.

Subsequently, development is performed on the photoresist layer (180 in FIG. 6C) exposed by the mask 200.

As illustrated in FIG. 6D, a photoresist pattern 181 corresponding to a portion where the pixel electrode 110 and the common electrode 120 are to be formed is formed on the insulating substrate 101 by the developing process.

In other areas, the photoresist layer (180 in FIG. 6C) is removed to expose a part of the haze layer 126c.

Next, as shown in FIG. 6E, the first and second conductive layers 126a and 126c and the haze layer 126c are sequentially etched by an etching process using the photoresist pattern 181 as a mask.

At this time, the haze layer 126c is formed on the entire surface of the second conductive layer 126b, so that not only the top surface of the haze layer 126c but also the side surface is used as an penetration path for the etching solution to etch the second conductive layer 126b. Speed up

In addition, an upper surface and a side surface of the second conductive layer 126b that are rapidly etched by the haze layer 126c are also used as penetration paths of the etching solution to form a first conductive layer (under the second conductive layer 126b). Increase the etching speed of 126a).

As described above, the haze layer 126c has the first and second conductive layers 126a because the density of the haze layer 126c is lower than that of the first and second conductive layers 126a and 126b. , 126b) is faster than the reaction rate with the etchant.

Meanwhile, the density of the haze layer 126c may be adjusted by adjusting the intensity of the hydrogen plasma so that the etch line widths of the haze layer 126c and the first and second conductive layers 126a and 126b may be adjusted. .

Accordingly, the haze layer 126c is etched to have a line width narrower than the line width of the photoresist pattern 181, and the first and second conductive layers 126a and 126b disposed under the haze layer 126c are formed. The haze layer 126c is etched using the mask to be etched to have a narrow line width.

The etch line width EW between the end of the photoresist pattern 181 and the ends of the first and second conductive layers 126a and 126b becomes wider and the first and second conductive layers 126a and 126b sequentially stacked. ) And the haze layer 126c are formed to form a forward oblique taper.

Subsequently, a strip is applied to the insulating substrate 101 on which the first and second conductive layers 126a and 126b and the haze layer 126c which form a forward diagonal taper are formed, as shown in FIG. 6F. The photoresist pattern (181 of FIG. 6E) is removed.

The first conductive patterns 110a and 120a, the second conductive patterns 110b and 120b, and the haze layers 110c and 120c are formed on the insulating substrate 101 from which the photoresist pattern has been removed.

The first conductive pattern 110a, the second conductive pattern 110b, and the haze layer 110c form the pixel electrode 110. In addition, the first conductive pattern 120a, the second conductive pattern 120b, and the haze layer 120c form the common electrode 120.

Then, annealing the insulating substrate 101 on which the pixel electrode 110 and the common electrode 120 are formed, the transmittances of the pixel electrode 110 and the common electrode 120 reduced by the haze layers 110c and 120c are reduced. Restores to a high level.

Line widths of the pixel electrode 110 and the common electrode 120 are formed to be about 1 to 2 μm. Accordingly, the area in which the liquid crystals on the common electrode 120 and the pixel electrode 110 are not driven decreases, thereby increasing the opening area, thereby improving transmittance and opening rate.

In addition, the pixel electrode 110 and the common electrode 120 include first conductive patterns 110a and 120a made of a titanium-molybdenum alloy having low reflection / low transmittance characteristics, and transparent second conductive patterns 110b and 120b. Since it is made of a double structure to minimize the defects compared to the case of a single layer has a fine line width.

7 is a flowchart sequentially illustrating a method of forming a fine pattern according to an embodiment of the present invention.

As shown in FIG. 7, a method of forming a fine pattern according to an embodiment of the present invention first forms a thin film transistor (TFT) on a substrate. (S300)

Subsequently, a passivation layer including a contact hole is formed on the thin film transistor TFT. (S310)

First and second metal layers are sequentially formed on the substrate on which the protective layer is formed. In this case, the first metal layer includes a conductive material made of a titanium-molybdenum alloy, and the second metal layer includes a transparent conductive material.

Plasma treatment is performed on the substrate on which the first and second metal layers are sequentially formed. (S330)

A haze layer is formed on the second metal layer by reacting indium oxide (In 2 O 3), which is a main component of the second metal layer, with a hydrogen plasma by the plasma treatment. (S340)

After applying the photoresist (PR) on the substrate on which the haze layer is formed, a photoresist process using a mask is performed to form a photoresist pattern. (S350)

Subsequently, wet etching using an etchant is performed (S360), and the photoresist pattern is removed. (S370)

Through this method, a pattern having a fine line width can be formed on the substrate.

Meanwhile, the present invention has been described using a horizontal field application type thin film transistor substrate having a pixel electrode 110 and a common electrode 120 as an example, and can be applied to any device requiring a thin film pattern having a fine line width.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

101: insulating substrate 102: gate electrode
103: gate insulating film 104: semiconductor layer
105: protective film 106: source electrode
108: drain electrode 110: pixel electrode
110a and 120a: first conductive pattern 110b and 120b: second conductive pattern
110c, 120c: Haze layer 120: Common electrode
180: photoresist layer 181: photoresist pattern
200: mask

Claims (10)

A thin film transistor formed on a substrate;
A pixel electrode connected to the thin film transistor; And
And a common electrode forming a horizontal electric field with the pixel electrode.
The pixel electrode and the common electrode may include a conductive metal layer, a transparent conductive layer formed on the conductive metal layer, and a haze layer having a faster etching rate than the conductive metal layer and the transparent conductive layer on the transparent conductive layer. Thin film transistor substrate. The method according to claim 1,
And the conductive metal layer, the transparent conductive layer and the haze layer form a forward oblique taper. The method according to claim 1,
The conductive metal layer is a thin film transistor substrate, characterized in that the titanium-molybdenum (MoTi) alloy. The method according to claim 1,
The transparent conductive layer may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (ITO), SnO 2, or amorphous pulse indium tin oxide (a-ITO). Thin film transistor substrate, characterized in that consisting of any one. The method according to claim 1,
The density of the haze layer is a thin film transistor substrate, characterized in that lower than the density of the transparent conductive layer and the conductive metal layer. Providing a substrate;
Forming a first conductive layer on the substrate;
Forming a transparent second conductive layer on an entire surface of the substrate on which the first conductive layer is formed;
Forming a haze layer on the transparent second conductive layer by performing hydrogen plasma treatment on the substrate on which the transparent second conductive layer is formed;
Forming a photoresist pattern on the substrate on which the haze layer is formed;
Etching the haze layer and the first and second conductive layers exposed by the photoresist pattern using the photoresist pattern as a mask to form one of a common electrode and a pixel electrode having a forward oblique taper; And
Removing the photoresist pattern; a method of manufacturing a thin film transistor substrate comprising: a. The method of claim 6,
The etching rate of the haze layer is faster than the etching rates of the first and second conductive layers, the method of manufacturing a thin film transistor substrate. The method of claim 6,
The density of the haze layer is a method of manufacturing a thin film transistor substrate, characterized in that lower than the density of the first and second conductive layer. The method of claim 6,
The first conductive layer is a method of manufacturing a thin film transistor substrate, characterized in that the titanium-molybdenum (MoTi) alloy. The method of claim 6,
The transparent second conductive layer may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (ITO), SnO 2, and amorphous pulse indium tin oxide (a-ITO). Method for manufacturing a thin film transistor substrate, characterized in that consisting of any one of).
KR1020110078787A 2011-08-08 2011-08-08 Thin film transistor substrate and method of fabricating the same KR20130016696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110078787A KR20130016696A (en) 2011-08-08 2011-08-08 Thin film transistor substrate and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110078787A KR20130016696A (en) 2011-08-08 2011-08-08 Thin film transistor substrate and method of fabricating the same

Publications (1)

Publication Number Publication Date
KR20130016696A true KR20130016696A (en) 2013-02-18

Family

ID=47895998

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110078787A KR20130016696A (en) 2011-08-08 2011-08-08 Thin film transistor substrate and method of fabricating the same

Country Status (1)

Country Link
KR (1) KR20130016696A (en)

Similar Documents

Publication Publication Date Title
JP4881368B2 (en) Manufacturing method of liquid crystal display device
KR101250319B1 (en) Fringe field switching mode liquid crystal display device and Method of fabricating the same
KR101492106B1 (en) Liquid crystal display device and manufacturing method thereof
KR101772511B1 (en) Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same
US7023017B2 (en) Thin film transistor substrate of horizontal electric field type liquid crystal display device and fabricating method thereof
JP4644179B2 (en) Array substrate for liquid crystal display device and manufacturing method thereof
US10192904B2 (en) Array substrate and manufacturing method thereof, display device
KR101137861B1 (en) Thin film transister of fringe field switching type and fabricating method thereof
US20120086009A1 (en) Array Substrate for Fringe Field Switching Mode Liquid Crystal Display Device and Method of Manufacturing the Same
US20150255327A1 (en) Manufacturing method of liquid crystal display
JP2006018281A (en) Method of manufacturing thin-film transistor panel
KR20170052801A (en) Display device and manufacturing method thereof
US8576367B2 (en) Liquid crystal display panel device with a transparent conductive film formed pixel electrode and gate pad and data pad on substrate and method of fabricating the same
KR20100059508A (en) Pad array of liquid crystal display device
KR20080050679A (en) Method of manufacturing thin film transistor substrate
KR101626899B1 (en) Thin film transistor substrate and method of fabricating the same
KR101320651B1 (en) Method of Fabricating Liquid Crystal Display Panel Of Horizontal Electronic Fileld Applying Type
KR20120075207A (en) Method for fabricating array substrate for liquid crystal display device of touch panel in cell type and method for the same
US7388226B2 (en) Liquid crystal display of horizontal electronic field applying type and fabricated method thereof
US9595542B2 (en) Thin film transistor array panel and manufacturing method thereof
KR102001056B1 (en) Array Substrate Including Oxide Thin Film Transistor And Method Of Fabricating The Same
US8476093B2 (en) Method of manufacturing a display substrate
KR20070073296A (en) Liquid crystal display and manufacturing method thereof
KR20130016696A (en) Thin film transistor substrate and method of fabricating the same
KR101086121B1 (en) In plane switching mode liquid crystal display device and method for fabricating thereof

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination