KR20130012739A - Voltage generator of semiconductor intergrated circuit - Google Patents

Voltage generator of semiconductor intergrated circuit Download PDF

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Publication number
KR20130012739A
KR20130012739A KR1020110074079A KR20110074079A KR20130012739A KR 20130012739 A KR20130012739 A KR 20130012739A KR 1020110074079 A KR1020110074079 A KR 1020110074079A KR 20110074079 A KR20110074079 A KR 20110074079A KR 20130012739 A KR20130012739 A KR 20130012739A
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South Korea
Prior art keywords
voltage
bit line
line precharge
activation signal
signal
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KR1020110074079A
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Korean (ko)
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임종만
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에스케이하이닉스 주식회사
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Priority to KR1020110074079A priority Critical patent/KR20130012739A/en
Publication of KR20130012739A publication Critical patent/KR20130012739A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

According to an embodiment of the present invention, a voltage generator of a semiconductor integrated circuit may generate an activation signal having a first level when the bit line precharge voltage is higher than the reference voltage by comparing a bit line precharge voltage with a reference voltage. A configured enable unit, a first voltage level maintenance signal for inducing a rise in the bit line precharge voltage, a second voltage level maintenance signal for inducing a fall in the bit line precharge voltage and the bit in response to the activation signal A voltage driver configured to generate a line precharge voltage and a drive control unit configured to control the bit line precharge voltage to a constant voltage level in response to the activation signal and the first and second voltage level maintenance signals.

Description

Voltage generator of semiconductor integrated circuit {Voltage Generator of Semiconductor Intergrated Circuit}

The present invention relates to a semiconductor memory device, and more particularly to a voltage generating device of a semiconductor integrated circuit.

The semiconductor integrated circuit, which is one of the semiconductor integrated circuits, uses a core voltage Vcore, a bit line precharge voltage Vblp, a cell plate voltage Vcp, and the like as an internal voltage.

Among the internal voltages, the bit line precharge voltage Vblp is a voltage used to precharge the bit line transferring the data amplified by the sense amplifier. The cell plate voltage Vcp is a voltage used for substrate biasing.

In general, the bit line precharge voltage Vblp and the cell plate voltage Vcp use a 1/2 core voltage Vcore, and the bit line precharge voltage Vblp equalizes a sense amplifier. Is used to minimize power consumption. The cell plate voltage Vcp is used to secure data storage reliability of a cell capacitor by supplying a 1/2 core voltage Vcore across both cell capacitors in which a memory of a semiconductor integrated circuit is stored. do.

1 is a circuit diagram of a voltage generator according to the prior art.

The conventional voltage generator includes a reference voltage generator 10 which generates a low reference voltage lv_L having a 1/3 core voltage Vcore level and a high reference voltage lv_H having a 2/3 core voltage Vcore level. And a voltage generator 20 that generates the bit line precharge voltage Vblp.

The voltage generator 20 compares the low reference voltage lv_L with the bit line precharge voltage Vblp, and if the bit line precharge voltage Vblp is lower than the low reference voltage lv_L, the PMOS driver PDRV. NMOS differential amplifier 21, which raises the voltage to the low reference voltage lv_L and the high reference voltage lv_H, and the bit line precharge voltage Vblp, When the voltage is higher than the reference voltage lv_H, the PMOS differential amplifier 22 operates the NMOS driver NDRV to lower the voltage up to the high reference voltage lv_H.

2 is a graph comparing a core voltage Vcore versus a bit line precharge voltage Vblp of a conventional device for generating a bit line precharge voltage Vblp.

The bit line precharge voltage Vblp generator according to the related art forms a dead zone in which the bit line precharge voltage Vblp is not generated even when a core voltage Vcore is applied to thereby detect the sense amplifier. Lowers.

In addition, when the bit line precharge voltage Vblp is generated using the 1/2 core voltage as a reference voltage to remove the dead zone, the NMOS driver NDRV and the PMOS driver PDRV are turned on at the same time to generate a voltage. The bit line precharge voltage Vblp output from the unit 20 does not stably output, but a ringing phenomenon occurs in which the voltage rises and falls repeatedly. There was a problem that the current consumption is increased.

The present invention has been made to solve the above-described problem, and provides a voltage generator of a semiconductor integrated circuit capable of generating a stable level of voltage without a dead zone.

According to an embodiment of the present invention, a voltage generator of a semiconductor integrated circuit may generate an activation signal having a first level when the bit line precharge voltage is higher than the reference voltage by comparing a bit line precharge voltage with a reference voltage. A configured enable unit, a first voltage level maintenance signal for inducing a rise in the bit line precharge voltage, a second voltage level maintenance signal for inducing a fall in the bit line precharge voltage and the bit in response to the activation signal A voltage driver configured to generate a line precharge voltage and a drive control unit configured to control the bit line precharge voltage to a constant voltage level in response to the activation signal and the first and second voltage level maintenance signals.

The voltage generator of the semiconductor integrated circuit according to the present invention can reduce current consumption and generate a stable level of voltage.

1 is a circuit diagram of a voltage generator of a semiconductor integrated circuit according to the prior art;
2 is a graph comparing a core voltage Vcore versus a bit line precharge voltage Vblp according to the related art.
3 is a schematic view showing a voltage generator of a semiconductor integrated circuit according to an embodiment of the present invention;
4 is a configuration diagram showing in detail a voltage generating device of a semiconductor integrated circuit according to an embodiment of the present invention;
5 is a graph comparing core voltage Vcore versus bit line precharge voltage Vblp according to an exemplary embodiment of the present invention.

3 is a configuration diagram schematically illustrating a voltage generator of a semiconductor integrated circuit according to an embodiment of the present invention.

The voltage generation device of the semiconductor integrated circuit compares the bit line precharge voltage Vblp and the 1/2 core voltage (1/2 * Vcore) so that the bit line precharge voltage VblP is 1/2 core voltage (1 / When lower than 2 * Vcore, the first activation signal EN having a low level (PMOS turn-on voltage) and the first activation signal are inverted to generate a second activation signal / EN having a high level (NMOS turn-on voltage). It includes an enable unit 300 to.

In addition, the first activation signal EN and the second activation signal / EN generated by the enable unit 300 compare the bit line precharge voltage Vblp with the 1/2 core voltage to compare the bit line precharge voltage. When Vblp is higher than 1/2 core voltage, the first activation signal EN having the high level and the first activation signal EN may be inverted to become the second activation signal / EN having the low level.

First, when the bit line precharge voltage Vblp is lower than the 1/2 core voltage by comparing the bit line precharge voltage Vblp with the 1/2 core voltage, the voltage driver 100 is connected to the enable unit 300. To receive a 1/2 core voltage in response to the first activation signal EN having a low level and the second activation signal / EN having a high level to induce an increase in the bit line precharge voltage Vblp. A first voltage level maintenance signal Vpdr, a second voltage level maintenance signal Vndr and a bit line precharge voltage Vblp for inducing a drop in the bit line precharge voltage Vblp are generated.

The driving controller 200 may include a second activation signal / EN input from the enable unit 300, a first voltage level maintenance signal Vpdr and a second voltage level maintenance signal input from the voltage driver 100. In response to Vndr, the bit line precharge voltage Vblp is maintained at a constant voltage level.

Specifically, the driving controller 200 applies a second activation signal / EN to the gate to adjust the amount of current flowing between the core voltage Vcore connected to the source and the first voltage level maintenance signal Vpdr connected to the drain. The eighth PMOS transistor P8 and the second activation signal / EN are applied to the gate to adjust the amount of current flowing between the drain-connected second voltage level maintenance signal Vndr and the source-connected ground voltage VSS. 7 A switch unit 210 including an NMOS transistor N7 and a first voltage level maintaining signal Vpdr are applied to a gate to between a source-connected core voltage Vcore and a drain-connected bit line precharge voltage Vblp. The ninth PMOS transistor P9 and the second voltage level maintaining signal Vndr are applied to the gate to control the current flowing through the gate, and the drain line is connected between the bit line precharge voltage Vblp and the source connected ground voltage VSS. Regulation to regulate the current flowing A voltage level holding unit 220 including an eighth NMOS transistor N8 and a second voltage Dcore connected to a source voltage core connected to a drain by applying a second activation signal / EN to a gate. The tenth PMOS transistor P10 for adjusting the amount of current flowing through the first diode, the first diode D1 for flowing the current flowing from the drain of the tenth PMOS transistor to the bit line precharge voltage Vblp node, and the bit line precharge A second diode (D2) drained by applying a second diode (D2) and a second activation signal (/ EN) to the gate to inject current from the voltage (Vblp) node to flow current to the ninth NMOS transistor (N9). And a reset unit 230 including a ninth NMOS transistor N9 for flowing the current flowing from the current to the source-connected ground voltage VSS.

In more detail, the switch unit 210 controls the second voltage level maintaining signal Vndr by grounding the second voltage level maintaining signal Vndr in response to the seventh NMOS transistor N7 in response to the second activation signal / EN. It can not be applied to the voltage level holding unit 220. Since the second activation signal / EN is at the high level, the eighth PMOS transistor P8 is not turned on, so that the first voltage level sustain signal Vpdr is the ninth PMOS transistor P9 of the voltage level maintainer 220. Is applied to the gate of.

Accordingly, the voltage level maintaining unit 220 applies the first voltage level maintaining signal Vpdr to the gate of the ninth PMOS transistor P9 and flows between the core voltage Vcore and the bit line precharge voltage Vblp. By adjusting the amount of current, the bit line precharge voltage Vblp is increased so that the bit line precharge voltage Vblp becomes equal to the 1/2 core voltage Vcore.

The current used to raise the bit line precharge voltage Vblp by the ninth PMOS transistor P9 of the voltage level maintaining unit 220 is transferred to the ninth NMOS transistor through the second diode D2 of the reset unit 230. It flows into the drain of N9 and leaks through the source-connected ground voltage VSS as the low level second activation signal / EN is applied to the gate of the ninth NMOS transistor N9.

Next, when the bit line precharge voltage Vblp is higher than the half core voltage Vcore by comparing the bit line precharge voltage Vblp and the 1/2 core voltage Vcore, the voltage driver 100 The 1/2 core is from the enable unit 300 in response to the first activation signal EN having a high level (NMOS turn-on voltage) and the second activation signal / EN having a low level (PMOS turn-on voltage). A first voltage level maintenance signal Vpdr for inputting a voltage Vcore to induce a voltage increase in the bit line precharge Vblp, and a second voltage level maintenance signal Vndr for inducing a voltage drop in the bit line precharge Vblp ) And the bit line precharge voltage Vblp.

In this case, the switch unit 210 applies a second activation signal / EN having a low level (PMOS turn-on voltage) to the gate so that the core voltage Vcore connected to the source and the first voltage level maintenance signal connected to the drain The eighth PMOS transistor P8 that adjusts the amount of current flowing between Vpdr prevents the first voltage level maintaining signal Vpdr from being applied to the voltage level maintaining unit 220. A ninth voltage is supplied to the first voltage level maintaining signal Vpdr so that the first voltage level maintaining signal Vpdr increases in voltage to be applied to the gate of the ninth PMOS transistor P9 of the voltage level maintaining unit 220. This is because the PMOS transistor P9 cannot be turned on.

A second activation signal / EN having a low level (PMOS turn-on voltage) is applied to the gate to adjust the amount of current flowing between the drain-connected second voltage level maintenance signal Vndr and the source-connected ground voltage VSS. Since the seventh NMOS transistor N7 is not turned on, the second voltage level maintenance signal Vndr may be applied to the gate of the eighth NMOS transistor N8 of the voltage level maintenance unit 220.

Accordingly, the voltage level maintaining unit 220 applies the second voltage level signal Vndr applied from the switch unit 210 to the gate of the eighth NMOS transistor N8 to drain the bit line precharge voltage Vblp. ) And the bit line precharge voltage Vblp is lowered by adjusting the amount of current flowing between the source and the ground-connected ground voltage VSS, so that the bit line precharge voltage Vblp is equal to 1/2 core voltage Vcore. To lose.

The tenth PMOS transistor P10 of the reset unit 230 is connected to a gate to compensate for the current used by the eighth NMOS transistor N8 of the voltage level maintaining unit 220 to drop the bit line precharge voltage Vblp. In response to the second activation signal of the applied low level (PMOS turn-on voltage), a current is supplied through the first diode D1 connected to the drain.

4 is a configuration diagram illustrating in detail a voltage generator of a semiconductor integrated circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the voltage generation device of the semiconductor integrated circuit will be described in detail.

The voltage generator of the semiconductor integrated circuit is low when the bit line precharge voltage VblP is lower than the half core voltage Vcore by comparing the bit line precharge voltage Vblp and the 1/2 core voltage Vcore. An enable unit 300 for generating a second activation signal / EN having a high level (NMOS turn-on voltage) by inverting the first activation signal EN having a level (PMOS turn-on voltage) and the first activation signal. Include.

In addition, the first activation signal EN and the second activation signal / EN generated by the enable unit 300 compare the bit line precharge voltage Vblp and the half core voltage Vcore. When the precharge voltage Vblp is higher than the 1/2 core voltage Vcore, the first activation signal EN having the high level (NMOS turn-on voltage) and the first activation signal EN are inverted to lower the level (PMOS turn-on voltage). May be a second activation signal / EN

The voltage driver 100 applies a 1/2 core voltage Vcore to the gate to control the amount of current flowing between the drain-connected second node n2 and the third node n3 connected to the source. N1), a second NMOS transistor N2 for applying a bit line precharge voltage Vblp to the gate to adjust the amount of current flowing between the first node n1 connected to the drain and the third node n3 connected to the source; The bias voltage Vbias is applied to the gate to adjust the amount of current flowing between the drain-connected third node n3 and the source-connected ground voltage VSS, and thus, the third NMOS transistor N3 and the fourth node n4. The voltages of the fourth NMOS transistor N4 and the fourth node n4 for controlling the amount of current flowing between the drain-connected fourth node n4 and the source-connected ground voltage VSS by applying a voltage to the gate are applied to the gate. The first voltage level maintaining signal Vpdr and the source connected to the drain The fifth NMOS transistor N5 and the fourth node n4, which control the amount of current flowing between the connected ground voltages VSS, are applied to the gate, and the source is connected to the drain-connected second voltage level maintenance signal Vndr. The sixth NMOS transistor N6 and the second node n2 are applied to the gate to control the amount of current flowing between the ground voltage VSS and the source-connected core voltage Vcore and the drain-connected second node n2. The amount of current flowing between the source-connected core voltage Vcore and the drain-connected first node n1 is applied by applying a voltage of the first PMOS transistor P1 and the second node n2 to the gate to control the amount of current flowing therebetween. A third PMOS for controlling the amount of current flowing between the source-connected core voltage Vcore and the drain-connected fourth node n4 by applying the second PMOS transistor P2 and the second node n2 voltage to the gate. Transistor P3, the first activation signal EN The fourth PMOS transistor P4 and the first node n1 are applied to the gate to control the amount of current flowing between the core voltage Vcore connected to the source and the fifth node n5 connected to the drain. The fifth PMOS transistor P5 and the second activation signal / EN to adjust the amount of current flowing between the first voltage level maintaining signal Vpdr connected to the drain at the fourth node n4, and the source connection is performed. The sixth node connected to the gate by applying a voltage of the sixth PMOS transistor P6 and the first node n1 to adjust the amount of current flowing between the core voltage Vcore and the sixth node n6 connected to the drain. and a seventh PMOS transistor P7 for regulating the amount of current flowing between the second voltage level maintaining signal Vndr connected to the drain at n6).

Specifically, the voltage driver 100 has a structure of a two-stage differential amplifier. First, a first stage differential amplifier having current mirrors using the first and second PMOS transistors P1 and P2 applies a 1/2 core voltage Vcore to the gate of the first NMOS transistor N1. The bit line precharge voltage Vblp is applied to the gate of the second NMOS transistor N2 to generate a voltage at the first node n1 and the second node n2. The next stage of the differential amplifier applies the voltage of the second node n2 to the gate of the third PMOS transistor p3 to generate the fourth node n4 at the drain of the third PMOS.

The bit line precharge voltage Vblp applied to the gate of the second NMOS transistor N2 is output to the driving controller 200 again.

The first node n1 is applied to the gate of the fifth PMOS transistor P5, the fourth node n4 is applied to the gate of the fifth NMOS transistor N5, and the first activation signal EN is The first voltage level maintenance signal Vpdr having a low level (PMOS turn-on voltage) is generated at the drains of the fifth NMOS transistor N5 and the fifth PMOS transistor P5 by being applied to the fourth PMOS transistor P4.

In addition, the first node n1 voltage is applied to the gate of the seventh PMOS transistor P7, the fourth node n4 is applied to the gate of the sixth NMOS transistor N6, and the second activation signal (/ EN is applied to the sixth PMOS transistor P6 to generate a second voltage level maintenance signal Vndr at a high level (NMOS turn-on voltage) at the drains of the sixth NMOS transistor N6 and the seventh PMOS transistor P7. do.

The driving controller 200 applies the second activation signal / EN to the gate to adjust the amount of current flowing between the core voltage Vcore connected to the source and the first voltage level maintenance signal Vpdr connected to the drain. A seventh NMOS transistor for controlling the amount of current flowing between the drain-connected second voltage level maintenance signal Vndr and the source-connected ground voltage VSS by applying the transistor P8 and the second activation signal / EN to the gate. A current flowing between the core voltage Vcore connected to the source and the bit line precharge voltage Vblp connected to the drain by applying the switch unit 210 including the N7 and the first voltage level maintaining signal Vpdr to the gate. The current flowing between the drain-connected bit line precharge voltage Vblp and the source-connected ground voltage VSS is applied by applying a ninth PMOS transistor P9 and a second voltage level maintaining signal Vndr to the gate. Regulating 8th NMOS Regulating The amount of current flowing between the voltage level holding unit 220 including the transistor N8 and the second activation signal / EN is applied to the gate to the gate-connected core voltage Vcore and the drain-connected first diode D1. The first PMOS transistor P10 to adjust, the first diode D1 and the bit line precharge voltage Vblp, which allow current to flow from the drain of the tenth PMOS transistor to the bit line precharge voltage Vblp node. A second diode D2 and a second activation signal / EN are applied to the gate to inject current from the node to flow the current to the ninth NMOS transistor N9 and flow from the second diode D2 exclusively drained. And a reset unit 230 including a ninth NMOS transistor N9 for flowing a current to a source-connected ground voltage VSS.

In more detail, the switch unit 210 applies a second activation signal / EN having a high level (NMOS turn-on voltage) to the gate, and a ground voltage source-connected with the second voltage level maintenance signal Vndr connected to the drain. The seventh NMOS transistor N7, which controls the amount of current flowing between the VSSs, prevents the second voltage level maintaining signal Vndr from being applied to the voltage level maintaining unit 220. Even when the current flows out to the ground voltage VSS and the second voltage level maintaining signal Vndr is applied to the gate of the eighth NMOS transistor N8 of the voltage level maintaining unit 220, the eighth NMOS transistor N8 may be turned on. Because it is not.

A second activation signal / EN having a high level (NMOS turn-on voltage) is applied to the gate to adjust the amount of current flowing between the source-connected core voltage Vcore and the drain-connected first voltage level maintenance signal Vpdr. Since the eighth PMOS transistor P8 is not turned on, the first voltage level maintaining signal Vpdr may be applied to the gate of the ninth PMOS transistor P9 of the voltage level maintaining unit 220.

Accordingly, the voltage level maintaining unit 220 applies the first voltage level signal Vpdr applied by the switch unit 210 to the gate of the ninth PMOS transistor P9 to source-connect the core voltage Vcore and the bit. The amount of current flowing between the line precharge voltages Vblp is adjusted to induce an increase in the bit line precharge voltages Vblp so that the bit line precharge voltages Vblp are equal to the 1/2 core voltage Vcore.

The current used to raise the bit line precharge voltage Vblp by the ninth PMOS transistor P9 of the voltage level maintaining unit 220 is transferred to the ninth NMOS transistor through the second diode D2 of the reset unit 230. It flows into the drain of N9 and leaks through the source voltage of grounded voltage VSS by applying the low level second activation signal / EN to the gate of the ninth NMOS transistor N9.

Next, when the bit line precharge voltage Vblp is higher than the half core voltage Vcore by comparing the bit line precharge voltage Vblp and the 1/2 core voltage Vcore, the voltage driver 100 The 1/2 core is from the enable unit 300 in response to the first activation signal EN having a high level (NMOS turn-on voltage) and the second activation signal / EN having a low level (PMOS turn-on voltage). A first voltage level maintenance signal Vpdr for inputting a voltage Vcore to induce a voltage increase in the bit line precharge Vblp, and a second voltage level maintenance signal Vndr for inducing a voltage drop in the bit line precharge Vblp ) And the bit line precharge voltage Vblp.

In this case, the switch unit 210 applies a second activation signal / EN having a low level (PMOS turn-on voltage) to the gate so that the core voltage Vcore connected to the source and the first voltage level maintenance signal connected to the drain The eighth PMOS transistor P8 that adjusts the amount of current flowing between Vpdr prevents the first voltage level maintaining signal Vpdr from being applied to the voltage level maintaining unit 220. A ninth voltage is supplied to the first voltage level maintaining signal Vpdr so that the first voltage level maintaining signal Vpdr increases in voltage to be applied to the gate of the ninth PMOS transistor P9 of the voltage level maintaining unit 220. This is because the PMOS transistor P9 cannot be turned on.

A second activation signal / EN having a low level (PMOS turn-on voltage) is applied to the gate to adjust the amount of current flowing between the drain-connected second voltage level maintenance signal Vndr and the source-connected ground voltage VSS. Since the seventh NMOS transistor N7 is not turned on, the second voltage level maintenance signal Vndr may be applied to the gate of the eighth NMOS transistor N8 of the voltage level maintenance unit 220.

Accordingly, the voltage level maintaining unit 220 applies the second voltage level signal Vndr applied from the switch unit 210 to the gate of the eighth NMOS transistor N8 to drain the bit line precharge voltage Vblp. ) And the bit line precharge voltage Vblp is lowered by adjusting the amount of current flowing between the source and the ground-connected ground voltage VSS, so that the bit line precharge voltage Vblp is equal to 1/2 core voltage Vcore. To lose.

The tenth PMOS transistor P10 of the reset unit 230 is connected to a gate to compensate for the current used by the eighth NMOS transistor N8 of the voltage level maintaining unit 220 to drop the bit line precharge voltage Vblp. In response to the second activation signal of the applied low level (PMOS turn-on voltage), a current is supplied through the first diode D1 connected to the drain.

5 is a graph comparing core voltage Vcore versus bit line precharge voltage Vblp according to an exemplary embodiment of the present invention.

Referring to FIG. 5, it can be seen that the bit line precharge voltage Vblp using the core voltage Vcore is generated without a dead zone in the PMOS driving region or the NMOS driving region.

Since the voltage generator of the semiconductor integrated circuit according to the embodiment of the present invention generates a voltage without a ringing phenomenon or a dead zone region, sensing of a sense amplifier using the generated bit line precharge voltage Vblp is performed. Increasing the capability and no ringing occurs to reduce unnecessary power consumption in order to generate cell plate voltage Vcp or bit line precharge voltage Vblp.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: voltage driving unit 200: driving control unit
210: switch unit 220: voltage level holding unit
230: reset unit 300: enable unit

Claims (6)

An enable unit configured to compare a bit line precharge voltage with a reference voltage to generate an activation signal having a first level when the bit line precharge voltage is higher than the reference voltage;
In response to the activation signal, a first voltage level maintenance signal for inducing an increase in the bit line precharge voltage, a second voltage level maintenance signal for inducing a drop in the bit line precharge voltage, and the bit line precharge voltage. A voltage driver configured to generate; And
And a driving control unit configured to control the bit line precharge voltage to a constant voltage level in response to the activation signal and the first and second voltage level maintenance signals. The method of claim 1,
The driving control unit may include a switch unit controlling the first and second voltage level maintenance signals in response to the activation signal;
A voltage level maintaining unit configured to maintain the bit line precharge voltage at a constant voltage level in response to the first and second voltage level maintenance signals; And
And a reset unit configured to provide a leakage path of the bit line precharge voltage in response to the activation signal. The method of claim 2,
And the switch unit controls the voltage of the voltage level holding unit by blocking the first voltage level holding signal in response to the activation signal. The method of claim 2,
And the switch unit controls the voltage of the voltage level holding unit by passing the second voltage level holding signal in response to the activation signal. 5. The method according to any one of claims 2 to 4,
And the reset unit maintains the bit line precharge voltage constant in response to the activation signal and blocks current leakage. The method of claim 1,
And the enable part is configured to shift the level of the activation signal when the bit line precharge voltage is lower than the reference voltage by comparing the bit line precharge voltage with the reference voltage. Voltage generator.
KR1020110074079A 2011-07-26 2011-07-26 Voltage generator of semiconductor intergrated circuit KR20130012739A (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
KR1020110074079A KR20130012739A (en) 2011-07-26 2011-07-26 Voltage generator of semiconductor intergrated circuit

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