KR20130009536A - Memory control device and method - Google Patents

Memory control device and method Download PDF

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Publication number
KR20130009536A
KR20130009536A KR1020110088086A KR20110088086A KR20130009536A KR 20130009536 A KR20130009536 A KR 20130009536A KR 1020110088086 A KR1020110088086 A KR 1020110088086A KR 20110088086 A KR20110088086 A KR 20110088086A KR 20130009536 A KR20130009536 A KR 20130009536A
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South Korea
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data
memories
host controllers
memory
host
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KR1020110088086A
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Korean (ko)
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김지민
서윤범
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삼성전자주식회사
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Priority to EP20120161103 priority Critical patent/EP2546754A1/en
Priority to US13/525,740 priority patent/US20130019055A1/en
Publication of KR20130009536A publication Critical patent/KR20130009536A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/205—Hybrid memory, e.g. using both volatile and non-volatile memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/253—Centralized memory
    • G06F2212/2532—Centralized memory comprising a plurality of modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/604—Details relating to cache allocation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A memory control device is disclosed. The memory control apparatus according to the present invention includes a plurality of memories, a plurality of host controllers connected to each of the plurality of memories, and a synchronization unit configured to collectively perform data read or data write operations on the plurality of memories through the plurality of host controllers. . Accordingly, by simultaneously controlling a plurality of memory cards that perform data read or write related operations at different timings, data read or data write related operations may be simultaneously performed on the plurality of memory cards.

Description

Memory control device and method

The present invention relates to a memory control apparatus and method, and more particularly to a memory control apparatus and method capable of controlling a plurality of memories at the same time.

In general, a memory device such as a multimedia card (hereinafter referred to as MMC) is widely used for data storage devices of devices such as smart phones, cameras, and MP3s. Such a memory device is coupled to an external device such as a computer through a system bus and performs data communication according to a predetermined communication protocol.

In the case of MMC, it has 8 to 9 communication signals (CLK, CMD, DATA0 to DATA7, H / W reset) as an interface. The CMD and DATA lines send commands to the CMD line and receive the corresponding responses. The DATA line is fixed at 8 bits, and 1 bit, 4 bit and 8 bit data transfer is available according to the user's choice.

When the memory card is combined with a host such as a computer, the process of accessing the memory card shows that a voltage range at which the memory card can operate through the CMD1 is first used to access the memory card. Check At this time, the memory card notifies the voltage range supported by the host through the CMD1, and if the voltage range can be supported, the memory card performs a response while notifying the card operating voltage. Accordingly, the memory card enters the ready state, and the host checks how many slots there are in the memory card.

Thereafter, the host transmits a CMD2 (Send Card ID) to the memory card, and the memory cards that receive the CMD2 transmit identification information to the host. Accordingly, the host determines the number of memory cards connected to the host and assigns an identification number to each memory card through CMD3. Accordingly, the memory cards connected to the host enter a standby state, and only one of the memory cards entering the standby state is selected and used through CMD7 (select / deselect card).

As described above, when a host and a plurality of memory cards are connected, the operation of another memory card is terminated after the operation of the selected memory card is terminated through the CMD7 for data reading or data writing to the connected memory cards. Can be performed. That is, conventionally, since a plurality of memory cards connected to a host do not have the same timing according to data processing, data read or data write operations for a plurality of memory cards cannot be simultaneously performed.

The present invention has been made to solve the above-described problem, and an object of the present invention is to read or write data for a plurality of memory cards by synchronizing and controlling a plurality of memory cards that perform data read or write related operations at different timings. The purpose is to allow write-related operations to be performed at the same time. Furthermore, an object of the present invention is to enable a large amount of data processing with only the data bits of an existing memory card without increasing the data bit width of the memory card.

According to an embodiment of the present invention, a memory control apparatus includes a plurality of memories, a plurality of host controllers connected to each of the plurality of memories, and a plurality of memory units through the plurality of host controllers. It includes a synchronization unit for performing a data read or data write operation.

When the data read operation is performed, the synchronization unit may include a master controller that collects data read from the plurality of memories by the plurality of host controllers and transmits the data to the external device.

When the data write operation is performed, when the data for writing to the plurality of memories is input, the master controller may divide the input data and provide the divided data to the plurality of host controllers.

Each of the plurality of host controllers may perform a data read or write operation on a plurality of connected memories according to a plurality of registers individually set by the master controller and setting values of the plurality of registers. It may include a direct memory access (DMA) controller.

The synchronization unit may further include a slave controller configured to simultaneously control the plurality of registers to simultaneously perform data write operations to the plurality of memories, wherein the plurality of DMA controllers are configured to control commands of the slave controller. According to the setting values of the plurality of registers set at the same time, it is possible to request the data write to the master controller at the same time.

The plurality of memories, the plurality of host controllers, and the synchronizer may be integrated in a single chip.

The plurality of memories may include at least one of a multi media card (MMC), a secure digital (SD), and a nonvolatile memory.

On the other hand, according to an embodiment of the present invention for achieving the above object, a memory control method of a memory control apparatus including a plurality of memory, according to the data read control command for the plurality of memories, each of the plurality of memories Setting a plurality of host controllers connected to a data read related operation mode, receiving data stored in the plurality of memories read by the plurality of host controllers according to the data read related operation mode setting; And when all data read by the plurality of host controllers is received, collecting the received data into one and transmitting the collected data to an external device.

Each of the plurality of host controllers may include a direct memory access (DMC) controller that performs a data read or data write operation to the plurality of memories according to a register and a setting value of the register.

The method may further include setting respective registers connected to each of the plurality of memories in a data write related operation mode according to a data write control command for the plurality of memories, and the plurality of host controllers in which the data write related operation mode is set. Receiving data for writing to the plurality of memories from an external device in response to a data write request from the external device; and dividing the input data to store the input data in the plurality of memories to the plurality of host controllers. It may further comprise the step of providing.

In the setting of the data write related operation mode, the registers connected to each of the plurality of memories may be simultaneously set to the data write related operation mode according to a data write simultaneous control command for the plurality of memories. .

The plurality of memories may include at least one of a multi media card (MMC), a secure digital (SD), and a nonvolatile memory.

1 is a block diagram of a general memory device;
2 is a block diagram of a memory control apparatus according to an embodiment of the present invention;
3 is a timing diagram illustrating a time point at which first and second host controllers transmit request information related to reading or writing data, according to an embodiment of the present invention;
4 is a flowchart illustrating a memory control method according to a data read operation in a memory control apparatus including a plurality of memories according to an embodiment of the present invention;
5 is a flowchart illustrating a memory control method according to a data write operation in a memory control apparatus including a plurality of memories according to an embodiment of the present invention.

Hereinafter, a temporal example of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a general memory device.

As shown in FIG. 1, the memory device includes a host controller 100 and a plurality of multimedia cards (hereinafter, referred to as memories) 110 and 120. The host controller 100 using the Multi Media Card (MMC) or Secure Digital (SD) protocol is connected to the memories 100 and 120 through the system bus 130. The memories 110 and 120 connected to the host controller 100 and the system bus 130 may read data stored in the memory 110 and 120 or may store data stored in an external device according to a control command of the host controller 100. The data write operation is performed to be stored in the memories 110 and 120.

Each of the memories 110 and 120 performs an operation through a card identification mode and a data transfer mode. Specifically, in the card identification mode operation, the host controller 100 requests a card identification number (CID Number) from each of the first and second memories 110 and 120. In response to the request, the first and second memories 110 and 120 may transmit response information according to the card identification number request to the host controller 100. The memory that successfully transmits the response information to the host controller 100 among the first and second memories 110 and 120 capable of transmitting such response information is allocated an RCA (Relative Card Address) from the host controller 100.

According to an embodiment, if the first memory 110 successfully transmits response information to the host controller 100, the first memory 110 is allocated an RCA from the host controller 100. As such, when the RCA is allocated to the first memory 110, the first memory 110 enters the data transfer mode from the card identification mode. As described above, the first memory 110 suppressing the data transmission mode may include a standby state, a transfer state, a data transmission state, and a data reception state in the data transmission mode state. It may have one of Receive Data State and Programming State.

In general, an operation required by the host controller 100 according to a control command (for example, a write command) of the host controller 100 in a transfer state is performed when the first memory 110 that enters the data transfer mode is allocated to the RCA. Can be performed. As such, when the first memory 110 performs an operation such as writing data according to the control command of the host controller 100, the second memory 120 is in a standby state. That is, the host controller 100 cannot issue a control command such as a write command to the second memory 120 until the write operation of the first memory 110 that controls the write operation is completed.

In other words, after all the operations of the first memory 110 are terminated according to the control command of the host controller 100, the control for the operation of the second memory 120 may be performed. Therefore, reading or writing data to the first and second memories 110 and 120 cannot be performed at the same time. Up to now, the operation of the conventional memory control apparatus has been outlined. Hereinafter will be described in detail with respect to the memory control device of the present invention proposed to improve the above problems of the conventional memory control device.

2 is a block diagram of a memory control apparatus according to an embodiment of the present invention.

As shown in FIG. 2, the memory control apparatus according to the present invention includes first and second memories 210 and 220, first and second host controllers 230 and 240, a synchronizer 250, and an external device 260. In the present invention, the present invention is limited to two memories and two host controllers. However, the present invention is not limited thereto, and it is preferable to include m memories and n host controllers corresponding to each of the m memories.

The first and second memories 210 and 220 are general low-cost data storage devices manufactured for built-in, not portable, and are used in smart phones, cameras, personal digital assistants (PDAs), digital recorders, and MP3 players. The memory used in such a device may be one of a multi-media card (MMC), a secure digital card (SD-Card), and a nonvolatile memory 9Non-Volatile Memory (NVM).

The first and second host controllers 230 and 240 are connected to the first and second memories 210 and 220, respectively, to read data stored in the first and second memories 210 and 220 or to write data to the first and second memories 210 and 220. Control to perform the operation. The first and second memories 210 and 220 and the first and second host controllers 230 and 240 are connected through an interface, and both sides have a total of 8 to 9 communication signals CLK, CMD, DATA0 to DATA7, and H / W reset. Send and receive data reading or data writing related information.

The synchronizer 250 performs a data read or data write operation on the first and second memories 210 and 22 connected to the first and second host controllers 230 and 240 through the first and second host controllers 230 and 240. To perform. More specifically, when all the data read-related request information is received from the first and second host controllers 230 and 240, the synchronizer 250 receives data related to the data read-related request information from the first and second host controllers 230 and 240. do. That is, the first and second host controllers 230 and 240 request data to be transmitted to the external device to the first and second memories 210 and 220 connected thereto, respectively. Accordingly, the first and second memories 210 and 220 transmit the requested data to the first and second host controllers 230 and 240 connected thereto, respectively, and the first and second host controllers 230 and 240 transmit the first and second memories 210 and 220. The data received from the data is transmitted to the synchronizer 250. Accordingly, the synchronizer 250 collects data received from the first and second host controllers 230 and 240 and transmits the data to the external device 260 to simultaneously transmit data of the first and second memories 210 and 220 to the external device 260. ) Can be sent.

Meanwhile, when all data write related request information is received from the first and second host controllers 230 and 240, the synchronizer 250 receives the data write related request information received from the first and second host controllers 230 and 240. To send). Accordingly, the external device 260 transmits data related to data write related request information received from the synchronization unit 250 to the synchronization unit 250. Receiving data stored in the external device 260, the synchronization unit 250 divides the received data, so that each of the divided data can be written in the first, second memory (210, 220) The first and second host controllers 230 and 240 connected to the 210 and 220 are transmitted.

According to an embodiment, when 128 bits of data are received from the external device 260, the synchronization unit 250 divides the received 124 bits of data into 64 bits of data, and according to a preset condition, the upper 64 bits Is transmitted to the first host controller 230 connected to the first memory 210, and lower 64-bit data is transmitted to the second host controller 230 connected to the second memory 220. Accordingly, the first memory 210 and the second memory 220 may simultaneously receive and store data stored in an external device.

Up to now, each configuration of the memory control device has been described in outline. Hereinafter, respective components of the memory control apparatus controlling to simultaneously perform data read or write operations of the first and second memories 210 will be described in detail.

As described above, the first and second host controllers 230 and 240, which are connected to the first and second memories 210 and 220, respectively, and control data read or write operations of the first and second memories 210 and 220, respectively, include first and second registers. 231 and 241 and first and second DAM controllers 232 and 242. The first and second registers 231 and 241 are set by the synchronization unit 250 to transmit a data read or data write command to the first and second memories 210 and 220 and receive a response message accordingly.

According to an embodiment, when performing a data read-related operation, the first and second registers 231 and 241 may transmit data to the first and second memories 210 and 22 connected through an interface with the first and second host controllers 230 and 240. Send read-related operation command information. That is, the first and second registers 231 and 241 transmit data read-related operation command information to the first and second memories 210 and 220 to transmit data to the master 261 side of the external device 260. The first and second memories 210 and 220 receiving the data read related operation command information from the first and second registers 231 and 241 transmit the response messages to the first and second registers 231 and 241.

According to another embodiment, when performing a data write related operation, the first and second registers 231 and 241 write data to the first and second memories 210 and 220 connected through an interface with the first and second host controllers 230 and 240. Send relevant operation command information. That is, the first and second registers 231 and 241 transmit data write related operation command information to store the data stored in the DDR 262 of the external device 260 in the first and second memories 210 and 220. The first and second memories 210 and 220 that receive data write related operation command information from the first and second registers 231 and 241 transmit a response message to the first and second registers 231 and 241.

As described above, the first and second registers 231 and 241 may set an operation for reading data stored in the first and second memories 210 and 220 or writing data to the first and second memories 210 and 220.

The first and second DMA controllers 232 and 242 may be configured when an operation related to reading data stored in the first and second memories 210 and 220 or writing data to the first and second memories 210 and 220 is set by the first and second registers 231 and 241. According to a setting value according to the data read or write operation setting of the first and second registers 231 and 241, the data read or write operation may be performed on the first and second memories 210 and 22. Accordingly, the first and second DMA controllers 232 and 242 transmit data read from the first and second memories 210 and 220 to the synchronizer 250 or receive and divide data received from the DDR 262 of the external device 260. The data may be received from the synchronization unit 250 and stored in the first and second memories 210 and 220.

Meanwhile, the above-described synchronization unit 250 transmits data stored in the first and second memories 210 and 220 to the external device 260 through the master controller 251, or divides the data input from the external device 260. It may be controlled to be stored in the first and second memories 210 and 22.

In detail, when the master controller 251 performs a data read operation, the master controller 251 collects data read from the first and second memories 210 and 220 by the first and second host controllers 230 and 240 and transmits the data to the external device 260. Specifically, in order to read data stored in the first and second memories 210 and 220 through the master 261 of the external device 260, the first and second host controllers 230 and 240 transmit data to the master controller 251. Send read request information. As such, when all data read request information is received from the first and second host controllers 230 and 240, the master controller 251 reads data read by the first and second host controllers 230 and 240 from the first and second memories 210 and 220. Synchronize and collect as one data. More specifically, the first and second host controllers 230 and 240 transmitting the data read request information to the master controller 251 may transmit the data at different times as shown in FIG. 3.

3 is a timing diagram illustrating a point in time at which the first and second host controllers transmit request information related to reading or writing data according to an embodiment of the present invention.

As illustrated, in order for the first host controller 230 and the second host controller 240 to perform data read or write operations of the first and second memories 210 and 220, the first and second host controllers 230 and 240 may be used. Data read or write request information is transmitted to the master controller 251. In this case, data read or write request information transmitted from the first and second host controllers 230 and 240 to the master controller 251 is transmitted differently. As illustrated, data read or write request information of the first host controller 230 is first transmitted to the master controller 250, and data read or write request information of the second host controller 240 is passed after a predetermined time. Is sent to the master controller 250.

Therefore, as the data read request information from the first and second host controllers 230 and 240 is differently transmitted, the master controller 251 reads the first and second reads from the first and second host controllers 230 and 240. Synchronization is performed to simultaneously transmit data from the two memories 210 and 220 to the external device 260. Accordingly, the master controller 251 collects data of the first and second memories 210 and 220 read by the first and second host controllers 230 and 240 into one at the time when the data read request information is received from the second host controller 240. Send to external device 260. Accordingly, the master 261 of the external device 260 may read data stored in the first memory 210 and the second memory 220 at the same time.

Meanwhile, when data to be written is input to the first and second memories 210 and 220 when the master controller 251 performs a data write operation, the master controller 251 divides the input data and transmits the divided data to the first and second host controllers 230 and 240. do. Specifically, when all data write request information is received from the first and second host controllers 230 and 240, the master controller 251 transmits the data write request information received from the first and second host controllers 230 and 240 to the external device 260. To the DDR 262 side.

As described above, data write request information transmitted from the first and second host controllers 230 and 240 to the master controller 251 is differently transmitted. As shown in FIG. 3, data write request information of the first host controller 230 is first transmitted to the master controller 250, and data write request information of the second host controller 240 is mastered after a predetermined time. Is sent to the controller 250.

As described above, as the data write request information from the first and second host controllers 230 and 240 is differently transmitted, the master controller 250 receives the data write request information received from the first and second host controllers 230 and 240 from the external device. Synchronization is performed to transmit to the DDR 262 side of 260. Accordingly, as illustrated in FIG. 3, the master controller 251 may transmit data write request information to the DDR 262 side of the external device 260 when the data write request information is received from the second host controller 240.

When the requested data is received from the DDR 262 that receives the data write request information, the master controller 251 divides the received data according to a preset condition and transmits the received data to the first and second host controllers 230 and 240.

According to the embodiment, the master controller 251 receives 128 bits of data from the DDR 262 side, and divides the received 128 bits of data into 64 bits, respectively. Thereafter, the master controller 251 transmits upper 64-bit data to the first host controller 230 according to a preset condition. The master controller 251 transmits the lower 64-bit data to the second host controller 240.

The first and second host controllers 230 and 240 that have received the upper 64-bit and lower 64-bit data through the master controller 251 communicate with the first and second host controllers 230 and 240 through the first and second DMA controllers 232 and 242. Request to perform a data write operation to the connected first and second memories 210 and 220. Accordingly, the first and second memories 210 and 22 perform a 64-bit data write operation received from the first and second host controllers 230 and 240. Accordingly, data stored in the DDR 262 of the external device 260 may be recorded and stored in the first memory 210 and the second memory 220.

Meanwhile, according to an additional aspect of the present disclosure, the synchronizer 250 may transmit data write request information to the DDR 261 side of the external device 260 without any synchronization. Such a synchronization unit 250 may be achieved through the slave controller 252. The slave controller 252 simultaneously controls the first and second registers 231 and 241 of the first and second host controllers 230 and 240 so that data write operations to the first and second memories 210 and 220 may be performed at the same time.

According to the control command of the slave controller 252, the first and second registers 231 and 241 may simultaneously set data write-related settings. Accordingly, the first and second host controllers 230 and 240 may simultaneously transmit data write request information to the master controller 251 through the first and second DMA controllers 232 and 242. As such, according to the control command of the slave controller 252, the master controller 251 simultaneously receives data write request information from the first and second host controllers 230 and 240, thereby not performing a separate synchronization, and thereby performing an external device ( The data write request information may be transmitted to the DDR 261 side of the 260. Meanwhile, the first and second memories 210 and 220, the first and second host controllers 230 and 240, and the synchronizer 250 may be integrated in a single chip.

Up to now, each configuration of the memory control apparatus according to the present invention has been described in detail. Hereinafter, a method of controlling the memory controller to perform data reading or writing of a plurality of memories simultaneously will be described in detail.

Prior to describing the method of controlling the memory in the memory control apparatus according to the present invention, the memory control apparatus may include a plurality of memories (hereinafter referred to as first and second memories), The first and second memories may be controlled as follows according to data read or data write. Therefore, FIG. 4 will be described in detail with respect to the memory control method according to the data read operation in the memory control device including the first and second memories. In FIG. 5, a memory control method according to a data write operation to the first and second memories in the memory control apparatus will be described in detail.

4 is a flowchart illustrating a memory control method according to a data read operation in a memory control apparatus including a plurality of memories according to an embodiment of the present invention.

As illustrated, when a data read operation is started for the first and second memories, the memory control apparatus reads data from a plurality of host controllers (hereinafter, referred to as first and second host controllers) connected to each of the first and second memories. Set to the relevant operation mode (S410). Thereafter, the memory controller receives data read request information from the first and second host controllers according to the data read related operation mode setting (S420). Here, the first and second memories are general low-cost data storage devices manufactured for built-in, not portable, and are used in smart phones, cameras, personal digital assistants (PDAs), digital recorders, MP3 players, and the like. The memory used in such a device may be one of a multimedia card (MMC), a secure digital (SD) card, and a non-volatile memory (NVM).

When such a data read operation to the first and second memories is started, the memory control apparatus receives data read request information from the first and second host controllers in connection with reading data stored in the first and second memories. In response to the data read request information input from the first and second host controllers, the memory controller checks whether all data read request information is input from the first and second host controllers (S430).

As a result of the check, when all data read request information is input from the first and second host controllers, the memory controller receives data of the first and second memories connected to each of the first and second host controllers. That is, when all data read request information is input from the first and second host controllers, the memory controller receives the data read from the first and second memories (S440). As described above, each of the first and second host controllers is connected to the first and second memories, and according to the registers (hereinafter referred to as first and second registers) and the setting values of the registers, the first and second hosts, respectively. And a DMA controller (hereinafter, referred to as a first and second DMA controller) that performs a data read or data write operation on the first and second memories connected to the host controller.

Accordingly, the first and second DMA controllers of the first and second host controllers may read data into the first and second memories according to data read related setting values of the first and second registers. As such, when data reads to the first and second memories are performed through the first and second DMA controllers, the first and second host controllers control the data read from the first and second memories through the first and second DMA controllers. To the device. When all data stored in the first and second memories are received from the first and second host controllers, the memory control apparatus synchronizes the received data to collect one data and transmits the collected data to an external device (S450). ).

Meanwhile, data read request information transmitted from the first and second host controllers to the memory control device are differently transmitted. As described above, in FIG. 3, the data read request information of the first host controller is first transmitted to the memory control device, and the data read request information of the second host controller is transmitted after the data read request information of the first host controller is transmitted. May be transmitted to the memory control device. As described above, since the data read request information is differently transmitted from the first and second host controllers, the memory control apparatus cannot simultaneously transmit data of the first and second memories received from the first and second host controllers to the external device. . Therefore, the memory controller performs synchronization to simultaneously transmit data of the first and second memories to the external device. That is, the memory control apparatus may receive data of the first and second memories received from the first and second host controllers when the data read request information is received from the second host controller that transmits the data read request information later than the first host controller. It is collected as one and sent to the external device.

Therefore, the memory control device may simultaneously transmit data stored in the first and second memories to the external device. Up to now, a plurality of memory control methods according to data read operations for a plurality of memories in the memory control apparatus have been described in detail. Hereinafter, a plurality of memory control methods according to data write operations to a plurality of memories in the memory control apparatus will be described in detail with reference to FIG. 5.

5 is a flowchart illustrating a memory control method according to a data write operation in a memory control apparatus including a plurality of memories according to an embodiment of the present invention.

As shown, when a data write operation to the first and second memories is started, the memory control apparatus checks whether each register included in the first and second host controllers is set to the data write related operation mode at the same time (S510). . As a result of the check, if the registers are not simultaneously set, the memory controller individually sets each register included in the first and second host controllers to the data write related operation mode through the master controller (S520). As the data write related operation mode is set, the memory controller receives data write request information from the first and second host controllers (S530).

As described above, each of the first and second host controllers is connected to the first and second memories, and the data for the first and second memories connected to the first and second host controllers according to a register and a setting value of the register. It includes a DMA controller that performs a read or write data operation. Accordingly, the first and second DMA controllers of the first and second host controllers may perform data writes to the first and second memories according to data write related settings of the first and second registers. The data stored in the DDR of the device may be recorded and stored in the first and second memories.

Specifically, in order to record and store data previously stored in the DDR of the external device in the first and second memories, the first and second host controllers transmit data write request information to the memory control device. When data write request information is received from the first and second host controllers, the memory controller checks whether all data write request information is received from the first and second host controllers (S540).

Specifically, as described above with reference to FIG. 3, the data write request information of the first host controller is first transmitted to the memory control device, and the data write request information of the second host controller is the data write request information of the first host controller. After the transmission, it may be transmitted to the memory control device. As such, since the data write request information is differently transmitted from the first and second host controllers, the memory control apparatus may transmit the data write request information to the first and second memories received from the first and second host controllers of the external device. It is not possible to transmit to the DDR side at the same time. Therefore, the memory controller checks whether all data write request information has been received from the first and second host controllers.

If it is checked that all data write request information has been received from the first and second host controllers, the memory controller transmits the data write request information received from the first and second host controllers to the external device through the master controller. A write request of data stored in the external device DDR may be requested (S550).

On the other hand, if it is checked in step S510 that the registers are concurrently set, the memory control apparatus performs the first and second operations of the first and second host controllers to simultaneously perform data write operations to the first and second memories through the slave controller. The registers are simultaneously set to a data write related operation mode (S560). According to the simultaneous control command of the slave controller, the first and second registers may simultaneously set data write related operation modes. Accordingly, the first and second host controllers simultaneously transmit data write request information to the memory controller. Thereafter, when data write request information is simultaneously transmitted from the first and second host controllers, the memory control apparatus transmits data write request information to the external device through the master controller in step S550.

The memory control apparatus which has transmitted the data write request information receives data related to the data write request information from the DDR of the external device. When data related to data write request information received from the external device's DDR is received, the memory control device divides the received data according to a preset condition and transmits the received data to the first and second host controllers (S570 and S580).

According to an embodiment, when the 128-bit data stored in the DDR of the external device is received with respect to the data write request information, the memory controller divides the received 128-bit data into 64 bits, respectively. Thereafter, the memory controller transmits upper 64-bit data to the first host controller and transmits lower 64-bit data to the second host controller according to a preset condition. The first and second host controllers receiving data of the upper 64 bits and the lower 64 bits from the memory control device respectively request data storage to the first and second memories connected to the first and second host controllers. Accordingly, the first and second memories store 64-bit data respectively received from the first and second host controllers. Therefore, data stored in the DDR of the external device can be simultaneously recorded and stored in the first memory and the second memory.

So far I looked at the center of the preferred embodiment for the present invention.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

100: host controller 110, 120: memory
210: first memory 220: second memory
230: first host controller 231: first register
232: first DMA controller 240: second host controller
241: second register 242: second DMA controller
250: synchronization unit 251: master controller
252: slave controller 260: external device
261: master 262: DDR

Claims (12)

A plurality of memories;
A plurality of host controllers connected to each of the plurality of memories; And
A synchronization unit configured to collectively perform a data read or data write operation on the plurality of memories through the plurality of host controllers;
Memory control device comprising a. The method of claim 1,
Wherein the synchronization unit comprises:
A master controller configured to collect data read from the plurality of memories by the plurality of host controllers and transmit the collected data to an external device when the data read operation is performed;
Memory control device comprising a. The method of claim 2,
The master controller,
In the case of performing the data write operation, when data for writing to the plurality of memories is input, the input data is divided and provided to the plurality of host controllers. The method of claim 3, wherein
Each of the plurality of host controllers,
A plurality of registers individually set by the master controller; And
A plurality of direct memory access (DMA) controllers that perform data read or write operations on a plurality of connected memories according to setting values of the plurality of registers;
Memory control device comprising a. The method of claim 4, wherein
Wherein the synchronization unit comprises:
And a slave controller which simultaneously controls the plurality of registers to simultaneously perform data write operations to the plurality of memories.
The plurality of DMA controllers,
And writing data to the master controller at the same time according to setting values of the plurality of registers set at the same time by the control command of the slave controller. 6. The method according to any one of claims 1 to 5,
And the plurality of memories, the plurality of host controllers and the synchronizer are integrated in a single chip. 6. The method according to any one of claims 1 to 5,
The plurality of memories,
And at least one of a multi media card (MMC), a secure digital (SD), and a nonvolatile memory. In the memory control method of the memory control device including a plurality of memories,
Setting a plurality of host controllers connected to each of the plurality of memories to a data read related operation mode according to a data read control command for the plurality of memories;
Receiving data stored in the plurality of memories read by the plurality of host controllers according to the data read related operation mode setting; And
When all data read by the plurality of host controllers is received, collecting the received data into one and transmitting the collected data to an external device;
Memory control method comprising a. The method of claim 8,
Each of the plurality of host controllers,
And a direct memory access (DMC) controller performing a data read or data write operation to the plurality of memories according to a register and a setting value of the register. The method of claim 9,
Setting respective registers connected to each of the plurality of memories to a data write related operation mode according to a data write control command for the plurality of memories;
Receiving data for writing to the plurality of memories from an external device according to a data write request of the plurality of host controllers in which the data write related operation mode is set; And
Dividing the input data to the plurality of host controllers so that the input data is stored in the plurality of memories;
Memory control method comprising a further. 11. The method of claim 10,
The setting of the data writing related operation mode may include:
And setting each register connected to each of the plurality of memories to a data write related operation mode simultaneously according to a data write simultaneous control command for the plurality of memories. The method according to any one of claims 8 to 11,
The plurality of memories
And at least one of a multi media card (MMC), a secure digital (SD), and a nonvolatile memory.

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140117934A (en) * 2013-03-27 2014-10-08 삼성전자주식회사 Storage system and the method for synchronizing the storage system
KR20140122350A (en) * 2013-04-09 2014-10-20 삼성전자주식회사 Non-volatile storage device and method of storing data thereof
CN111857817A (en) * 2019-04-25 2020-10-30 比亚迪股份有限公司 Data reading method, data reading device and data reading system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140117934A (en) * 2013-03-27 2014-10-08 삼성전자주식회사 Storage system and the method for synchronizing the storage system
KR20140122350A (en) * 2013-04-09 2014-10-20 삼성전자주식회사 Non-volatile storage device and method of storing data thereof
CN111857817A (en) * 2019-04-25 2020-10-30 比亚迪股份有限公司 Data reading method, data reading device and data reading system
CN111857817B (en) * 2019-04-25 2024-02-20 比亚迪半导体股份有限公司 Data reading method, data reading device and data reading system

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