KR20120090202A - Stage block for manufacturing semiconductor package - Google Patents

Stage block for manufacturing semiconductor package Download PDF

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Publication number
KR20120090202A
KR20120090202A KR1020110010494A KR20110010494A KR20120090202A KR 20120090202 A KR20120090202 A KR 20120090202A KR 1020110010494 A KR1020110010494 A KR 1020110010494A KR 20110010494 A KR20110010494 A KR 20110010494A KR 20120090202 A KR20120090202 A KR 20120090202A
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South Korea
Prior art keywords
stage block
counterpart
semiconductor chip
bonding
bumps
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KR1020110010494A
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Korean (ko)
Inventor
정유신
정훈
김태호
이상균
권용호
김선일
박세엽
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020110010494A priority Critical patent/KR20120090202A/en
Publication of KR20120090202A publication Critical patent/KR20120090202A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A stage block for manufacturing a semiconductor package is provided to evenly maintain flatness by having a low thermal expansion coefficient like that of an alumina oxide. CONSTITUTION: A counter part(34) is mounted on a stage block(10). The stage block is made out of materials having a low thermal expansion coefficient. The stage block is made of alumina oxide materials. The stage block is shaped by ceramic materials. The upper side of the stage block is coated by the alumina oxide materials.

Description

반도체 패키지 제조용 스테이지 블럭{STAGE BLOCK FOR MANUFACTURING SEMICONDUCTOR PACKAGE}Stage block for manufacturing semiconductor package {STAGE BLOCK FOR MANUFACTURING SEMICONDUCTOR PACKAGE}

본 발명은 반도체 패키지 제조용 스테이지 블럭에 관한 것으로서, 더욱 상세하게는 써멀 컴프레션 방식의 본딩 과정에서 기판 또는 적층 대상의 칩 등이 안정적으로 안착될 수 있도록 고른 편평도를 갖는 반도체 패키지 제조용 스테이지 블럭에 관한 것이다.
The present invention relates to a stage block for manufacturing a semiconductor package, and more particularly, to a stage block for manufacturing a semiconductor package having an even flatness such that a substrate or a chip to be stacked can be stably seated in a thermal compression bonding process.

통상적으로, 반도체 패키지는 기판에 부착된 반도체 칩과, 반도체 칩과 기판간을 전기적 신호 교환 가능하게 연결하는 도전성 와이어와, 반도체 칩과 와이어 등을 봉지시켜 보호하기 위하여 기판의 일면에 몰딩되는 몰딩 컴파운드 수지 등을 포함하여 구성된다.In general, a semiconductor package includes a semiconductor chip attached to a substrate, a conductive wire connecting the semiconductor chip and the substrate to enable electrical signal exchange, and a molding compound molded on one surface of the substrate to seal and protect the semiconductor chip and the wire. It is comprised, including resin.

이러한 반도체 패키지의 구성중, 기판과 반도체 칩을 연결하는 도전성 와이어는 소정의 길이를 갖기 때문에 실질적으로 반도체 패키지의 사이즈 및 신호 전달 경로를 증가시키는 원인이 되고, 특히 반도체 칩이 고직접화, 고성능화 및 고속화됨에 따라 반도체 패키지를 소형화시키기 위한 노력에 오히려 역행하는 요인이 되고 있다.In the configuration of the semiconductor package, since the conductive wire connecting the substrate and the semiconductor chip has a predetermined length, the conductive wire substantially increases the size and the signal transmission path of the semiconductor package. As it becomes faster, it is becoming a factor against the efforts to miniaturize semiconductor packages.

이에, 반도체 칩의 전극패드(=본딩패드)에 솔더 또는 금속 재질의 범프를 일체로 형성하고, 이 범프를 매개로 반도체 칩의 전극패드들과 인쇄회로기판의 전도성패턴을 전기적으로 직접 연결시킴으로써, 도전성 와이어가 포함된 패키지에 비하여 경박단소화를 실현할 수 있는 반도체 패키지가 제안되고 있다.Accordingly, solder or metal bumps are integrally formed on the electrode pads (= bonding pads) of the semiconductor chip, and the electrode pads of the semiconductor chip and the conductive patterns of the printed circuit board are electrically connected directly through the bumps. Compared to a package containing conductive wires, a semiconductor package capable of realizing light and small shortening has been proposed.

첨부한 도 4에서 보듯이, 상기 범프(20)는 구리 도금 공정을 진행하여 반도체 칩(32)의 본딩패드 상에 소정의 높이로 형성되는 구리필러(22)와, 이 구리필러(22)의 상면에 일체로 형성되는 전도성 솔더(24)로 구성되며, 포토리소그래피 공정을 이용하여 칩의 본딩패드 상에 구리필러가 먼저 도금된 후, 그 위에 전도성 솔더가 순차적으로 도금된다.As shown in FIG. 4, the bump 20 includes a copper filler 22 formed at a predetermined height on a bonding pad of the semiconductor chip 32 by performing a copper plating process, and of the copper filler 22. It is composed of a conductive solder 24 integrally formed on the upper surface, the copper filler is first plated on the bonding pad of the chip using a photolithography process, and then the conductive solder is sequentially plated thereon.

이렇게 반도체 칩의 본딩패드에 구리필러(Cu pillar) 및 전도성 솔더로 이루어진 범프가 일체로 형성된 상태에서, 각 범프가 상대 칩 또는 기판과 같은 상대부품의 본딩영역 등에 본딩된다.In this state in which bumps made of a copper pillar and a conductive solder are integrally formed on the bonding pad of the semiconductor chip, each bump is bonded to a bonding area of a counterpart component such as a counterpart chip or a substrate.

즉, 상기 범프가 형성된 반도체 칩을 상대 칩 또는 기판과 같은 상대부품의 전기접속용 본딩영역에 적층되게 상호 접착시키되, 비전도성 페이스트(NCP: Non Conductive Paste)를 이용하여 소정의 온도에서 가압하는 써멀 컴프레션 방식의 본딩 방법(TCNCP: Thermal Compression Non Conductive Paste)을 이용하여 상대부품의 본딩영역에 범프의 전도성솔더를 접착시키거나, 또는 리플로우 솔더링(Reflow Soldering) 공정을 이용하여 상대부품의 본딩영역에 범프의 전도성솔더를 접착시키게 된다.That is, the thermally bonded semiconductor chips having the bumps are laminated to each other in the bonding region for electrical connection of the counterpart component such as the counterpart chip or the substrate, and pressurized at a predetermined temperature using a non-conductive paste (NCP). Bond the conductive solder of the bump to the bonding area of the mating part using a thermal bonding non-conductive paste (TCNCP), or use the reflow soldering process to bond to the mating area of the mating part. Bond the conductive solder of the bump.

여기서, 종래의 스테이지 블럭 및 이를 이용한 TCNCP 방법을 첨부한 도 4를 참조로 설명하면 다음과 같다.Here, with reference to Figure 4 attached to the conventional stage block and the TCNCP method using the same as follows.

먼저, 본딩 툴(30)이 범프(20)를 갖는 반도체 칩(32)의 상면을 소정의 압력으로 가압하는 동시에 진공 흡착한 다음, 상대부품(34, 적층 대상 칩 또는 기판 등)이 안착된 열압착 본딩부(38)의 스테이지 블럭(10)쪽으로 이송한 후, 연이어 본딩 툴(20)이 상대부품(34)쪽으로 하강을 한다.First, the bonding tool 30 pressurizes the upper surface of the semiconductor chip 32 having the bumps 20 to a predetermined pressure and vacuum-sucks them, and then heats on which the counterpart 34, the stacking chip or the substrate, etc. are seated. After transferring to the stage block 10 of the crimp bonding part 38, the bonding tool 20 descends to the counterpart part 34 successively.

연속해서, 반도체 칩(32)의 범프(20)가 적층 대상의 상대부품(34)의 본딩영역에 안착되는 상태가 되고, 이에 열과 압력을 가하는 열압착 방식에 의하여 범프(20)가 상대부품(34)의 본딩영역에 융착된다.Subsequently, the bump 20 of the semiconductor chip 32 is in a state of being seated in the bonding region of the mating component 34 to be stacked, and the bump 20 is applied to the mating component (by a thermocompression method for applying heat and pressure thereto). 34) is bonded to the bonding area.

보다 상세하게는, 범프(20)를 융착시키기 전에 상대부품(34)의 본딩영역을 포함하는 표면에 걸쳐 접착제의 일종인 비전도성 페이스트(NCP: Non Conductive Paste)를 미리 도포하는 과정과, 본딩 툴(30)이 하강을 하여 반도체 칩(32)의 범프(20)가 경화 전 상태인 비전도성 페이스트(36)를 뚫고 상대부품(34)의 본딩영역에 안착되는 과정과, 열과 압력이 인가되는 상태에서 본딩 툴(30)이 반도체 칩(32)을 소정의 힘으로 가압하여 범프(20)의 전도성 솔더(24) 부분이 상대부품(34)의 본딩영역에 융착되는 과정 등이 순차적으로 진행됨으로써, 범프(20)를 매개로 반도체 칩(32)이 상대부품(34)에 전기적 신호 교환 가능하게 적층 부착되고, 각 범프(20)들은 비전도성 페이스트(36)에 의하여 상호 절연되는 상태가 된다.More specifically, before the bump 20 is fused, a process of applying a non-conductive paste (NCP), which is a kind of adhesive, on a surface including the bonding area of the counterpart 34 in advance, and a bonding tool 30 is lowered so that the bump 20 of the semiconductor chip 32 penetrates through the non-conductive paste 36, which is a state before curing, and is seated in the bonding region of the counterpart 34, and a state in which heat and pressure are applied. The bonding tool 30 presses the semiconductor chip 32 with a predetermined force so that a portion of the conductive solder 24 of the bump 20 is fused to the bonding region of the counterpart 34 in sequence. The semiconductor chip 32 is laminated and attached to the counterpart component 34 so as to exchange electrical signals via the bumps 20, and the bumps 20 are insulated from each other by the non-conductive paste 36.

이때, 상기 상대부품(34)이 안착된 열압착 본딩부(38)의 스테이지 블럭(10) 은 SiC, Si와 같은 세라믹 재질로 제작된 것을 사용한다.At this time, the stage block 10 of the thermocompression bonding part 38 on which the counterpart 34 is seated may be made of a ceramic material such as SiC and Si.

그러나, 상대부품 즉, 기판 또는 적층 대상의 칩이 안착되는 스테이지 블럭이 세라믹 재질로 제작됨에 따라, 편평도가 좋지 않은 단점이 있다.However, as the stage block on which the counterpart, that is, the substrate or the chip to be stacked, is made of a ceramic material, there is a disadvantage that the flatness is not good.

즉, 100℃ 이상의 고온으로 스테이지 블럭이 유지될 때, SiC, Si와 같은 세라믹 재질은 그 열팽창계수(CTE)가 크기 때문에 스테이지 블럭의 전체 표면에 대한 편평도가 고르지 않고 다소 큰 차이를 나타내게 된다.That is, when the stage block is maintained at a high temperature of 100 ° C. or higher, ceramic materials such as SiC and Si have a large thermal expansion coefficient (CTE), so that the flatness of the entire surface of the stage block is uneven and shows a large difference.

이렇게 편평도의 차이를 갖는 세라믹 재질의 스테이지 블럭 상에 상대부품이 안착된 상태에서, 반도체 칩의 범프를 상대부품의 본딩영역에 융착시키게 되면, 스테이지 블럭의 편평도가 고른 부분에서는 범프의 융착이 제대로 이루어지지만, 스테이지 블럭의 편평도가 낮거나 높은 부분에서는 범프의 융착이 제대로 이루어지지 않는 미스 어라인먼트 현상이 발생되는 문제점이 있었다.
When the bumps of the semiconductor chip are fused to the bonding area of the counterpart in a state in which the counterpart is seated on the stage block of ceramic material having the flatness difference, the bumps are properly fused at the flat part of the stage block. However, there is a problem in that a misalignment phenomenon in which bumps are not properly fused is generated in a portion where the flatness of the stage block is low or high.

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 적층 대상의 상대부품(기판, 적층 대상 칩)이 안착되는 스테이지 블럭의 재질을 산화알루미나와 같은 낮은 열팽창계수를 갖는 재질로 형성하여, 스테이지 블럭의 편평도가 고르게 유지되도록 함으로써, 적층 대상의 상대부품에 반도체 칩의 범프가 미스 어라인먼트없이 제대로 융착될 수 있도록 한 반도체 패키지 제조용 스테이지 블럭을 제공하는데 그 목적이 있다.
The present invention has been made in view of the above, and the stage block on which the mating component (substrate, chip for stacking) to be stacked is placed is formed of a material having a low coefficient of thermal expansion such as alumina, and thus the stage block. It is an object of the present invention to provide a stage block for manufacturing a semiconductor package in which bumps of a semiconductor chip can be properly fused without misalignment to a mating component to be stacked, by keeping the flatness of the film evenly.

상기한 목적을 달성하기 위한 본 발명은 상대부품이 안착되는 스테이지 블럭을 낮은 열팽창 계수를 갖는 재질로 제작하여, 반도체 칩의 범프가 상대부품에 융착되는 고온 조건에서도 스테이지 블럭의 편평도가 고르게 유지될 수 있도록 한 것을 특징으로 하는 반도체 패키지 제조용 스테이지 블럭을 제공한다.In order to achieve the above object, the present invention manufactures the stage block on which the counterpart is mounted with a material having a low coefficient of thermal expansion, so that the flatness of the stage block can be evenly maintained even at a high temperature condition in which bumps of the semiconductor chip are fused to the counterpart. A stage block for manufacturing a semiconductor package is provided.

바람직한 구현예로서, 상기 스테이지 블럭은 낮은 열팽창 계수를 갖는 산화 알루미나 재질로 제작된 것임을 특징으로 한다.In a preferred embodiment, the stage block is made of alumina oxide material having a low coefficient of thermal expansion.

더욱 바람직하게는, 상기 스테이지 블럭은 세라믹 재질로 성형되고, 그 상면이 산화 알루미나 재질로 코팅된 것임을 특징으로 한다.
More preferably, the stage block is formed of a ceramic material, the upper surface is characterized in that the coated with alumina oxide material.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above-mentioned means for solving the problems, the present invention provides the following effects.

본 발명에 따르면, 반도체 칩의 범프를 상대부품에 융착시키는 공정에 있어서, 적층 대상의 상대부품(기판, 적층 대상 칩)이 안착되는 스테이지 블럭의 재질을 산화알루미나와 같은 낮은 열팽창계수를 갖는 재질로 형성함으로써, 반도체 칩의 범프를 상대부품에 융착시키는 고온 조건에서도 스테이지 블럭의 편평도가 고르게 유지될 수 있다.According to the present invention, in the step of fusing the bumps of the semiconductor chip to the counterpart parts, the material of the stage block on which the counterpart parts (substrate, the stacking chip) to be stacked is placed may be formed of a material having a low coefficient of thermal expansion such as alumina oxide. By forming, the flatness of the stage block can be maintained even in a high temperature condition in which bumps of the semiconductor chip are fused to the counterpart parts.

또한, 스테이지 블럭의 편평도가 고르게 유지됨에 따라, 적층 대상의 상대부품에 반도체 칩의 범프가 융착될 때, 미스 어라인먼트 현상이 발생됨 없이 융착될 수 있고, 이에 범프의 우수한 융착 품질을 제공할 수 있다.In addition, as the flatness of the stage block is maintained evenly, when the bumps of the semiconductor chip are fused to the mating parts to be stacked, a misalignment phenomenon can be fused without occurrence, thereby providing excellent fusion quality of the bumps. have.

또한, 적층 대상의 상대부품에 반도체 칩의 범프가 융착될 때, 미스 어라인먼트 현상을 방지할 수 있을 뿐만 아니라, 다이 틸트(die tilt) 현상 즉, 다이 틸트에 의한 논웨트(non-wet) 불량도 방지할 수 있는 장점이 있다.
In addition, when the bumps of the semiconductor chip are fused to the mating parts to be stacked, not only the misalignment phenomenon can be prevented, but also the die tilt phenomenon, that is, non-wet due to die tilt. It also has the advantage of preventing defects.

도 1a 및 도 1b는 본 발명에 따른 반도체 패키지 제조용 스테이지 블럭을 나타낸 개략도,
도 2는 본 발명의 스테이지 블럭과 종래의 스테이지 블럭에 대한 편평도 측정 위치를 나타낸 개략도,
도 3은 본 발명의 스테이지 블럭과 종래의 스테이지 블럭에 대한 편평도 측정 결과를 나타낸 그래프,
도 4는 종래의 반도체 패키지 제조용 스테이지 블럭을 나타낸 개략도.1A and 1B are schematic views showing a stage block for manufacturing a semiconductor package according to the present invention;
Figure 2 is a schematic diagram showing the flatness measurement position for the stage block of the present invention and the conventional stage block,
Figure 3 is a graph showing the flatness measurement results for the stage block and the conventional stage block of the present invention,
4 is a schematic view showing a stage block for manufacturing a conventional semiconductor package.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 반도체 칩의 범프를 적층 대상의 상대부품(인쇄회로기판 또는 적층 대상 칩)에 융착시키기 위한 써멀 컴프레션 방식의 본딩 방법(TCNCP: Thermal Compression Non Conductive Paste)에 사용되는 스테이지 블럭을 제공하고자 한 것으로서, 상대부품인 적층 대상의 칩 또는 기판이 등이 안정적으로 안착될 수 있도록 스테이지 블럭의 편평도가 고르게 유지될 수 있도록 한 점에 주안점이 있다.An object of the present invention is to provide a stage block used for a thermal compression bonding method (TCNCP) for fusion bonding bumps of a semiconductor chip to a counterpart component (a printed circuit board or a stack target chip). The main focus is that the flatness of the stage block can be maintained evenly so that the chip or the substrate to be stacked as the counterpart can be stably seated.

전술한 바와 같이, 반도체 칩의 전극패드(=본딩패드)에 솔더 또는 금속 재질의 범프를 형성하고, 이 범프를 적층 대상의 상대부품인 반도체 칩 또는 인쇄회로기판의 전도성패턴에 전기적으로 연결시킴으로써, 경박단소화를 실현할 수 있는 반도체 패키지가 제안되고 있으며, 상기 범프는 구리 도금 공정을 진행하여 반도체 칩의 본딩패드 상에 소정의 높이로 형성되는 구리필러와, 이 구리필러의 상면에 일체로 형성되는 전도성 솔더로 구성된다.As described above, bumps made of solder or metal are formed on the electrode pads (= bonding pads) of the semiconductor chip, and the bumps are electrically connected to the conductive patterns of the semiconductor chip or the printed circuit board, which are the counterparts to be stacked. A semiconductor package capable of realizing light and short reduction has been proposed, and the bumps are formed on the bonding pad of the semiconductor chip by a copper plating process, and are formed integrally with the upper surface of the copper filler. Consists of conductive solder.

첨부한 도 1a 및 도 1b에 도시된 바와 같이, 상기 반도체 칩(32)의 본딩패드에 구리필러(22) 및 전도성 솔더(24)로 이루어진 범프(20)가 일체로 형성된 상태에서, 각 범프(20)가 상대 칩 또는 기판과 같은 상대부품(34)의 본딩영역 등에 본딩된다.As illustrated in FIGS. 1A and 1B, bumps 20 formed of a copper filler 22 and a conductive solder 24 are integrally formed on a bonding pad of the semiconductor chip 32. 20 is bonded to a bonding area of the counterpart component 34 such as a counterpart chip or a substrate.

즉, 상대부품(34)이 스테이지 블럭(10) 상에 안착된 상태에서, 범프(20)가 형성된 반도체 칩(32)을 써멀 컴프레션 방식의 본딩 방법(TCNCP: Thermal Compression Non Conductive Paste)을 이용하여 상대부품(34)의 본딩영역에 접착하되, 범프(20)의 전도성솔더(24)가 상대부품(34)의 본딩영역에 융착되며 적층 부착된다.That is, in the state in which the counterpart 34 is seated on the stage block 10, the semiconductor chip 32 having the bumps 20 formed thereon is bonded using a thermal compression bonding method (TCNCP: Thermal Compression Non Conductive Paste). Bonded to the bonding region of the mating component 34, but the conductive solder 24 of the bump 20 is fused to the bonding region of the mating component 34 and laminated.

상기 스테이지 블럭(10)은 상대부품(34)인 인쇄회로기판또는 적층 대상 칩이 안착되어 대기되는 곳으로서, 본 발명은 스테이지 블럭(10)을 낮은 열팽창 계수를 갖는 재질로 제작하여 반도체 칩(32)의 범프(20)가 상대부품(34)에 융착되는 고온 조건에서도 스테이지 블럭(10)의 표면이 아무런 변형없이 고른 편평도를 유지할 수 있도록 한 점에 특징이 있다.The stage block 10 is a place where the printed circuit board or the stacking target chip, which is the counterpart component 34, is seated and waiting. The present invention provides a semiconductor chip 32 by fabricating the stage block 10 with a material having a low coefficient of thermal expansion. ) Is characterized in that the surface of the stage block 10 can maintain an even flatness without any deformation even in a high temperature condition in which the bump 20 of the bump 20 is fused to the counterpart component 34.

바람직하게는, 도 1a에서 보듯이 본 발명의 스테이지 블럭(10)은 그 전체가 낮은 열팽창 계수를 갖는 산화 알루미나 재질을 이용하여 성형 제작된다.Preferably, as shown in FIG. 1A, the stage block 10 of the present invention is molded and manufactured using an alumina oxide material having a low coefficient of thermal expansion as a whole.

더욱 바람직하게는, 도 1b에서 보듯이 본 발명의 스테이지 블럭(10)은 몸체를 이루는 부분을 세라믹 재질로 성형하고, 이 세라믹 몸체의 표면을 낮은 열팽창계수를 갖는 산화 알루미나 재질로 코팅하여 제작된다.More preferably, as shown in FIG. 1B, the stage block 10 of the present invention is manufactured by molding a portion constituting the body with a ceramic material and coating the surface of the ceramic body with alumina oxide material having a low coefficient of thermal expansion.

여기서, 본 발명에 따른 스테이지 블럭 및 이를 이용한 TCNCP 방법을 첨부한 도 1a 및 도 1b를 참조로 설명하면 다음과 같다.Herein, a stage block and a TCNCP method using the same according to the present invention will be described with reference to FIGS. 1A and 1B.

먼저, 본딩 툴(30)이 범프(20)를 갖는 반도체 칩(32)을 진공 흡착한 다음, 상대부품(34, 적층 대상 칩 또는 기판 등)이 안착된 열압착 본딩부(38)의 스테이지 블럭(10)쪽으로 이송한 후, 본딩 툴(20)이 상대부품(34)쪽으로 하강을 한다.First, the bonding tool 30 vacuum-adsorbs the semiconductor chip 32 having the bumps 20, and then the stage block of the thermocompression bonding portion 38 on which the counterpart 34 (a stacking target chip or substrate, etc.) is seated. After conveying to the (10) side, the bonding tool 20 descends toward the mating component 34.

연속해서, 반도체 칩(32)의 범프(20)가 적층 대상의 상대부품(34)의 본딩영역에 접촉되는 상태가 되고, 이에 열과 압력을 가하는 열압착 방식에 의하여 범프(20)가 상대부품(34)의 본딩영역에 융착된다.Subsequently, the bump 20 of the semiconductor chip 32 is brought into contact with the bonding region of the counterpart component 34 to be stacked, and the bump 20 is connected to the counterpart part by a thermocompression bonding method that applies heat and pressure thereto. 34) is bonded to the bonding area.

즉, 범프(20)를 융착시키기 전에 상대부품(34)의 본딩영역을 포함하는 표면에 걸쳐 접착제의 일종인 비전도성 페이스트(NCP: Non Conductive Paste)를 미리 도포하는 과정과, 본딩 툴(30)이 하강을 하여 반도체 칩(32)의 범프(20)가 경화 전 상태인 비전도성 페이스트(36)를 뚫고 상대부품(34)의 본딩영역에 안착되는 과정과, 열과 압력이 인가되는 상태에서 본딩 툴(30)이 반도체 칩(32)을 소정의 힘으로 가압하여 범프(20)의 전도성 솔더(24) 부분이 상대부품(34)의 본딩영역에 융착되는 과정 등을 통하여, 범프(20)를 매개로 반도체 칩(32)이 상대부품(34)에 전기적 신호 교환 가능하게 적층 부착된다.That is, before the bumps 20 are fused, a process of applying a non-conductive paste (NCP), which is a kind of adhesive, in advance over the surface including the bonding area of the counterpart 34, and the bonding tool 30. This lowering process allows the bump 20 of the semiconductor chip 32 to penetrate through the non-conductive paste 36, which is a state before curing, and to be seated in the bonding region of the counterpart component 34, and a bonding tool in a state where heat and pressure are applied. The bump 20 may be mediated through a process in which the 30 presses the semiconductor chip 32 with a predetermined force and the conductive solder 24 of the bump 20 is fused to the bonding region of the counterpart 34. The semiconductor chip 32 is laminated and attached to the counterpart 34 so as to exchange electrical signals.

이때, 상기 상대부품(34)이 안착된 열압착 본딩부(38)의 스테이지 블럭(10) 은 낮은 열팽창계수를 갖는 산화 알루미늄 재질로 제작됨에 따라, 반도체 칩(32)의 범프(20)를 상대부품(34)에 융착시키는 고온 조건에서도 스테이지 블럭(10)의 편평도가 고르게 유지될 수 있다.At this time, the stage block 10 of the thermocompression bonding portion 38 on which the mating component 34 is seated is made of aluminum oxide having a low coefficient of thermal expansion, thereby facing the bump 20 of the semiconductor chip 32. The flatness of the stage block 10 can be maintained even in high temperature conditions fused to the component 34.

이렇게, 본 발명의 스테이지 블럭(10)의 편평도가 고르게 유지됨에 따라, 적층 대상의 상대부품(34)에 반도체 칩(32)의 범프(20)가 융착될 때, 미스 어라인먼트 현상이 발생됨 없이 융착될 수 있다.Thus, as the flatness of the stage block 10 of the present invention is maintained evenly, when the bump 20 of the semiconductor chip 32 is fused to the counterpart component 34 to be stacked, a misalignment phenomenon does not occur. Can be fused.

시험예로서, 산화 알루미나 재질로 된 본 발명의 스테이지 블럭과, SiC 재질로 된 기존의 세라믹 스테이지 블럭에 대한 편평도를 동일한 조건에서 측정하였다.As a test example, the flatness of the stage block of the present invention made of alumina oxide and the conventional ceramic stage block made of SiC was measured under the same conditions.

측정 방법은 본 발명의 스테이지 블럭과 기존의 스테이지 블럭을 70℃로 히팅한 상태에서, 도 2에서 보듯이 가로 및 세로 방향을 따라 서로 교차하는 총 15개의 지점을 다이얼 게이지를 이용하여 측정하되, 기준점인 포인트 "1"을 제로(zero)로 셋팅하여 측정하였는 바, 그 결과는 아래의 표 1 및 도 3에 나타낸 바와 같다.In the measurement method, while the stage block of the present invention and the existing stage block are heated at 70 ° C., as shown in FIG. 2, a total of 15 points crossing each other along the horizontal and vertical directions are measured using a dial gauge, It was measured by setting the in point "1" to zero, and the result is as shown in Table 1 and FIG. 3 below.

Figure pat00001
Figure pat00001

위의 표 1 및 도 3에서 보듯이, 본 발명의 스테이지 블럭은 어떤 위치에서는 위쪽으로 2마이크로미터, 또 다른 위치에서는 아래쪽으로 -2마이크로미터 정도 편평도 차이를 나타내고, 총 4마이크로미터의 편평도 편차를 나타냄을 알 수 있었다.As shown in Table 1 and FIG. 3 above, the stage block of the present invention exhibits a flatness difference of about 2 micrometers upward in some positions and -2 micrometers downward in another position, and shows a flatness deviation of 4 micrometers in total. It can be seen that.

반면, 종래의 스테이지 블럭은 어떤 위치에서는 위쪽으로 3마이크로미터, 또 다른 위치에서는 아래쪽으로 -10마이크로미터 정도 편평도 차이를 나타내고, 총 13마이크로미터의 편평도 편차를 나타냄을 알 수 있었다.On the other hand, the stage block of the related art shows a flatness difference of about 3 micrometers upward in some positions and -10 micrometers downward in another position, and a flatness deviation of 13 micrometers in total.

이와 같이, 본 발명의 스테이지 블럭의 경우, 낮은 열팽창계수를 갖기 때문에 반도체 칩의 범프를 상대부품에 융착시키는 고온 조건에서도 그 편평도가 고르게 유지될 수 있고, 이에 적층 대상의 상대부품에 반도체 칩의 범프가 융착될 때, 미스 어라인먼트 현상이 발생됨 없이 정확하게 융착될 수 있고, 뿐만 아니라 다이 틸트(die tilt) 현상 즉, 다이 틸트에 의한 논웨트(non-wet) 불량도 방지할 수 있다.
As described above, the stage block of the present invention has a low coefficient of thermal expansion, so that even in high temperature conditions in which bumps of the semiconductor chips are fused to the counterpart parts, their flatness can be maintained evenly. When is fused, it is possible to fusion accurately without a misalignment phenomenon occurring, as well as to prevent the die tilt phenomenon, that is, non-wet defects due to die tilt.

10 : 스테이지 블럭 20 : 범프
22 : 구리필러 24 : 전도성 솔더
30 : 본딩 툴 32 : 반도체 칩
34 : 상대부품 36 : 비전도성 페이스트
38 : 열압착 본딩부10: stage block 20: bump
22: copper filler 24: conductive solder
30: bonding tool 32: semiconductor chip
34: counterpart 36: non-conductive paste
38: thermocompression bonding part

Claims (3)

상대부품이 안착되는 스테이지 블럭을 낮은 열팽창 계수를 갖는 재질로 제작하여, 반도체 칩의 범프가 상대부품에 융착되는 고온 조건에서도 스테이지 블럭의 편평도가 고르게 유지될 수 있도록 한 것을 특징으로 하는 반도체 패키지 제조용 스테이지 블럭.
The stage block on which the counterpart is mounted is made of a material having a low coefficient of thermal expansion, so that the flatness of the stage block can be evenly maintained even at a high temperature condition in which bumps of the semiconductor chip are fused to the counterpart. block.
청구항 1에 있어서,
상기 스테이지 블럭은 낮은 열팽창 계수를 갖는 산화 알루미나 재질로 제작된 것임을 특징으로 하는 반도체 패키지 제조용 스테이지 블럭.
The method according to claim 1,
The stage block is a stage block for manufacturing a semiconductor package, characterized in that made of alumina oxide material having a low coefficient of thermal expansion.
청구항 1에 있어서,
상기 스테이지 블럭은 세라믹 재질로 성형되고, 그 상면이 산화 알루미나 재질로 코팅된 것임을 특징으로 하는 반도체 패키지 제조용 스테이지 블럭.The method according to claim 1,
The stage block is formed of a ceramic material, the upper surface is a stage block for manufacturing a semiconductor package, characterized in that the coating is made of alumina oxide material.
KR1020110010494A 2011-02-07 2011-02-07 Stage block for manufacturing semiconductor package KR20120090202A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016050467A1 (en) * 2014-09-29 2016-04-07 Danfoss Silicon Power Gmbh Sintering tool for the lower die of a sintering device
KR20190120955A (en) * 2018-04-17 2019-10-25 주식회사 엘지화학 Bonding apparatus and method
US10483229B2 (en) 2014-09-29 2019-11-19 Danfoss Silicon Power Gmbh Sintering device
US10814396B2 (en) 2014-09-29 2020-10-27 Danfoss Silicon Power Gmbh Sintering tool and method for sintering an electronic subassembly
US11776932B2 (en) 2014-09-29 2023-10-03 Danfoss Silicon Power Gmbh Process and device for low-temperature pressure sintering

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016050467A1 (en) * 2014-09-29 2016-04-07 Danfoss Silicon Power Gmbh Sintering tool for the lower die of a sintering device
CN107004611A (en) * 2014-09-29 2017-08-01 丹佛斯硅动力有限责任公司 Sintering instrument for the lower mould of sintering equipment
US10483229B2 (en) 2014-09-29 2019-11-19 Danfoss Silicon Power Gmbh Sintering device
US10818633B2 (en) 2014-09-29 2020-10-27 Danfoss Silicon Power Gmbh Sintering tool for the lower die of a sintering device
US10814396B2 (en) 2014-09-29 2020-10-27 Danfoss Silicon Power Gmbh Sintering tool and method for sintering an electronic subassembly
US11776932B2 (en) 2014-09-29 2023-10-03 Danfoss Silicon Power Gmbh Process and device for low-temperature pressure sintering
KR20190120955A (en) * 2018-04-17 2019-10-25 주식회사 엘지화학 Bonding apparatus and method

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