KR20120086860A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR20120086860A
KR20120086860A KR1020110008172A KR20110008172A KR20120086860A KR 20120086860 A KR20120086860 A KR 20120086860A KR 1020110008172 A KR1020110008172 A KR 1020110008172A KR 20110008172 A KR20110008172 A KR 20110008172A KR 20120086860 A KR20120086860 A KR 20120086860A
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KR
South Korea
Prior art keywords
delay
mode
clock signal
control signals
response
Prior art date
Application number
KR1020110008172A
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Korean (ko)
Inventor
김용훈
박기덕
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020110008172A priority Critical patent/KR20120086860A/en
Publication of KR20120086860A publication Critical patent/KR20120086860A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used

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Abstract

PURPOSE: A semiconductor memory device is provided to sufficiently secure the read margin of an external controller by tuning an AC parameter within a preset range according to a stack package mode. CONSTITUTION: A control signal generating unit(110) generates a plurality of control signals corresponding to a stack package mode in response to an address and a command. An internal circuit tunes an AC parameter in response to the plurality of the control signals. A delay locked loop(120) generates a delay locked clock signal by delaying an external clock signal according to the plurality of the clock signals. A data strobe signal generating unit generates a data strobe signal in response to a delay locked clock signal.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

TECHNICAL FIELD The present invention relates to semiconductor design technology, and more particularly, to an AC parameter control technology of a semiconductor memory device.

In general, semiconductor memory devices, such as Dynamic Random Access Memory (DRAM), stack and package a plurality of semiconductor chips (or dies) to obtain greater capacity in a single area. For example, a semiconductor memory device in which only one semiconductor chip is stacked and packaged is called a single die package (SDP), and a semiconductor memory device in which two semiconductor chips are stacked and packaged is called a dual die package (DDP). A semiconductor memory device in which a semiconductor chip is stacked and packaged is referred to as a quad die package (QDP). Here, 'DDP' and 'QDP' cause the AC parameter 'tDQSCK' to be pushed down compared to 'SDP'. The reason is that the length of the bonding wire for outputting the data strobe signal included in the 'DDP' and the 'QDP' is longer than that of the 'SDP', thereby increasing the self-loading of the bonding wire. For reference, 'tDQSCK' is a parameter representing a skew between the external clock signal and the data strobe signal during the read operation.

'TDQSCK', on the other hand, has a defined range as defined in the specification. However, 'DDP' and 'QDP' may have a longer length of the data strobe signal output bonding wire than 'SDP', and thus 'tDQSCK' may be out of the prescribed range. In this case, a problem occurs that an error occurs during a read operation.

An object of the present invention is to provide a semiconductor memory device in which the AC parameter tDQSCK is controlled so as not to be out of the range defined in the specification according to the stack package mode.

According to an aspect of the present invention, a control signal generation unit for generating a plurality of control signals corresponding to the stack package mode in response to an address and a command; And internal circuitry for tuning AC parameters in response to a plurality of control signals.

According to another aspect of the invention, the present invention includes a mode signal generator for generating a plurality of mode signals in response to at least one address and at least one command; A control signal decoder for decoding the plurality of control signals corresponding to the stack package mode in response to the plurality of mode signals; And a delay lock loop for tuning the AC parameter in accordance with the plurality of control signals.

In this case, the stack package mode includes a single die package (SDP) mode, a dual die package (DDP) mode, and a quad die package (QDP) mode.

In addition, the AC parameter refers to a parameter tDQSCK indicating a skew between the external clock signal and the data strobe signal during the read operation.

According to the present invention, the AC parameter tDQSCK is tuned within the range defined in the specification according to the stack package mode, thereby sufficiently securing the lead margin of the external controller. Therefore, there is an effect that a malfunction is prevented during a read operation.

1 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.
FIG. 2 is a block diagram illustrating an example of a control signal generator shown in FIG. 1. FIG.
FIG. 3 is a block diagram illustrating an example of a delay locked loop (DLL) shown in FIG. 1.
4 is an internal circuit diagram showing an example of the replica delay shown in FIG.
FIG. 5 is a table for explaining an operation of the semiconductor memory device shown in FIG. 1; FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor memory device 100 may include a plurality of control signals corresponding to a stack package mode in response to a plurality of addresses ADD <0: N> and a plurality of commands CMD <0: M>. Delay locked loop for tuning the AC parameter in response to a control signal generator 110 for generating TM_CTRL <0: P> and a plurality of control signals TM_CTRL <0: P>. Loop: DLL) (120).

Here, the stack package mode includes a single die package (SDP) mode in which only one semiconductor chip is stacked in a semiconductor memory device, and a dual die package (DDP) mode in which two semiconductor chips are stacked in a semiconductor memory device. And a 'Quad Die Package' mode in which four semiconductor chips are stacked and packaged in a semiconductor memory device.

In addition, the AC parameter refers to a parameter tDQSCK indicating a skew between the external clock signal and the data strobe signal during the read operation.

2 is a block diagram showing an example of the control signal generator 110 shown in FIG.

Referring to FIG. 2, the control signal generation unit 110 responds to a plurality of addresses ADD <0: N> and a plurality of commands CMD <0: M> and a plurality of mode signals MRS <0: R. And a mode signal generator 112 to generate a plurality of control signals TM_CTRL <0: P> corresponding to the stack package mode in response to the plurality of mode signals MRS <0: R>. And a control signal decoder 114 for

Here, the mode signal generator 112 includes a mode register set (MRS), and the plurality of mode signals MRS <0: R> output from the mode register set (MRS) are external controllers (drawings). (Not shown) is an arbitrary code signal that is not used.

In addition, the control signal decoder 114 is a test decoder used in the test mode, for example, serves to tune the modeled delay amount of the replica delay 124 described below in the test mode.

FIG. 3 is a block diagram showing an example of the delay locked loop 120 shown in FIG. 1, and FIG. 4 is an internal circuit diagram showing an example of the replica delay 124 shown in FIG.

Referring to FIG. 3, the delay lock loop 120 delays the external clock signal CLK_EXT by a delay time necessary for delay lock, and outputs a delay line 122 for outputting the delay locked clock signal CLK_DLL. Phase of the external clock signal CLK_EXT and the feedback clock signal CLK_FB, and a replica delay 124 for outputting the feedback clock signal CLK_FB by delaying the clock signal CLK_DLL by the delay time for which the internal delay element is modeled. The phase comparator 126 for comparing the signal and the control signal DELY_CTR <0: S> for adjusting the delay time required for delay lock in response to the output signal UP / DOWN of the phase comparator 126. And a delay amount adjuster 128 for outputting to the delay line 122.

Here, the replica delay 124 is implemented such that its modeled delay time is adjusted according to the plurality of control signals TM_CTRL <0: P>. For example, the replica delay 124 may include a plurality of first negations for selectively delivering a delay fixed clock signal CLK_DLL in response to a plurality of control signals TM_CTRL <0: P>. The feedback clock signal CLK_FB reflects a predetermined delay amount in the delayed fixed clock signal CLK_DLL transmitted from one of the AND gates NAND0 to NANDP and the plurality of first negative logic gates NAND0 to NANDP. A plurality of second negative logical gates (NAND'0 to NAND'2P-1) for outputting the signal. In other words, the replica delay 124 includes a plurality of first negative logical gates NAND0 to NANDP, and a plurality of second negative logical gates NAND'0 to NAND'2P-1. One negative logic gates NAND0 to NANDP and a plurality of second negative logic gates NAND'0 to NAND'2P-1 are all composed of two-input negative logic gates. In this case, each of the plurality of first negative logical gates NAND0 to NANDP uses one delayed fixed clock signal CLK_DLL as one input and each control signal TM_CTRL <#> as the other input. Since the plurality of second negative logical gates NAND'0 to NAND'2P-1 each have an output of the second negative logical gate disposed at the front end as one input, the second negative logical gates NAND'0 to NAND'2P-1 have a series connection structure. However, since only the second negative logic gate NAND'2P disposed at the rearmost end has no second negative logic gate disposed at the front end, the predetermined power supply voltage VDDL is used as one input. In addition, the second negative logical gates NAND'0 to NAND'2P-1 may be odd-numbered based on the second negative logical gate NAND'0 for outputting the feedback clock signal CLK_FB. The second negative logic gates NAND'0, NAND'2, NAND4, ..., NAND'2P are arranged to have the output of each of the first negative logic gates NAND0 to NANDP as the other input, and even The second negative logic gates NAND'1, NAND'3, ..., and NAND'2P-1 arranged in the second have the predetermined power supply voltage VDDL as the other input.

Although not shown in the drawing, the semiconductor memory device 100 further includes a data strobe signal generator for generating a data strobe signal in response to the delayed fixed clock signal CLK_DLL output through the delay locked loop 120. do. That is, the data strobe signal is a signal derived from the delay locked clock signal CLK_DLL, and the phase of the delay locked clock signal CLK_DLL and the phase of the data strobe signal are the same. Therefore, when the phase of the delay-fixed clock signal CLK_DLL is adjusted, the phase of the data strobe signal is also adjusted in the same manner, so that 'tDQSCK', a parameter representing a skew between the data strobe signal and the external clock signal, can be tuned. .

Hereinafter, an operation of the semiconductor memory device 100 having the above configuration will be described with reference to FIG. 5.

FIG. 5 illustrates a table for describing a process of adjusting a delay amount of a replica delay according to a stack package mode in describing an operation of the semiconductor memory device 100 illustrated in FIG. 1.

In the embodiment of the present invention, for convenience of description, the plurality of mode signals MRS <0: R> are described as examples of the first and second mode signals MRS <0: 1>, and the plurality of control signals An example of TM_CTRL <0: P> as the first to fourth control signals TM_CTRL <0: 3> will be described.

First, prior to referring to FIG. 5, the overall operation of the semiconductor memory device 100 will be briefly described. The mode signal generator 112 may output the first and second mode signals MRS <0: 1> in response to a plurality of addresses ADD <0: N> and a plurality of commands CMD <0: M>. Create Then, the control signal decoder 114 decodes the first and second mode signals MRS <0: 1> to generate the first to fourth control signals TM_CTRL <0: 3> corresponding to the stack package mode. do. Accordingly, the delay locked loop 120 tunes 'tDQSCK' in response to the first to fourth control signals TM_CTRL <0: 3>. Hereinafter, a process of tuning 'tDQSCK' will be described in more detail with reference to FIG. 5.

Referring to FIG. 5, the control signal decoder 114 may include first to fourth control signals TM_CTRL <0: 3 corresponding to the stack package mode in response to the first and second mode signals MRS <0: 1>. >) For example, when the first and second mode signals MRS <0: 1> are '00', the control signal decoder 114 may have the first to fourth control signals TM_CTRL of '1000' corresponding to the 'SDP' mode. <0: 3>) and when the first and second mode signals MRS <0: 1> are '10', the first to fourth control signals '0100' corresponding to the 'DDP' mode ( TM_CTRL <0: 3>) and the first to fourth control signals of '0010' corresponding to the 'QDP' mode when the first and second mode signals MRS <0: 1> are '01'. Outputs (TM_CTRL <0: 3>).

Here, referring to the case of the 'SDP' mode, the replica delay 124 first receives the delayed clock signal CLK_DLL according to the first to fourth control signals TM_CTRL <0: 3> of '1000'. By outputting through the arranged first negative logic gate NAND0, the feedback clock signal CLK_FB reflecting only the default delay amount is output.

In the case of the 'DDP' mode, the replica delay 124 may secondly delay the clock signal CLK_DLL that is delay-fixed according to the first to fourth control signals TM_CTRL <0: 3> of '0100'. By outputting through the arranged first negative logic gate NAND1, the feedback clock signal CLK_FB reflecting the delay amount corresponding to the 'DDP' mode, which has a larger delay amount than the 'SDP' mode, is output.

In addition, referring to the case of the 'QDP' mode, the replica delay 124 thirdly delays the clock signal CLK_DLL which is delayed and fixed according to the first to fourth control signals TM_CTRL <0: 3> of '0010'. The feedback clock signal CLK_FB reflects the delay amount corresponding to the 'QDP' mode, which has a larger delay amount than the 'DDP' mode, by outputting through the arranged first negative logic gate NAND2.

As the semiconductor memory device stacks more semiconductor chips as described above, as the length of the bonding wire (not shown) for outputting the data strobe signal becomes longer, the delay amount of the replica delay 124 is adjusted to reflect more delay elements. Done.

Meanwhile, when the delay amount of the replica delay 124 is adjusted according to the stack package mode according to the first to fourth control signals TM_CTRL <0: 3>, the delay lock loop 120 adjusts the replica delay adjusted as described above. The delayed clock signal CLK_DLL is output by delaying the external clock signal CLK_EXT by a delay time necessary for delay lock based on the delay amount of 124. Then, the data strobe signal generator (not shown) generates the data strobe signal in response to the delay-fixed clock signal CLK_DLL, and the generated data strobe signal is associated with the corresponding pad (not shown in the figure) and the corresponding bonding. It is output via a wire and finally delivered to an external controller (not shown). Therefore, the data strobe signal transmitted to the external controller is in a phase-adjusted state corresponding to the stack package mode, and 'tDQSCK' does not go out of the range defined in the specification according to the phase-adjusted data strobe signal.

According to this embodiment of the present invention, by tuning 'tDQSCK' according to the stack package mode, there is an advantage that the malfunction during the read operation is prevented.

Although the technical spirit of the present invention has been described in detail with reference to the above embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

For example, in the exemplary embodiment of the present invention, a parameter tDQSCK indicating a skew between an external clock signal and a data strobe signal is described as an example, but the present invention is not limited thereto. The data setup time tDS and the data hold time tDH are not limited thereto. The present invention can also be applied to correcting AC parameters such as the above.

100: semiconductor memory device 110: control signal generator
112: mode signal generator 114: control signal decoder
120: delay lock loop (DLL) 122: delay line
124: replica delay 126: phase comparison unit
128: delay amount control unit

Claims (13)

A control signal generator for generating a plurality of control signals corresponding to the stack package mode in response to the address and the command; And
Internal circuitry for tuning an AC parameter in response to the plurality of control signals
And a semiconductor memory device.
The method of claim 1,
The internal circuit,
A delay locked loop (DLL) for generating a delay locked clock signal by delaying an external clock signal by a predetermined delay time according to the plurality of control signals; And
And a data strobe signal generator for generating a data strobe signal in response to the delayed clock signal.
The method of claim 2,
The delay lock loop is configured to adjust the predetermined delay time according to the plurality of control signals, and output the delay locked clock signal reflecting the adjusted delay time.
The method of claim 1,
The stack package mode may include a single die package (SDP) mode, a dual die package (DDP) mode, and a quad die package (QDP) mode.
The method of claim 1,
And the AC parameter is a parameter tDQSCK indicating a skew between an external clock signal and a data strobe signal during a read operation.
A mode signal generator for generating a plurality of mode signals in response to at least one address and at least one command;
A control signal decoder for decoding a plurality of control signals corresponding to a stack package mode in response to the plurality of mode signals; And
A delay lock loop for tuning an AC parameter according to the plurality of control signals
And a semiconductor memory device.
The method of claim 6,
The mode signal generator includes a mode register set (MRS).
The method of claim 7, wherein
And the plurality of mode signals are any code signals output from the mode register set.
The method of claim 6,
And the decoder is a test decoder for tuning the delayed amount of delay of the replica delay in a test mode.
The method of claim 6,
The delay lock loop,
A delay line configured to delay an external clock signal by a delay time necessary for delay lock to output a delay locked clock signal;
A replica delay for delaying the delayed clock signal by a delay time modeled by an internal delay element and outputting a feedback clock signal;
A phase comparator for comparing phases of the external clock signal and the feedback clock signal; And
And a delay amount adjusting unit for outputting an adjustment signal for adjusting the delay time required for the delay fixing to the delay line in response to an output signal of the phase comparing unit.
The method of claim 10,
The modeled delay time of the replica delay is adjusted according to the plurality of control signals.
The method of claim 6,
The stack package mode may include a single die package (SDP) mode, a dual die package (DDP) mode, and a quad die package (QDP) mode.
The method of claim 6,
And the AC parameter is a parameter tDQSCK indicating a skew between an external clock signal and a data strobe signal during a read operation.
KR1020110008172A 2011-01-27 2011-01-27 Semiconductor memory device KR20120086860A (en)

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