KR20120077562A - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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KR20120077562A
KR20120077562A KR1020100139559A KR20100139559A KR20120077562A KR 20120077562 A KR20120077562 A KR 20120077562A KR 1020100139559 A KR1020100139559 A KR 1020100139559A KR 20100139559 A KR20100139559 A KR 20100139559A KR 20120077562 A KR20120077562 A KR 20120077562A
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South Korea
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numbered
lines
common electrode
odd
voltage
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KR1020100139559A
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Korean (ko)
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이도영
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엘지디스플레이 주식회사
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Priority to KR1020100139559A priority Critical patent/KR20120077562A/en
Publication of KR20120077562A publication Critical patent/KR20120077562A/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

There is provided a liquid crystal display device which can improve the flicker phenomenon and the horizontal crosstalk phenomenon. The liquid crystal display includes a plurality of gate lines formed on an insulating substrate, a plurality of data lines formed to intersect the plurality of gate lines, and a plurality of pixels formed in an area where the plurality of gate lines and the plurality of data lines intersect. And a plurality of common electrode lines formed between the plurality of gate lines, a plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines, and connected to the plurality of pixels. A voltage having the opposite polarity of the voltage applied to the odd-numbered data line is applied to the even-numbered data line, and an opposite polarity of the voltage applied to the odd-numbered common electrode line to the even-numbered common electrode line of the plurality of common electrode lines. Voltage is applied.

Description

[0001] Liquid crystal display device [0002]

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that can improve the flicker phenomenon and the horizontal crosstalk phenomenon.

In general, a liquid crystal display (LCD) can display a desired image by individually controlling data transmittance of pixels by separately supplying data signals according to image information to pixels arranged in an active matrix form. Display device.

Such a liquid crystal display device is a light-receiving display device that does not emit light by itself, and thus requires a backlight unit installed on a rear surface of the liquid crystal panel for displaying an image to maintain uniform brightness of the entire screen.

In general, the liquid crystal display device can be divided into several methods depending on the method of operating the liquid crystal molecules, but the active matrix thin film transistor is mainly used because of the fast reaction speed and low afterimage. Mainly used.

Herein, a method of driving a liquid crystal panel displaying an image includes line inversion, column inversion, and dot inversion depending on a phase of a data signal applied to a data line (not shown). And frame inversion.

In this case, the line inversion method is a method of inverting and applying a phase of a data signal applied to a data line for each line, and the column inversion method is a method of inverting and applying a phase of a data signal applied to a data line for each column. The dot inversion method is a method in which the polarity of the voltage applied to the data line is inverted and applied at the same time for each column and line, and the frame inversion method is a frame ((N-3)) sequentially input to the liquid crystal display device. Inversion is performed between neighboring frames among F, (N-2) F, (N-1) F, (N) F, (N + 1) F, and (N + 2) F), but any neighbor 2 There are no inversions between the two frames (N) F and (N-1) F. That is, the N-frame inversion driving method inverts a plurality of frames which are sequentially input in order, but does not invert adjacently input frames at every specific time by dividing the plurality of input frames into a certain number of frame units. .

1A and 1B illustrate a conventional dot inversion scheme, FIG. 2A illustrates a voltage applied to a pixel in an N frame, and FIG. 2B illustrates a voltage applied to a pixel in an N + 1 frame.

1A and 1B, the dot inversion scheme includes a plurality of pixels R 11 , G 12 , B 13 , R 14 , G 15 , and B 16 connected to a first gate line (not shown) in an N frame. ) And the polarities of the plurality of pixels R 21 , G 22 , B 23 , R 24 , G 25 , and B 26 connected to the second gate line (not shown) are inverted. For example, the data voltages Vdata applied to the first pixels R 11 to the sixth pixel B 16 connected to the first gate line in the N frame are all different polarities, as shown in FIG. 2A. It has polarity of (+), (-), (+), (-), (+), and (-). In addition, as shown in FIG. 2B, the data voltages Vdata applied to the first pixels R 21 to the sixth pixel B 26 connected to the second gate line are all different in polarities, that is, (−). , (+), (-), (+), (-), (+) Has the polarity.

In the next frame, that is, the N + 1 frame, the plurality of pixels R 11 , G 12 , B 13 , R 14 , G 15 , and B 16 connected to the first gate line are connected to the second gate line. The polarities of the plurality of pixels R 21 , G 22 , B 23 , R 24 , G 25 , B 26 are all inverted to the opposite polarities of the previous polarities.

As described above, in the dot inversion scheme, since the polarity of the voltage applied to the pixel for each frame is inverted at the same time for each column and line, the driving voltage is increased, thereby increasing power consumption.

The line inversion scheme has a problem in that flicker, such as a stripe pattern, occurs between horizontal lines as crosstalk exists between pixels in a horizontal direction.

In addition, the column inversion scheme has a problem in that flicker such as a stripe pattern occurs between vertical lines as crosstalk exists between pixels in the vertical direction.

In addition, the frame inversion method has an advantage of being driven at a lower power consumption than other inversion driving methods, but has a problem in that flicker is generated on a frame basis.

The present invention is to solve the above problems, and to provide a liquid crystal display device that can improve the flicker phenomenon and the horizontal crosstalk phenomenon.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above objects, a liquid crystal display according to an embodiment of the present invention, a plurality of gate lines formed on an insulating substrate, a plurality of data lines formed to cross each other and the plurality of gate lines, the plurality of gates A plurality of pixels formed in an area where lines and the plurality of data lines intersect, a plurality of common electrode lines formed between the plurality of gate lines, and the plurality of gate lines and the plurality of data lines, and the plurality of pixels And a plurality of thin film transistors connected to each other, a voltage having a polarity opposite to a voltage applied to an odd-numbered data line is applied to an even-numbered data line, and an even-numbered one of the plurality of common electrode lines. Opposite of the voltage applied to the odd-numbered common electrode line on the common electrode line The voltage having the property is applied.

Voltages applied to the odd-numbered and even-numbered data lines are inverted every frame, and voltages applied to the odd-numbered and even-numbered common electrode lines are inverted from frame to frame.

The pixels invert the data voltages alternately with respect to the vertical direction, and the pixels arranged in the horizontal direction all have data voltages of the same polarity.

Voltages applied to the odd-numbered data lines and the even-numbered common electrode lines are positive voltages, and voltages applied to the even-numbered data lines and the odd-numbered common electrode lines are negative voltages.

The odd-numbered pixels and the even-numbered pixels of the previous stage are connected to the corresponding gate lines.

In addition, a liquid crystal display according to another exemplary embodiment of the present invention may include a plurality of gate lines formed on an insulating substrate, a plurality of data lines formed to cross the plurality of gate lines, and the plurality of gate lines and the plurality of data. A plurality of pixels formed in an area where lines cross each other, a plurality of common electrode lines formed between the plurality of gate lines, a plurality of pixels connected to the plurality of gate lines and the plurality of data lines, and connected to the plurality of pixels And a thin film transistor, wherein a voltage having a polarity opposite to a voltage applied to the odd-numbered data line is applied to an even-numbered data line of the plurality of data lines, and an upper portion of the odd-numbered gate lines of the plurality of common electrode lines. And a voltage having the same polarity is applied to the common electrode line disposed below. Voltages of different polarities are applied to the common electrode lines disposed above and below the even-numbered gate lines.

Voltages applied to the odd-numbered and even-numbered data lines are inverted every frame, and voltages applied to the odd-numbered and even-numbered common electrode lines are inverted from frame to frame.

The pixels arranged in the vertical direction are inverted in data voltage every two pixels, and the pixels arranged in the horizontal direction all have data voltages of the same polarity.

Positive voltages are provided to the common electrode lines disposed above and below the odd-numbered data lines and the odd-numbered gate lines, and negative voltages to the even-numbered data lines.

When a positive voltage is applied to the common electrode lines disposed above the even-numbered gate lines, a negative voltage is applied to the common electrode lines disposed below the even gate lines.

When a negative voltage is applied to the common electrode line disposed above the even-numbered gate lines, a positive voltage is applied to the common electrode line disposed below the even gate line.

The odd-numbered pixels and the even-numbered pixels of the previous stage are connected to the corresponding gate lines.

As described above, the liquid crystal display according to the present invention provides an effect of improving the flicker phenomenon and the horizontal crosstalk phenomenon.

1A and 1B illustrate a conventional dot inversion scheme.
2A is a diagram showing a voltage applied to a pixel in an N frame.
2B illustrates a voltage applied to a pixel in an N + 1 frame.
3 is a plan view illustrating an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.
4 is a diagram illustrating a voltage applied to a data line according to an embodiment of the present invention.
5 is a diagram illustrating a voltage applied to a common electrode line according to an exemplary embodiment of the present invention.
6 is a diagram illustrating polarities of voltages applied to pixels according to an exemplary embodiment of the present invention.
7 is a plan view illustrating an array substrate of a liquid crystal display according to another exemplary embodiment of the present invention.
8 is a diagram illustrating polarities of voltages applied to pixels according to another exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 4 is a diagram illustrating a voltage applied to a data line according to an exemplary embodiment of the present invention, and FIG. 6 is a diagram illustrating a voltage applied to a common electrode line, and FIG. 6 is a diagram illustrating a polarity of a voltage applied to a pixel according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a plurality of gate lines G11 to G15 and a plurality of data lines D11 to D15 intersect on the array substrate 100 of the liquid crystal display 100 according to the exemplary embodiment of the present invention. It is.

In this case, the plurality of data lines D11 to D15 are divided into odd-numbered data lines D11, D13, and D15 and even-numbered data lines D12 and D14.

As in 'A' of FIG. 4, for example, a positive voltage (+) may be applied to odd-numbered data lines D11, D13, and D15 in an N frame, and also as in 'B' of FIG. 4. The negative voltage (−) may be applied to the even-numbered data lines D12 and D14.

In the N + 1 frame, a negative voltage (−) may be applied to odd-numbered data lines D11, D13, and D15 as opposed to an N frame, and a positive voltage (−) may be applied to even-numbered data lines D12 and D14. +) Can be applied.

Here, a plurality of pixels PX is formed in an area where the plurality of gate lines G11 to G15 and the plurality of data lines D11 to D15 cross each other. In this case, odd-numbered pixels and even-numbered pixels of the previous stage are connected to the corresponding gate lines G11 to G15.

Here, the plurality of pixels PX includes thin film transistors T11 to T30 connected to corresponding gate lines and data lines, and capacitors C11 to C30 connected thereto. Although not shown in the drawings, a capacitor (not shown) includes a liquid crystal capacitor (Clc) and a storage capacitor (Cst).

 Also, common electrode lines Vcom11 to Vcom14 are formed between the gate lines G11 to G15. In this case, the common electrode lines Vcom11 to Vcom14 are divided into odd-numbered common electrode lines Vcom11 and Vcom13 and even-numbered common electrode lines Vcom12 and Vcom14.

As shown in 'C' of FIG. 5, for example, a negative voltage (−) may be applied to the odd-numbered common electrode lines Vcom11 and Vcom13 in the N frame, and also in 'D' of FIG. 5. As described above, for example, a positive voltage (+) may be applied to the even-numbered common electrode lines Vcom12 and Vcom14.

In the N + 1 frame, the positive voltage (+) may be applied to the odd-numbered common electrode lines Vcom11 and Vcom13 as opposed to the N frame, and the negative voltage (the negative voltage) may be applied to the even-numbered common electrode lines Vcom12 and Vcom14. -) Can be applied.

In an exemplary embodiment, odd-numbered thin film transistors T11, T13, and T15 are connected to the first gate line G11 in the horizontal direction. In this case, the source electrodes (not shown) of the odd-numbered thin film transistors T11, T13, and T15 are electrically connected to the odd-numbered data lines D11, D13, and D15.

Here, the odd-numbered and even-numbered thin film transistors are connected to the remaining gate lines G12 to G15 except for the first gate line G11.

When a predetermined gate signal is applied to the first gate line G11, the odd-numbered thin film transistors T11, T13, and T15 connected to the first gate line G11 are all turned on, and thus the thin film transistor is turned on. Data voltages applied to odd-numbered data lines D11, D13, and D15 are applied through the source electrodes of T11, T13, and T15, respectively. For example, assuming that the data voltage applied to the odd-numbered data lines D11, D13, and D15 is a positive voltage (+), the positive voltage (+) is applied to the source electrode of the thin film transistors T11, T13, and T15. Is applied.

When a predetermined gate signal is applied to the second gate line G12, all of the thin film transistors T12, T14, T16, T18, and T20 connected to the second gate line G12 are turned on. The even-numbered thin film transistors T12 and T14 are connected to odd-numbered data lines D11 and D13, and the odd-numbered thin film transistors T16, T18 and T20 are connected to even-numbered data lines D12 and D14. have.

Therefore, voltages applied to the odd-numbered data lines D11 and D13 are applied through the source electrodes of the even-numbered thin film transistors T12 and T14, and through the source electrodes of the odd-numbered thin film transistors T16, T18 and T20. Voltages applied to even-numbered data lines D12 and D14 are respectively applied. For example, assuming that the data voltage applied to the odd-numbered data lines D11 and D13 is a positive voltage (+), the positive voltage (+) is applied to the source electrodes of the even-numbered thin film transistors T12 and T14. If the data voltage applied to the even-numbered data lines D12 and D14 is a negative voltage (-), the negative voltage (-) is applied to the source electrode of the odd-numbered thin film transistors T16, T18, and T20. Is applied.

In addition, when a predetermined gate signal is applied to the third gate line G13, all of the thin film transistors T17, T19, T21, T23, and T25 connected to the third gate line G13 are turned on. Here, even-numbered thin film transistors T17 and T19 are connected to even-numbered data lines D12 and D14, and odd-numbered thin film transistors T21, T23 and T25 are connected to odd-numbered data lines D11, D13, and D15. It is connected.

Accordingly, voltages applied to the even-numbered data lines D12 and D14 are applied through the source electrodes of the even-numbered thin film transistors T17 and T19, and through the source electrodes of the odd-numbered thin film transistors T21, T23 and T25, respectively. Voltages applied to the odd-numbered data lines D11, D13, and D15 are respectively applied. For example, assuming that the data voltage applied to the even-numbered data lines D12 and D14 is a negative voltage (−), the negative voltage (−) is applied to the source electrode of the even-numbered thin film transistors T17 and T19. Is applied and the data voltages applied to the odd-numbered data lines D11, D13, and D15 are positive voltages (+), the positive voltages are applied to the source electrodes of the odd-numbered thin film transistors T21, T23, and T25. +) Is applied.

In an exemplary embodiment of the present invention, as shown in FIG. 6, the pixels Px arranged in the horizontal direction all have data voltages having the same polarity, so that when driven at 60 Hz by the same driving as the line inversion, the pixels Px are displayed on the screen. This can prevent flickering of images.

In addition, in one embodiment of the present invention, the data voltage applied to the data lines D11 to D15 is inverted for each frame. That is, the data lines D11 to D15 are divided into odd-numbered data lines D11, D13, and D15 and even-numbered data lines D12 and D14, so that voltages applied to the data lines in the same frame are converted into positive and negative voltages. Apply separately. For example, as shown in FIG. 4, a positive voltage (+) is applied to odd-numbered data lines D11, D13, and D15 in an N frame, and a negative voltage is applied to odd-numbered common electrode lines Vcom11 and Vcom13. By applying (−), the polarities of the data line and the common electrode line cancel each other, thereby preventing a coupling phenomenon occurring between the data line and the common electrode line. Accordingly, the horizontal crosstalk phenomenon can be prevented by preventing the voltage distortion of the common electrode.

7 is a plan view illustrating an array substrate of a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. 8 is a diagram illustrating polarities of voltages applied to pixels according to another exemplary embodiment of the present invention.

Referring to FIG. 7, the liquid crystal display 200 according to another exemplary embodiment has the same structure as in the exemplary embodiment of the present invention except for voltages applied to the common electrode lines Vcom21 to Vcom25. Here, when the negative voltage (−) is applied to the first common electrode line Vcom21 in the N frame, the positive voltage (+) is applied to the second and third common electrode lines Vcom22 and Vcom23, and A negative voltage (−) may be applied to the fourth and fifth common electrode lines Vcom24 and Vcom25.

In addition, when the positive voltage (+) is applied to the first common electrode line Vcom21 at N + 1, the negative voltage (−) is applied to the second and third common electrode lines Vcom22 and Vcom23. The positive voltage may be applied to the fourth and fifth common electrode lines Vcom24 and Vcom25.

The plurality of data lines D21 to D25 are divided into odd-numbered data lines D21, D23, and D25 and even-numbered data lines D22 and D24.

As in 'A' of FIG. 4, for example, a positive voltage (+) may be applied to odd-numbered data lines D21, D23, and D25 in an N frame, and also, as in 'B' of FIG. 4. Likewise, a negative voltage (−) may be applied to even-numbered data lines D22 and D24.

In the N + 1 frame, a negative voltage (−) may be applied to odd-numbered data lines D21, D23, and D25 as opposed to an N frame, and a positive voltage (−) may be applied to even-numbered data lines D22 and D24. +) Can be applied.

When a predetermined gate signal is applied to the first gate line G21, all of the odd-numbered thin film transistors T31, T33, and T35 connected to the first gate line G21 are turned on. Accordingly, the thin film transistor is turned on. Data voltages applied to odd-numbered data lines D31, D33, and D35 are respectively applied through the source electrodes of T31, T33, and T35. For example, assuming that the data voltage applied to the odd-numbered data lines D31, D33, and D35 is the positive voltage (+), the positive voltage (+) is applied to the source electrode of the thin film transistors T31, T33, and T35. Is applied. In this case, a negative voltage (−) may be applied to the first common electrode line Vcom21.

In addition, when a predetermined gate signal is applied to the second gate line G22, all of the thin film transistors T32, T34, T36, T38, and T40 connected to the second gate line G22 are turned on. The even-numbered thin film transistors T32 and T34 are connected to odd-numbered data lines D21 and D23, and the odd-numbered thin film transistors T36, T38 and T40 are connected to even-numbered data lines D22 and D24. have.

Accordingly, voltages applied to the odd-numbered data lines D21 and D23 are applied through the source electrodes of the even-numbered thin film transistors T32 and T34, respectively, and through the source electrodes of the odd-numbered thin film transistors T36, T38 and T40. Voltages applied to even-numbered data lines D22 and D24 are respectively applied. For example, assuming that the data voltage applied to the odd-numbered data lines D21 and D23 is a positive voltage (+), the positive voltage (+) is applied to the source electrodes of the even-numbered thin film transistors T32 and T34. If the data voltage applied to the even-numbered data lines D12 and D14 is a negative voltage (-), the negative voltage (-) is applied to the source electrode of the odd-numbered thin film transistors T16, T18, and T20. Is applied. In this case, a positive voltage (+) may be applied to the second common electrode line Vcom22.

In addition, when a predetermined gate signal is applied to the third gate line G23, all of the thin film transistors T37, T39, T41, T43, and T45 connected to the third gate line G23 are turned on. The even-numbered thin film transistors T37 and T39 are connected to the even-numbered data lines D22 and D24, and the odd-numbered thin film transistors T41, T43 and T45 are connected to the odd-numbered data lines D21, D23, and D25. It is connected.

Accordingly, voltages applied to the even-numbered data lines D22 and D24 are applied through the source electrodes of the even-numbered thin film transistors T37 and T39, and through the source electrodes of the odd-numbered thin film transistors T41, T43 and T45. Voltages applied to the odd-numbered data lines D21, D23, and D25 are respectively applied. For example, assuming that the data voltage applied to the even-numbered data lines D22 and D24 is the negative voltage (−), the negative voltage (−) is applied to the source electrode of the even-numbered thin film transistors T37 and T39. Is applied and the data voltage applied to the odd-numbered data lines D21, D23, and D25 is a positive voltage (+), the positive voltage (a) is applied to the source electrode of the odd-numbered thin film transistors T41, T43, and T45. +) Is applied. In this case, a positive voltage (+) may be applied to the third common electrode line Vcom23.

In another embodiment of the present invention, as shown in FIG. 8, since the pixels Px arranged in the horizontal direction all have data voltages having the same polarity, flicker phenomenon in which an image appears on the screen flickers by driving the same as line inversion. Can be prevented and the opening ratio can be prevented from being lowered.

In another exemplary embodiment of the present invention, as shown in FIG. 8, the pixels PX arranged in the vertical direction are inversion driven every two lines, thereby canceling the polarity of the data line and the common electrode line. Coupling between lines can be prevented. Accordingly, the horizontal crosstalk phenomenon can be prevented by preventing the voltage distortion of the common electrode.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

100, 200: array substrates G11 to G15: gate lines
D11 to D15: data lines T11 to T30: thin film transistors
Vcom11 to Vcom14: common electrode line
PX: Pixel

Claims (18)

A plurality of gate lines formed on the insulating substrate;
A plurality of data lines formed to intersect with the plurality of gate lines;
A plurality of pixels formed in an area where the plurality of gate lines and the plurality of data lines cross each other;
A plurality of common electrode lines formed between the plurality of gate lines; And
A plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines and connected to the plurality of pixels,
A voltage having a polarity opposite to a voltage applied to an odd data line is applied to an even data line among the plurality of data lines,
And a voltage having a polarity opposite to a voltage applied to an odd-numbered common electrode line is applied to an even-numbered common electrode line among the plurality of common electrode lines. The method of claim 1,
The voltage applied to the odd and even data lines is inverted for each frame. The method of claim 1,
The voltage applied to the odd and even common electrode lines is inverted for each frame. The method of claim 1,
And the pixels invert the data voltages alternately with respect to the vertical direction. The method of claim 1,
And the pixels arranged in the horizontal direction have data voltages of the same polarity. The method of claim 1,
The voltage applied to the odd-numbered data line and the even-numbered common electrode line is a positive voltage. The method of claim 1,
The voltage applied to the even-numbered data line and the odd-numbered common electrode line is a negative voltage. The method of claim 1,
And the odd-numbered pixels and the even-numbered pixels of the previous stage are connected to the corresponding gate lines. A plurality of gate lines formed on the insulating substrate;
A plurality of data lines formed to intersect with the plurality of gate lines;
A plurality of pixels formed in an area where the plurality of gate lines and the plurality of data lines cross each other;
A plurality of common electrode lines formed between the plurality of gate lines; And
A plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines and connected to the plurality of pixels,
A voltage having a polarity opposite to that of the voltage applied to the odd data line is applied to the even data line among the plurality of data lines,
Voltages having the same polarity are applied to common electrode lines disposed above and below the odd-numbered gate lines among the plurality of common electrode lines, and different polarities are applied to common electrode lines disposed above and below the even-numbered gate lines. LCD is characterized in that the voltage is applied. 10. The method of claim 9,
The voltage applied to the odd and even data lines is inverted for each frame. 10. The method of claim 9,
The voltage applied to the odd and even common electrode lines is inverted for each frame. 10. The method of claim 9,
And the data voltages of the pixels arranged in the vertical direction are inverted every two pixels. 10. The method of claim 9,
And the pixels arranged in the horizontal direction have data voltages of the same polarity. 10. The method of claim 9,
And a common voltage on the common electrode lines disposed above and below the odd-numbered data lines and the odd-numbered gate lines. 10. The method of claim 9,
The even-numbered data line has a negative voltage. 10. The method of claim 9,
And when a positive voltage is applied to the common electrode lines disposed above the even-numbered gate lines, a negative voltage is applied to the common electrode line disposed below the even gate lines. 10. The method of claim 9,
And when a negative voltage is applied to the common electrode lines disposed above the even-numbered gate lines, a positive voltage is applied to the common electrode line disposed below the even gate lines. 10. The method of claim 9,
And the odd-numbered pixels and the even-numbered pixels of the previous stage are connected to the corresponding gate lines.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104200786A (en) * 2014-07-31 2014-12-10 京东方科技集团股份有限公司 Array substrate, and drive method, display panel and display device thereof
US9064467B2 (en) 2012-10-29 2015-06-23 Samsung Display Co., Ltd. Liquid crystal display device and driving method thereof
CN105511184A (en) * 2016-01-13 2016-04-20 深圳市华星光电技术有限公司 Liquid crystal display panel and driving method thereof
CN112433413A (en) * 2020-11-26 2021-03-02 深圳市华星光电半导体显示技术有限公司 Liquid crystal display and crosstalk elimination method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064467B2 (en) 2012-10-29 2015-06-23 Samsung Display Co., Ltd. Liquid crystal display device and driving method thereof
CN104200786A (en) * 2014-07-31 2014-12-10 京东方科技集团股份有限公司 Array substrate, and drive method, display panel and display device thereof
US9640126B2 (en) 2014-07-31 2017-05-02 Boe Technology Group Co., Ltd. Array substrate, driving method thereof and display panel
CN105511184A (en) * 2016-01-13 2016-04-20 深圳市华星光电技术有限公司 Liquid crystal display panel and driving method thereof
CN105511184B (en) * 2016-01-13 2019-04-02 深圳市华星光电技术有限公司 Liquid crystal display panel and its driving method
CN112433413A (en) * 2020-11-26 2021-03-02 深圳市华星光电半导体显示技术有限公司 Liquid crystal display and crosstalk elimination method thereof

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