KR20120077275A - Semiconductor memory device and method of operating the same - Google Patents

Semiconductor memory device and method of operating the same Download PDF

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Publication number
KR20120077275A
KR20120077275A KR1020100139175A KR20100139175A KR20120077275A KR 20120077275 A KR20120077275 A KR 20120077275A KR 1020100139175 A KR1020100139175 A KR 1020100139175A KR 20100139175 A KR20100139175 A KR 20100139175A KR 20120077275 A KR20120077275 A KR 20120077275A
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South Korea
Prior art keywords
data input
planes
plane
data
test
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KR1020100139175A
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Korean (ko)
Inventor
강원경
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에스케이하이닉스 주식회사
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Priority to KR1020100139175A priority Critical patent/KR20120077275A/en
Publication of KR20120077275A publication Critical patent/KR20120077275A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

In a semiconductor memory device according to an embodiment of the present invention,
A plurality of planes each including memory cells for data storage and page buffers for temporarily storing data to be programmed into the memory cells; And a control logic for controlling the same test data to be simultaneously input by connecting the page buffers of the plurality of planes and the data input / output lines such that data input for a test is simultaneously input to page buffers of the plurality of planes. do.

Description

Semiconductor memory device and method of operation

The present invention relates to a semiconductor memory device and a method of operating the same.

Recently, there is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function that requires rewriting of data at regular intervals.

In order to further improve the integration degree of a semiconductor memory device, a multi-level cell (MLC) capable of programming the threshold voltage level of one memory cell to various levels has been developed. In contrast, a memory cell is referred to as a single level cell (SLC).

Accordingly, in the case of a multi-level cell, a plurality of pages are logically included in one physical page. For example, in the case of a 2-bit multi-level cell, one physical page may be divided into a logical page of a least significant bit (LSB) page and a most significant bit (MSB) page. The program operation and the data read operation are performed in units of logical pages.

In addition, semiconductor memory devices may be classified into a single-plane type and a multi-plane type according to the structure of the memory cell array.

The single-plane type includes only one plane composed of a plurality of memory cell blocks, and the multi-plane type includes a plurality of planes each composed of a plurality of memory cell blocks.

In the multi-plane type semiconductor memory device, a multi-program and a multi-read operation may be performed to simultaneously select a memory block of each of a plurality of planes to perform a program or data read. As a result, a semiconductor device of a multi-plane type may have an increased data throughput compared to a single plane type that can only program a page of one memory block.

The present invention provides a semiconductor memory device capable of inputting test data to multiple planes at the same time when performing a test of a semiconductor memory device having multiple planes and a method of operating the same.

In a semiconductor memory device according to an embodiment of the present invention,

A plurality of planes each including memory cells for data storage and page buffers for temporarily storing data to be programmed into the memory cells; And a control logic for controlling the same test data to be simultaneously input by connecting the page buffers of the plurality of planes and the data input / output lines such that data input for a test is simultaneously input to page buffers of the plurality of planes. do.

In another embodiment, a method of operating a semiconductor memory device is provided.

Enabling a test data input signal in a test mode of operation; Simultaneously connecting page buffers connected to a plurality of planes to a data input / output line in response to the test data input signal; And simultaneously inputting test data input through the data input / output line to page buffers connected to the plurality of planes.

The semiconductor memory device and the method of operating the same according to an exemplary embodiment of the present invention can input test data to multiple planes at the same time when performing a test on multiple planes, thereby reducing data input time for a test.

1 shows a semiconductor memory device.
2 shows a control logic for outputting a control signal for selecting a plane for data input.
3 illustrates a data input / output circuit for connecting the first and second page buffer groups with a global word line.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 shows a semiconductor memory device.

Referring to FIG. 1, the semiconductor memory device 100 includes first and second planes P0 (110, P1; 120), a peripheral circuit 130, and a control logic 140.

And a pad 150 for transmitting and receiving data with the outside.

The first and second planes 110 and 120 may include first and second memory cell arrays 111 and 121 and first and second page buffer groups 112 and 122, respectively.

The first and second memory cell arrays 111 and 121 include a plurality of memory cells. The memory cells are connected to word lines and bit lines.

The first and second page buffer groups 112 and 122 include page buffers connected to one or more bit lines. The page buffers temporarily store data to be programmed in the selected memory cell, or read and store data programmed in the selected memory cell.

The peripheral circuit 130 may include circuits for selecting, programming, or erasing the pages of the first to second planes 110 and 120, respectively or simultaneously.

The peripheral circuit 130 includes a data input / output circuit 131, and the data input / output circuit 131 is disposed between the first and second page buffer groups 112 and 122 and a global data line (GDL). And a global data line to the first and second data lines GDL_P0 and GDL_P1 in response to the first and second page buffer group selection signals SEL_P0 and SEL_P1 output from the control logic 140.

The first and second data lines GDL_P0 and GDL_P1 are connected to page buffer groups 112 and 122, respectively.

The control logic 140 operates the first and second planes 110 and 120 and the peripheral circuit 130 according to a command and an address AX inputted through the data input / output circuit 131 of the peripheral circuit 130. To control.

Of the control signals output from the control logic 140, control signals related to the operation of the page buffer are commonly input to the first and second page buffer groups 112 and 122.

Therefore, when performing data input / output, the first and second page buffer group selection signals SEL_P0 and SEL_P1 are required to control the connection of the global data line GDL and the first and second page buffer groups 112 and 122.

In addition, the control logic 140 inputs the first or second page buffer group selection signals SEL_P0 and SEL_P1 to the data input / output circuit 131 according to the input address. When the control logic 140 operates in the test mode, the control logic 140 may apply the first or second page buffer group selection signals SEL_P0 and SEL_P1 to simultaneously input test data to the first and second planes 110 and 120. Enable at the same time.

2 shows a control logic for outputting a control signal for selecting a plane for data input.

Referring to FIG. 2, the control logic 140 includes a controller 141, a plane selector 142, and a MUX 144.

The controller 141 outputs control signals for controlling the operation of the first and second planes 110 and 120 and the peripheral circuit 130. Operation control signals are input to the MUX 144.

The controller 141 outputs the cache program control signal Cashepgm for the cache program operation or when the test data is simultaneously input to the first and second planes 110 and 120 when the test operation is performed. Outputs the multi-plane data input signal MP_DATAIN.

The plane selector 142 includes a plane select logic 143 and first and second OR gates OR1 and OR2.

The plane selection logic 143 outputs the first and second plane selection signals Planesel_P0 and Planesel_P1 according to the address AX. During execution of the cache program, the first and second plane selection signals Planesel_P0 and Planesel_P1 are output in accordance with the address AX and the cache program control signal Cachepgm.

The first and second plane selection signals Planesel_P0 and Planesel_P1 are also input to the MUX 144.

The MUX 144 transfers the control signals output from the controller 144 to the first or second planes 110 and 120 by the first and second plane selection signals Planesel_P0 and Planesel_P1.

Data paths of the first and second OR gates OR1 and OR2 to the first and second page buffer groups 112 and 122 are performed using the first and second plane selection signals Planesel_P0 and Planesel_P1. The first and second page buffer group selection signals SEL_P0 and SEL_P1 for selection are output.

That is, the first OR gate OR1 combines the multi-plane data input signal MP_DATAIN and the first plane selection signal Planesel_P0. The output of the first OR gate OR1 is the first page buffer group selection signal SEL_P0.

The second OR gate OR2 combines the multi-plane data input signal MP_DATAIN and the second plane selection signal Planesel_P1. The output of the second OR gate OR2 is the second page buffer group selection signal SEL_P1.

The multi-plane data input signal MP_DATAIN is enabled at a high level only during a test operation, and is maintained at a low level during other operations.

That is, in the normal operation mode other than the test operation, the first and second page buffer group selection signals SEL_P0 and SEL_P1 are determined according to the first and second plane selection signals Planesel_P0 and Planesel_P1.

During the test operation, both the first and second page buffer group selection signals SEL_P0 and SEL_P1 are output at a high level regardless of the first and second plane selection signals Planesel_P0 and Planesel_P1.

That is, when the multi-plane data input signal MP_DATAIN becomes high during data input for a test operation, both the first and second page buffer groups 112 and 122 are selected, and thus the global data line GDL. The test data input through the N 1) is simultaneously input to the first and second page buffer groups 112 and 122.

3 illustrates a data input / output circuit for connecting the first and second page buffer groups with a global word line.

3 shows only a circuit connecting the first and second page buffer groups and the global word line.

Referring to FIG. 3, the data input / output circuit 131 includes first and second AND gates AN1 and AN2.

The first AND gate AN1 is connected to the global data line GDL, and transfers the global data line GDL to the first data line GDL_P0 in response to the first page buffer group selection signal SEL_P0.

The second AND gate AN2 is connected to the global data line GDL, and transmits the global data line GDL to the second data line GDL_P1 in response to the second page buffer group selection signal SEL_P1.

In the test operation, when the first and second page buffer group selection signals SEL_P0 and SEL_P1 are simultaneously output at the high level in order to simultaneously input data to the multiplane, the global data line GDL is output. ), Since the first and second data lines GDL_P0 and GDL_P1 are commonly connected, the same data is simultaneously input to the first and second page buffer groups 112 and 122.

Accordingly, when it is necessary to input the same test data to the first page buffer group 112 and the second page buffer group 122 for the test, the test data for the first page buffer group 112 is inputted, and Compared with the conventional method of inputting test data for the two-page buffer group 122, when only one test data is input, the test data is simultaneously input to the first and second page buffer groups 112 and 122, so that data is input. Time is cut in half.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

100: semiconductor memory device 110, 120: first and second plane
111 and 121: first and second memory cell arrays
112, 122: First and second page buffer groups
130: peripheral circuit 131: data input and output circuit
140: control logic

Claims (7)

A plurality of planes each including memory cells for data storage and page buffers for temporarily storing data to be programmed into the memory cells; And
Control logic for controlling the same test data to be simultaneously input by connecting the page buffers of the plurality of planes and the data input / output lines so that data input for the test is simultaneously input to the page buffers of the plurality of planes.
Semiconductor memory device comprising a. The method of claim 1,
The control logic is,
A controller for outputting operation control signals according to an operation mode and a multi-plane data input signal representing a data input for a test;
Plane selection logic to generate at least one plane selection signal in response to the address signal;
A mux for delivering the operation control signal output from the controller to the selected plane according to the at least one plane selection signal,
A page buffer selection circuit for outputting a page buffer selection signal for connecting the page buffers of the selected plane and the data line according to the at least one plane selection signal,
The page buffer selection circuit is a page buffer for all page buffers for connecting the page buffers of all planes to the data input / output lines regardless of the at least one plane selection signal when the multi-plane data input signal is enabled. A semiconductor memory device that enables a selection signal. The method of claim 2,
And a data input / output circuit for connecting the data input / output line with a page buffer of a selected plane in response to the page buffer selection signal. Enabling a test data input signal in a test mode of operation;
Simultaneously connecting page buffers connected to a plurality of planes to a data input / output line in response to the test data input signal; And
Simultaneously inputting test data input through the data input / output line to page buffers connected to the plurality of planes
Method of operating a semiconductor memory device comprising a. The method of claim 4, wherein
After all the test data is input,
And simultaneously performing a test operation on the plurality of planes. The method of claim 4, wherein
When not in the test operation mode, selecting at least one plane from among the plurality of planes according to an input address, and a page buffer of the selected plane is connected to the data input / output line. The method of claim 4, wherein
And when the test data input through the data input / output lines are simultaneously input to page buffers connected to the plurality of planes, the same test data is stored in each page buffer.
KR1020100139175A 2010-12-30 2010-12-30 Semiconductor memory device and method of operating the same KR20120077275A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165672B2 (en) 2012-12-05 2015-10-20 Samsung Electronics Co., Ltd. Nonvolatile memory device comprising page buffer and operation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165672B2 (en) 2012-12-05 2015-10-20 Samsung Electronics Co., Ltd. Nonvolatile memory device comprising page buffer and operation method thereof
US9520201B2 (en) 2012-12-05 2016-12-13 Samsung Electronics Co., Ltd. Nonvolatile memory device comprising page buffer and program verification operation method thereof

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