KR20120068309A - Anti fuse circuit - Google Patents
Anti fuse circuit Download PDFInfo
- Publication number
- KR20120068309A KR20120068309A KR1020100129881A KR20100129881A KR20120068309A KR 20120068309 A KR20120068309 A KR 20120068309A KR 1020100129881 A KR1020100129881 A KR 1020100129881A KR 20100129881 A KR20100129881 A KR 20100129881A KR 20120068309 A KR20120068309 A KR 20120068309A
- Authority
- KR
- South Korea
- Prior art keywords
- fuse
- line
- programming voltage
- voltage generator
- programming
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2229/00—Indexing scheme relating to checking stores for correct operation, subsequent repair or testing stores during standby or offline operation
- G11C2229/70—Indexing scheme relating to G11C29/70, for implementation aspects of redundancy repair
- G11C2229/76—Storage technology used for the repair
- G11C2229/763—E-fuses, e.g. electric fuses or antifuses, floating gate transistors
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- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
TECHNICAL FIELD The present invention relates to semiconductor design techniques, and more particularly, to an antifuse circuit having a plurality of antifuses.
BACKGROUND In general, semiconductor memory devices including DDR SDRAM (Double Data Rate Synchronous DRAM) have various internal circuits to perform various operations, and among the devices constituting such internal circuits, there is an anti-fuse. Anti-fuse is a device having characteristics opposite to that of a general fuse. In the case of a general fuse, the fuse is manufactured in an initial short state and then programmed and opened according to the purpose. Programmed according to the purpose, the device is short-circuited. Here, programming refers to a series of operations to bring general fuses and anti-fuses to a desired state.
On the other hand, these fuses are mainly used in a redundancy circuit. The redundancy circuit is a circuit for increasing the yield of a semiconductor memory device. The redundancy circuit stores an address of a defective memory cell and compares it with an address input during normal operation to determine whether the currently input address accesses the defective memory cell. Indicates whether accessing a normal memory cell. Here, the fuses are used to store the address of the defective memory cell, and a general fuse or an anti-fuse is used depending on the design.
Conventional fuses have the advantage of being designed with a relatively small area, but the disadvantage is that they cannot be programmed for bad memory cells found in the package because they must be programmed in the wafer state. On the other hand, the anti-fuse has the advantage that can be programmed by applying a programming voltage after the package, but has a disadvantage that occupies a relatively large area.
Hereinafter, the anti-fuse will be described in more detail.
An antifuse may consist of a composite with a dielectric sandwiched between two conductors, such as silicon dioxide (SiO2), silicon nitride, tantalum oxide, or silicon dioxide-silicon nitride-silicon dioxide (ONO). Initially, it has very high resistance and very low resistance by the programming operation. The programming operation of the antifuse generally applies a predetermined programming voltage across the antifuse, thereby breaking the dielectric between the conductors of both ends and shorting the conductors of both ends. Therefore, the anti-fuse basically must be provided with a programming voltage generator for selectively applying a programming voltage.
1 is a block diagram for explaining an arrangement of a conventional anti-fuse circuit.
Referring to FIG. 1, the anti-fuse circuit includes a
Accordingly, the first programming voltage generated in the
As shown in FIG. 1, in the conventional anti-fuse circuit, the lengths of the first line L1 and the second line L2 are different from each other. Different lengths of the first line L1 and the second line L2 mean that the loading values reflected on each line are different from each other, which is different from the first and second programming voltages transmitted through each line. It means that skew is reflected. Eventually, this skew is a factor that prevents the anti-fuse from performing the desired programming operation.
An embodiment of the present invention has been proposed to solve the above problems, and to provide a fuse circuit in which the first and second programming voltages applied to the antifuse are transmitted through a line having the same loading value.
An anti-fuse circuit according to an aspect of the present invention for achieving the above object, an anti-fuse; A first programming voltage generator configured to generate a first programming voltage and apply the first programming voltage to a first line connected to one end of the anti-fuse; And a second programming voltage generator configured to generate a second programming voltage and apply the same to a second line connected to the other end of the anti-fuse, having the same loading value as that of the first line.
In particular, the first programming voltage generator and the second programming voltage generator are disposed at one end of an area where the antifuse is disposed.
According to another aspect of the present invention for achieving the above object, an anti-fuse circuit includes an anti-fuse and first and second programming voltage generators for generating first and second programming voltages applied across the anti-fuse. It is provided with a unit anti-fuse unit, characterized in that a plurality of unit anti-fuse is disposed adjacent to each other.
In particular, the anti-fuse and the first and second programming voltage generators are arranged in one predetermined unit region.
Since the anti-fuse circuit according to the embodiment of the present invention is transferred to both ends of the anti-fuse through a line having the first and second programming voltages having the same loading value, the anti-fuse may be guaranteed a stable programming operation. In addition, the arrangement according to the embodiment of the present invention may minimize the length of the line through which the first and second programming voltages are transmitted.
The present invention ensures a stable programming operation of the anti-fuse, thereby increasing the reliability of the programmed anti-fuse.
In addition, the present invention can achieve the effect of minimizing the loading value reflected in each line by minimizing the length of the line to which the programming voltage is transferred.
1 is a block diagram for explaining an arrangement of a conventional anti-fuse circuit.
2 is a block diagram illustrating an antifuse circuit according to an exemplary embodiment of the present invention.
Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
2 is a block diagram illustrating an
Referring to FIG. 2, the
Hereinafter, the first unit
The first unit
As shown in the figure, the first
As described above, the
Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.
210: anti-fuse circuit
211, 212, and 213: first to third unit anti-fuse parts
211A:
211C: second programming voltage generator
L1, L2, L3: first to third lines
Claims (11)
A first programming voltage generator configured to generate a first programming voltage and apply the first programming voltage to a first line connected to one end of the anti-fuse; And
A second programming voltage generator for generating a second programming voltage and applying it to a second line connected to the other end of the anti-fuse, having the same loading value as the first line;
An anti-fuse circuit comprising a.
And a third line transferring a control signal for controlling the first programming voltage generator and the second programming voltage generator.
And the first programming voltage generator and the second programming voltage generator are disposed at one end of a region where the anti-fuse is disposed.
And the first line and the second line are formed on the same metal line layer.
And the first line and the second line have the same length.
And the first to third lines are formed on the same metal line layer.
The anti-fuse circuit, characterized in that a plurality of unit anti-fuse unit is disposed adjacent to each other.
And the anti-fuse and the first and second programming voltage generators are arranged in one predetermined unit area.
The first line connected between the one end of the anti-fuse and the first programming voltage generator and the second line connected between the other end of the anti-fuse and the second programming voltage generator are formed on the same metal line layer. Anti-fuse circuit, characterized in that.
And the first line and the second line have the same loading value.
And the first line and the second line have the same length.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100129881A KR20120068309A (en) | 2010-12-17 | 2010-12-17 | Anti fuse circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100129881A KR20120068309A (en) | 2010-12-17 | 2010-12-17 | Anti fuse circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20120068309A true KR20120068309A (en) | 2012-06-27 |
Family
ID=46687025
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020100129881A KR20120068309A (en) | 2010-12-17 | 2010-12-17 | Anti fuse circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20120068309A (en) |
-
2010
- 2010-12-17 KR KR1020100129881A patent/KR20120068309A/en not_active Application Discontinuation
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