KR20120068309A - Anti fuse circuit - Google Patents

Anti fuse circuit Download PDF

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Publication number
KR20120068309A
KR20120068309A KR1020100129881A KR20100129881A KR20120068309A KR 20120068309 A KR20120068309 A KR 20120068309A KR 1020100129881 A KR1020100129881 A KR 1020100129881A KR 20100129881 A KR20100129881 A KR 20100129881A KR 20120068309 A KR20120068309 A KR 20120068309A
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KR
South Korea
Prior art keywords
fuse
line
programming voltage
voltage generator
programming
Prior art date
Application number
KR1020100129881A
Other languages
Korean (ko)
Inventor
김경희
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100129881A priority Critical patent/KR20120068309A/en
Publication of KR20120068309A publication Critical patent/KR20120068309A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2229/00—Indexing scheme relating to checking stores for correct operation, subsequent repair or testing stores during standby or offline operation
    • G11C2229/70—Indexing scheme relating to G11C29/70, for implementation aspects of redundancy repair
    • G11C2229/76—Storage technology used for the repair
    • G11C2229/763—E-fuses, e.g. electric fuses or antifuses, floating gate transistors

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: An anti-fuse circuit is provided to minimize a loading value reflected in each line by minimizing the length of a line to which a programming voltage is transmitted. CONSTITUTION: A first programming voltage generating unit(211B) generates a first programming voltage and applies the first programming voltage to a first line connected to one side of an anti-fuse. A second programming voltage generating unit(211C) generates a second programming voltage and applies the second programming voltage to the second line connected to other side of the anti-fuse. The second line has the same loading value as the first line.

Description

ANTI FUSE CIRCUIT {ANTI FUSE CIRCUIT}

TECHNICAL FIELD The present invention relates to semiconductor design techniques, and more particularly, to an antifuse circuit having a plurality of antifuses.

BACKGROUND In general, semiconductor memory devices including DDR SDRAM (Double Data Rate Synchronous DRAM) have various internal circuits to perform various operations, and among the devices constituting such internal circuits, there is an anti-fuse. Anti-fuse is a device having characteristics opposite to that of a general fuse. In the case of a general fuse, the fuse is manufactured in an initial short state and then programmed and opened according to the purpose. Programmed according to the purpose, the device is short-circuited. Here, programming refers to a series of operations to bring general fuses and anti-fuses to a desired state.

On the other hand, these fuses are mainly used in a redundancy circuit. The redundancy circuit is a circuit for increasing the yield of a semiconductor memory device. The redundancy circuit stores an address of a defective memory cell and compares it with an address input during normal operation to determine whether the currently input address accesses the defective memory cell. Indicates whether accessing a normal memory cell. Here, the fuses are used to store the address of the defective memory cell, and a general fuse or an anti-fuse is used depending on the design.

Conventional fuses have the advantage of being designed with a relatively small area, but the disadvantage is that they cannot be programmed for bad memory cells found in the package because they must be programmed in the wafer state. On the other hand, the anti-fuse has the advantage that can be programmed by applying a programming voltage after the package, but has a disadvantage that occupies a relatively large area.

Hereinafter, the anti-fuse will be described in more detail.

An antifuse may consist of a composite with a dielectric sandwiched between two conductors, such as silicon dioxide (SiO2), silicon nitride, tantalum oxide, or silicon dioxide-silicon nitride-silicon dioxide (ONO). Initially, it has very high resistance and very low resistance by the programming operation. The programming operation of the antifuse generally applies a predetermined programming voltage across the antifuse, thereby breaking the dielectric between the conductors of both ends and shorting the conductors of both ends. Therefore, the anti-fuse basically must be provided with a programming voltage generator for selectively applying a programming voltage.

1 is a block diagram for explaining an arrangement of a conventional anti-fuse circuit.

Referring to FIG. 1, the anti-fuse circuit includes a first region 110 in which a plurality of anti-fuses are disposed, a second voltage in which a programming voltage generator for selectively applying a programming voltage across each of the plurality of anti-fuses is disposed; Third regions 120 and 130 are provided. Here, the second region 120 has a first programming voltage generator for selectively applying a first programming voltage to one end of each antifuse, and the third region 130 is located at the other end of each of the antifuses. A second programming voltage generator is disposed for selectively applying the second programming voltage.

Accordingly, the first programming voltage generated in the second region 120 is transferred to the first region 110 through the first line L1, and the second programming voltage generated in the third region 130 is second. It is transmitted to the first region 110 through the line (L2). Subsequently, the second region 120 and the third region 130 receive a control signal through the third line L3.

As shown in FIG. 1, in the conventional anti-fuse circuit, the lengths of the first line L1 and the second line L2 are different from each other. Different lengths of the first line L1 and the second line L2 mean that the loading values reflected on each line are different from each other, which is different from the first and second programming voltages transmitted through each line. It means that skew is reflected. Eventually, this skew is a factor that prevents the anti-fuse from performing the desired programming operation.

An embodiment of the present invention has been proposed to solve the above problems, and to provide a fuse circuit in which the first and second programming voltages applied to the antifuse are transmitted through a line having the same loading value.

An anti-fuse circuit according to an aspect of the present invention for achieving the above object, an anti-fuse; A first programming voltage generator configured to generate a first programming voltage and apply the first programming voltage to a first line connected to one end of the anti-fuse; And a second programming voltage generator configured to generate a second programming voltage and apply the same to a second line connected to the other end of the anti-fuse, having the same loading value as that of the first line.

In particular, the first programming voltage generator and the second programming voltage generator are disposed at one end of an area where the antifuse is disposed.

According to another aspect of the present invention for achieving the above object, an anti-fuse circuit includes an anti-fuse and first and second programming voltage generators for generating first and second programming voltages applied across the anti-fuse. It is provided with a unit anti-fuse unit, characterized in that a plurality of unit anti-fuse is disposed adjacent to each other.

In particular, the anti-fuse and the first and second programming voltage generators are arranged in one predetermined unit region.

Since the anti-fuse circuit according to the embodiment of the present invention is transferred to both ends of the anti-fuse through a line having the first and second programming voltages having the same loading value, the anti-fuse may be guaranteed a stable programming operation. In addition, the arrangement according to the embodiment of the present invention may minimize the length of the line through which the first and second programming voltages are transmitted.

The present invention ensures a stable programming operation of the anti-fuse, thereby increasing the reliability of the programmed anti-fuse.

In addition, the present invention can achieve the effect of minimizing the loading value reflected in each line by minimizing the length of the line to which the programming voltage is transferred.

1 is a block diagram for explaining an arrangement of a conventional anti-fuse circuit.
2 is a block diagram illustrating an antifuse circuit according to an exemplary embodiment of the present invention.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a block diagram illustrating an antifuse circuit 210 according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the antifuse circuit 210 includes a plurality of unit antifuse parts including first to third unit antifuse parts 211, 212, and 213. Here, each of the plurality of unit anti-fuse units has one predetermined unit region, and each unit region is disposed adjacent to each other. For convenience of description, the first to third unit anti-fuse units 211, 212, and 213 of the plurality of unit anti-fuse units are representatively shown in the drawings.

Hereinafter, the first unit anti-fuse unit 211 of the plurality of unit anti-fuse units will be described as a representative.

The first unit anti-fuse unit 211 may include a fuse region 211A in which the anti-fuse is disposed and a first programming voltage to generate a first programming voltage and apply it to a first line L1 connected to one end of the anti-fuse. And a second programming voltage generator 211C for generating a second programming voltage and applying it to the second line L2 connected to the other end of the antifuse. Subsequently, a third line L3 is provided between the first programming voltage generator 211B and the second programming voltage generator 211C to transmit a control signal for controlling the two.

As shown in the figure, the first programming voltage generator 211B and the second programming voltage generator 211C are disposed at one end of the fuse region 211A, in the figure, to the right of the fuse region 211A. Therefore, the first line L1 and the second line L2 can be minimized to the same length, which means that the first line L1 and the second line L2 have the same loading value. Subsequently, since the first programming voltage generator 211B and the second programming voltage generator 211C are disposed adjacent to each other, the length of the third line L3 may also be minimized. In addition, the anti-fuse circuit 210 having such an arrangement structure may form the first to third lines L1, L2, and L3 as the same metal line layer.

As described above, the anti-fuse circuit 210 according to the exemplary embodiment of the present invention designs one unit anti-fuse unit in one predetermined unit area, and a plurality of unit anti-fuse units are disposed adjacent to each other. Accordingly, the lengths of the first and second lines L1 and L2 and the third line L3 to which the first and second programming voltages are transmitted can be minimized. In addition, since the first and second lines L1 and L2 have the same length, that is, the same loading value, the malfunction due to skew does not occur, which may prevent the anti-fuse circuit 210 from ensuring a stable programming operation. It means that there is. In addition, since the first to third lines L1, L2, and L3 are all formed on the same metal line layer, an area used to arrange the lines may be minimized.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

210: anti-fuse circuit
211, 212, and 213: first to third unit anti-fuse parts
211A: fuse area 211B: first programming voltage generator
211C: second programming voltage generator
L1, L2, L3: first to third lines

Claims (11)

Anti-fuse;
A first programming voltage generator configured to generate a first programming voltage and apply the first programming voltage to a first line connected to one end of the anti-fuse; And
A second programming voltage generator for generating a second programming voltage and applying it to a second line connected to the other end of the anti-fuse, having the same loading value as the first line;
An anti-fuse circuit comprising a.
The method of claim 1,
And a third line transferring a control signal for controlling the first programming voltage generator and the second programming voltage generator.
The method of claim 1,
And the first programming voltage generator and the second programming voltage generator are disposed at one end of a region where the anti-fuse is disposed. The method of claim 1,
And the first line and the second line are formed on the same metal line layer.
The method of claim 1,
And the first line and the second line have the same length.
The method of claim 2,
And the first to third lines are formed on the same metal line layer.
A unit anti-fuse unit including an anti-fuse and first and second programming voltage generators for generating first and second programming voltages applied across the anti-fuse,
The anti-fuse circuit, characterized in that a plurality of unit anti-fuse unit is disposed adjacent to each other.
The method of claim 7, wherein
And the anti-fuse and the first and second programming voltage generators are arranged in one predetermined unit area.
The method of claim 7, wherein
The first line connected between the one end of the anti-fuse and the first programming voltage generator and the second line connected between the other end of the anti-fuse and the second programming voltage generator are formed on the same metal line layer. Anti-fuse circuit, characterized in that.
The method of claim 7, wherein
And the first line and the second line have the same loading value.

The method of claim 7, wherein
And the first line and the second line have the same length.
KR1020100129881A 2010-12-17 2010-12-17 Anti fuse circuit KR20120068309A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100129881A KR20120068309A (en) 2010-12-17 2010-12-17 Anti fuse circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100129881A KR20120068309A (en) 2010-12-17 2010-12-17 Anti fuse circuit

Publications (1)

Publication Number Publication Date
KR20120068309A true KR20120068309A (en) 2012-06-27

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KR1020100129881A KR20120068309A (en) 2010-12-17 2010-12-17 Anti fuse circuit

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