KR20120038237A - Antifuse test circuit and semiconductor device including the same - Google Patents
Antifuse test circuit and semiconductor device including the same Download PDFInfo
- Publication number
- KR20120038237A KR20120038237A KR1020100099880A KR20100099880A KR20120038237A KR 20120038237 A KR20120038237 A KR 20120038237A KR 1020100099880 A KR1020100099880 A KR 1020100099880A KR 20100099880 A KR20100099880 A KR 20100099880A KR 20120038237 A KR20120038237 A KR 20120038237A
- Authority
- KR
- South Korea
- Prior art keywords
- fuse
- driving force
- breakdown
- antifuse
- test circuit
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2229/00—Indexing scheme relating to checking stores for correct operation, subsequent repair or testing stores during standby or offline operation
- G11C2229/70—Indexing scheme relating to G11C29/70, for implementation aspects of redundancy repair
- G11C2229/76—Storage technology used for the repair
- G11C2229/763—E-fuses, e.g. electric fuses or antifuses, floating gate transistors
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
An antifuse test circuit is disclosed. The anti-fuse test circuit may include a plurality of driving force adjusting units for adjusting driving force of breakdown voltage, a plurality of reference antifuses to which respective breakdown voltages determined by the plurality of driving force adjusting units, and isolation of the plurality of reference antifuses are applied. It includes a plurality of reference sensing unit for sensing the destruction.
Description
The present invention relates to an anti-fuse test circuit for setting breakdown conditions of an anti-fuse and a semiconductor device including the same.
Antifuse is an electrical device that works in the reverse way of a conventional fuse. That is, the general fuse is changed into a high resistance state by a programming operation such as fuse blowing in the initial low resistance state, while the antifuse is changed into a low resistance state by a programming operation in the high resistance state.
However, in the case of a general fuse, fuse blowing using a laser is possible in a wafer state, but such a laser fuse blowing is impossible in a package state. On the other hand, antifuse has the advantage that the circuit designer can change the desired state by using pins externally even in the package state. In addition, since the fuse is activated or deactivated by the electrical signal, there is an advantage that the size of the fuse circuit can be reduced together with the reduction of the process scale.
Due to these advantages, antifuses are currently used in semiconductor memory or logic devices for repair of defective cells, storage of chip identification, and circuit customization. For example, out of many cells in a memory device, the cells that turn out to be bad can be replaced by redundancy cells by antifuse, which can solve the problem of poor yield due to defects in some cells in a packaged state. have.
Antifuse is programmed by applying a constant voltage and current across the fuse. In general, anti-fuse is implemented by including a capacitor. When a high level of voltage and current is applied at both ends in an initial high resistance state, the dielectric inside the capacitor is damaged, that is, a breakdown is performed so that current flows. .
1 illustrates a portion of a conventional antifuse programming circuit.
Referring to FIG. 1, some of the conventional antifuse programming circuits include a
The dielectric
Conventionally, in order to set an optimal condition for the breakdown of the anti-fuse 113, the clamping PMOS transistor for supplying the external voltage Vpp to the anti-fuse 113 using the test mode in the programming controller 101 ( 107, 109, 111) were performed. That is, first, the voltage and current are supplied to the
However, in the case of using such a conventional test mode, a different clamp PMOS transistor size is required depending on the package due to a change in transistor characteristics due to process variables, etc., thus, it takes a long time to set the breakdown condition of the anti-fuse. There is a problem.
The present invention has been proposed to solve the above problems, and to reduce the test time for setting the dielectric breakdown conditions, to provide an anti-fuse test circuit that can be commonly applied to all the anti-fuse in the semiconductor device and a semiconductor device comprising the same The purpose.
The anti-fuse test circuit according to the present invention for achieving the above object, a plurality of driving force control unit for adjusting the driving force of the breakdown voltage, a plurality of reference anti-receiving each breakdown voltage determined by the plurality of driving force control unit A plurality of reference sensing unit for sensing whether the fuse and the dielectric breakdown of the plurality of reference anti-fuse.
The plurality of driving force adjusting units may each include one or more clamp PMOS transistors of different sizes, and the larger the size of the clamp PMOS transistor, the greater the driving force of the breakdown voltage.
In the semiconductor device according to the present invention, a program for driving the anti-fuse driver by using an anti-fuse driver, an anti-fuse test circuit for determining an insulation breakdown condition applied to the anti-fuse driver, and a test result of the anti-fuse test circuit. It includes a control unit.
The anti-fuse test circuit may include a plurality of driving force adjusting units for adjusting a driving force of breakdown voltages, a plurality of reference antifuses and respective reference antifuses to which respective breakdown voltages driven by the plurality of driving force adjusting units are applied. It may include a plurality of reference sensing unit for sensing whether the breakdown.
The anti-fuse driving unit senses a plurality of insulation breakdown setting units, a plurality of antifuses connected to the plurality of insulation breakdown setting units, and whether each of the plurality of antifuses breaks down the insulation, thereby activating an output signal of the breakdown antifuse. It may include a plurality of anti-fuse sensing unit.
According to the present invention, instead of selecting the size of the clamp PMOS transistor through the test mode, a reference antifuse test circuit in which the clamp PMOS transistors are classified by size is placed inside the semiconductor device, and the test results are used to generate a reference antifuse test circuit. This saves time and increases programming reliability.
In addition, an optimum antifuse dielectric breakdown condition may be set in each semiconductor device by reflecting various transistor characteristics due to process variables of the corresponding package and the like and applied to all antifuses in the semiconductor device.
1 illustrates a portion of a conventional antifuse programming circuit.
2 is a block diagram of a semiconductor device including an antifuse test circuit according to the present invention.
3 is a diagram illustrating an embodiment of the
Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.
2 is a configuration diagram of a semiconductor device including an
Referring to FIG. 2, the semiconductor device according to the present invention includes an
The
Here, the dielectric
In the present exemplary embodiment, three
The
The
A detailed configuration of the
The programming controller 205 optimizes the plurality of
FIG. 3 is a diagram illustrating an embodiment of the
Referring to FIG. 3, the
Each of the driving
The reference antifuses 311, 313, and 315 are the same antifuses commonly used in semiconductor devices, and whether the dielectric breakdown is caused by various breakdown voltages and currents applied through the driving
The test may be performed under such various conditions to find an optimal condition for the dielectric breakdown of the reference antifuse 311, 313, and 315. For example, when the second driving
The
As described above, in the present invention, instead of selecting the size of the clamp PMOS transistor through the test mode, a test circuit including a reference antifuse in which the clamp PMOS transistor is classified by size is placed inside the semiconductor device, and the test result is used. An antifuse test circuit and a semiconductor device including the same have been proposed to reduce the time required in the test mode and increase the reliability of programming.
The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by.
Claims (9)
A plurality of reference antifuses receiving respective breakdown voltages determined by the plurality of driving force adjusting units; And
A plurality of reference sensing unit for sensing the breakdown of the plurality of reference anti-fuse
Anti-fuse test circuit comprising a.
The plurality of driving force adjusting unit
Each containing one or more different size clamp PMOS transistors
Antifuse test circuit.
The larger the clamp PMOS transistor is, the larger the driving force of the breakdown voltage is.
Antifuse test circuit.
An anti-fuse test circuit for determining an insulation breakdown condition applied to the anti-fuse driver; And
A programming controller which drives the anti-fuse driver by using a test result of the anti-fuse test circuit
.
The antifuse test circuit
A plurality of driving force adjusting unit for adjusting the driving force of the breakdown voltage;
A plurality of reference antifuses receiving respective breakdown voltages driven by the plurality of driving force adjusting units; And
It includes a plurality of reference sensing unit for sensing whether the plurality of reference anti-fuse insulation breakdown
Semiconductor device.
The plurality of driving force adjusting unit
Each containing one or more different size clamp PMOS transistors
Semiconductor device.
The larger the clamp PMOS transistor is, the larger the driving force of the breakdown voltage is.
Semiconductor device.
The anti-fuse drive unit
A plurality of breakdown setting units;
A plurality of anti-fuses connected to the plurality of breakdown setting units, respectively; And
It includes a plurality of anti-fuse sensing unit for sensing the insulation breakdown of each of the plurality of anti-fuse to activate the output signal of the insulating anti-fuse
Semiconductor device.
The plurality of breakdown setting unit
Each comprising one or more different sized clamp PMOS transistors,
Driving the plurality of antifuse using some or all of the plurality of clamp PMOS transistors of different sizes with the driving force of the breakdown voltage determined by the antifuse test circuit.
Semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100099880A KR20120038237A (en) | 2010-10-13 | 2010-10-13 | Antifuse test circuit and semiconductor device including the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100099880A KR20120038237A (en) | 2010-10-13 | 2010-10-13 | Antifuse test circuit and semiconductor device including the same |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20120038237A true KR20120038237A (en) | 2012-04-23 |
Family
ID=46139085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020100099880A KR20120038237A (en) | 2010-10-13 | 2010-10-13 | Antifuse test circuit and semiconductor device including the same |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20120038237A (en) |
-
2010
- 2010-10-13 KR KR1020100099880A patent/KR20120038237A/en not_active Application Discontinuation
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