KR20120038237A - Antifuse test circuit and semiconductor device including the same - Google Patents

Antifuse test circuit and semiconductor device including the same Download PDF

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Publication number
KR20120038237A
KR20120038237A KR1020100099880A KR20100099880A KR20120038237A KR 20120038237 A KR20120038237 A KR 20120038237A KR 1020100099880 A KR1020100099880 A KR 1020100099880A KR 20100099880 A KR20100099880 A KR 20100099880A KR 20120038237 A KR20120038237 A KR 20120038237A
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KR
South Korea
Prior art keywords
fuse
driving force
breakdown
antifuse
test circuit
Prior art date
Application number
KR1020100099880A
Other languages
Korean (ko)
Inventor
공용호
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100099880A priority Critical patent/KR20120038237A/en
Publication of KR20120038237A publication Critical patent/KR20120038237A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2229/00—Indexing scheme relating to checking stores for correct operation, subsequent repair or testing stores during standby or offline operation
    • G11C2229/70—Indexing scheme relating to G11C29/70, for implementation aspects of redundancy repair
    • G11C2229/76—Storage technology used for the repair
    • G11C2229/763—E-fuses, e.g. electric fuses or antifuses, floating gate transistors

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

An antifuse test circuit is disclosed. The anti-fuse test circuit may include a plurality of driving force adjusting units for adjusting driving force of breakdown voltage, a plurality of reference antifuses to which respective breakdown voltages determined by the plurality of driving force adjusting units, and isolation of the plurality of reference antifuses are applied. It includes a plurality of reference sensing unit for sensing the destruction.

Description

ANTIFUSE TEST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

The present invention relates to an anti-fuse test circuit for setting breakdown conditions of an anti-fuse and a semiconductor device including the same.

Antifuse is an electrical device that works in the reverse way of a conventional fuse. That is, the general fuse is changed into a high resistance state by a programming operation such as fuse blowing in the initial low resistance state, while the antifuse is changed into a low resistance state by a programming operation in the high resistance state.

However, in the case of a general fuse, fuse blowing using a laser is possible in a wafer state, but such a laser fuse blowing is impossible in a package state. On the other hand, antifuse has the advantage that the circuit designer can change the desired state by using pins externally even in the package state. In addition, since the fuse is activated or deactivated by the electrical signal, there is an advantage that the size of the fuse circuit can be reduced together with the reduction of the process scale.

Due to these advantages, antifuses are currently used in semiconductor memory or logic devices for repair of defective cells, storage of chip identification, and circuit customization. For example, out of many cells in a memory device, the cells that turn out to be bad can be replaced by redundancy cells by antifuse, which can solve the problem of poor yield due to defects in some cells in a packaged state. have.

Antifuse is programmed by applying a constant voltage and current across the fuse. In general, anti-fuse is implemented by including a capacitor. When a high level of voltage and current is applied at both ends in an initial high resistance state, the dielectric inside the capacitor is damaged, that is, a breakdown is performed so that current flows. .

1 illustrates a portion of a conventional antifuse programming circuit.

Referring to FIG. 1, some of the conventional antifuse programming circuits include a programming control unit 101, an insulation breakdown setting unit 105, an antifuse 113, and an antifuse sensing unit 115. Here, the breakdown setting unit 103, the antifuse 111, and the antifuse sensing unit 113 constitute one antifuse block 103, and the entire programming circuit includes a plurality of antifuse blocks of this type. can do.

The dielectric breakdown setting unit 105 may include a plurality of clamp PMOS transistors 107, 109, and 111 of different sizes as shown.

Conventionally, in order to set an optimal condition for the breakdown of the anti-fuse 113, the clamping PMOS transistor for supplying the external voltage Vpp to the anti-fuse 113 using the test mode in the programming controller 101 ( 107, 109, 111) were performed. That is, first, the voltage and current are supplied to the antifuse 113 using the first transistor 107, and the antifuse sensing unit 115 determines whether or not the dielectric breakdown is performed. The dielectric breakdown using the two transistors 109 is attempted. Repeated attempts in this test mode may cause breakdown of the antifuse 113 at the optimal transistor size.

However, in the case of using such a conventional test mode, a different clamp PMOS transistor size is required depending on the package due to a change in transistor characteristics due to process variables, etc., thus, it takes a long time to set the breakdown condition of the anti-fuse. There is a problem.

The present invention has been proposed to solve the above problems, and to reduce the test time for setting the dielectric breakdown conditions, to provide an anti-fuse test circuit that can be commonly applied to all the anti-fuse in the semiconductor device and a semiconductor device comprising the same The purpose.

The anti-fuse test circuit according to the present invention for achieving the above object, a plurality of driving force control unit for adjusting the driving force of the breakdown voltage, a plurality of reference anti-receiving each breakdown voltage determined by the plurality of driving force control unit A plurality of reference sensing unit for sensing whether the fuse and the dielectric breakdown of the plurality of reference anti-fuse.

The plurality of driving force adjusting units may each include one or more clamp PMOS transistors of different sizes, and the larger the size of the clamp PMOS transistor, the greater the driving force of the breakdown voltage.

In the semiconductor device according to the present invention, a program for driving the anti-fuse driver by using an anti-fuse driver, an anti-fuse test circuit for determining an insulation breakdown condition applied to the anti-fuse driver, and a test result of the anti-fuse test circuit. It includes a control unit.

The anti-fuse test circuit may include a plurality of driving force adjusting units for adjusting a driving force of breakdown voltages, a plurality of reference antifuses and respective reference antifuses to which respective breakdown voltages driven by the plurality of driving force adjusting units are applied. It may include a plurality of reference sensing unit for sensing whether the breakdown.

The anti-fuse driving unit senses a plurality of insulation breakdown setting units, a plurality of antifuses connected to the plurality of insulation breakdown setting units, and whether each of the plurality of antifuses breaks down the insulation, thereby activating an output signal of the breakdown antifuse. It may include a plurality of anti-fuse sensing unit.

According to the present invention, instead of selecting the size of the clamp PMOS transistor through the test mode, a reference antifuse test circuit in which the clamp PMOS transistors are classified by size is placed inside the semiconductor device, and the test results are used to generate a reference antifuse test circuit. This saves time and increases programming reliability.

In addition, an optimum antifuse dielectric breakdown condition may be set in each semiconductor device by reflecting various transistor characteristics due to process variables of the corresponding package and the like and applied to all antifuses in the semiconductor device.

1 illustrates a portion of a conventional antifuse programming circuit.
2 is a block diagram of a semiconductor device including an antifuse test circuit according to the present invention.
3 is a diagram illustrating an embodiment of the antifuse test circuit 203 of FIG. 2.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a configuration diagram of a semiconductor device including an antifuse test circuit 203 according to the present invention.

Referring to FIG. 2, the semiconductor device according to the present invention includes an antifuse test unit 201, an antifuse test circuit 203, and an antifuse test circuit for determining an insulation breakdown condition applied to the antifuse driver 201. The programming control unit 205 for driving the anti-fuse driver 201 by using the test result of 203.

The anti-fuse driver 201 serves to insulate the anti-fuse by applying a predetermined voltage and current to both ends of the anti-fuse and drive the current flow. For this purpose, a plurality of the dielectric breakdown setting units 211, 215, and 217 are provided. The anti-insulation of the plurality of anti-fuses (221, 223, 225) and the plurality of anti-fuses (221, 223, 225) connected to the dielectric breakdown setting unit (211, 215, 217) of each of the A plurality of anti-fuse sensing unit (231, 233, 235) for activating the output signal of the fuse.

Here, the dielectric breakdown setting unit 211 includes a plurality of clamp PMOS transistors 212, 213, and 214 having different sizes. In order for the anti-fuse 221, 223, and 225 to break down and pass a current, a voltage and a current of a predetermined magnitude or more must be applied. In this case, a plurality of clamp PMOS transistors 212, 213, and 214 of different sizes are used to set an optimal condition for the dielectric breakdown of the antifuses 221, 223, and 225. For example, referring to the dielectric breakdown setting unit 211 of the first antifuse 221, the width of the first transistor 212 is 5 μm, the second transistor 213 is 10 μm, and the third transistor 214. ) May be designed to be 20 μm. As the size of the transistor increases, the driving force of the breakdown voltage applied across the first antifuse 221, that is, the strength of the current applied to the first antifuse 221 is also increased. When at least one of the clamp PMOS transistors 212, 213, and 214 is turned on by the programming controller 205, a breakdown voltage is applied across the first antifuse 221. The strength of the voltage and current applied to the antifuse 221 is determined.

In the present exemplary embodiment, three clamp PMOS transistors 212, 213, and 214 are illustrated, but it is apparent that the number and size of the transistors may vary according to circumstances.

The anti-fuse sensing units 231, 233, and 235 sense whether or not the connected anti-fuses 221, 223, and 225 are insulated, respectively, to activate the output signals FUSE_OUT1 to FUSE_OUT3. Each sensing unit may include a PMOS transistor (not shown). For example, when the first antifuse 221 is insulated and destroyed to flow a current, the voltage at the upper node of the fuse drops, and the first sensing is performed. The PMOS transistor of the unit 231 may be turned on so that the first output signal FUSE_OUT1 is activated to be 'high'.

The antifuse test circuit 203 sets an optimum breakdown condition that can be commonly applied to all antifuses used in the semiconductor device. Instead of selecting the size of the clamp PMOS transistor through the test mode, which has been a problem in the prior art, a reference test circuit in which the clamp PMOS transistor is classified by size is disposed in the semiconductor device. The test circuit first performs an insulation breakdown test on the reference antifuse to find the optimum condition, and then uses the result in a general purpose in the semiconductor device, thereby reducing the time required in the test mode and at the same time, the reliability of the programming. You can increase it.

A detailed configuration of the anti-fuse test circuit 203 and a test procedure for setting an optimum breakdown condition will be described below with reference to FIG. 3.

The programming controller 205 optimizes the plurality of breakdown setting units 211, 215, and 217 in the antifuse driver 201 in response to the test result signals FB <1: 3> of the antifuse test circuit 203. Set the dielectric breakdown condition.

FIG. 3 is a diagram illustrating an embodiment of the antifuse test circuit 203 of FIG. 2.

Referring to FIG. 3, the anti-fuse test circuit 203 is driven by a plurality of driving force adjusting units 301, 303, and 305 and a plurality of driving force adjusting units 301, 303, and 305 for adjusting a driving force of breakdown voltage. A plurality of reference sensing units 321, 323, which detect whether the plurality of reference antifuses 311, 313, 315 and the plurality of reference antifuses 311, 313, 315 receive breakdown voltages are insulated or not. 325).

Each of the driving force adjusting units 301, 303, and 305 may include one or more clamp PMOS transistors of different sizes. In this embodiment, the first driving force adjusting unit 301 is one transistor having a width of 5 μm, the second driving force adjusting unit 303 is a 5 μm transistor and a 10 μm transistor, and the third driving force adjusting unit 305 is 5 It includes three transistors in total: 10 μm, 10 μm, and 20 μm. It is apparent that the number and size of the driving force control unit and the internal transistor may vary.

The reference antifuses 311, 313, and 315 are the same antifuses commonly used in semiconductor devices, and whether the dielectric breakdown is caused by various breakdown voltages and currents applied through the driving force control units 301, 303, and 305. Will be tested. For example, a test is performed with a clamp PMOS transistor having a size of 5 μm through the first driving force adjusting unit 301, and the second driving force adjusting unit 303 turns on only one 10 μm size of two transistors or two. All dogs can be turned on to test for 10 μm and 15 μm sizes. Similarly, the third driving force adjusting unit 305 may test a size of 20 μm, 25 μm, 30 μm, and 35 μm by turning on some or all of the three transistors. (It is assumed that the total size of the clamp PMOS transistor is proportional to the magnitude of the applied current.)

The test may be performed under such various conditions to find an optimal condition for the dielectric breakdown of the reference antifuse 311, 313, and 315. For example, when the second driving force control unit 303 has a size of 15 μm, when the second reference antifuse 313 is not insulated, the third driving force control unit 305 has a size of 20 μm. If the third reference antifuse 315 is broken, it may be determined that an optimal breakdown condition is to use a clamp PMOS transistor having a size of 20 μm.

The reference sensing units 321, 323, and 325 detect whether the corresponding reference antifuses 311, 313, and 315 are insulated or not, and feed back the test results FB <1: 3> to the programming controller 205. . The programming controller 205 determines the optimal dielectric breakdown condition using the test result FB <1: 3> received as a feedback, and transfers it to all dielectric breakdown setting units 211, 215, and 217 in the semiconductor device. . If the size of the clamp PMOS transistor is 20 μm as described above, the programming controller 205 controls only 20 μm transistors to be turned on in each insulation break setting unit 211, 215, 217. .

As described above, in the present invention, instead of selecting the size of the clamp PMOS transistor through the test mode, a test circuit including a reference antifuse in which the clamp PMOS transistor is classified by size is placed inside the semiconductor device, and the test result is used. An antifuse test circuit and a semiconductor device including the same have been proposed to reduce the time required in the test mode and increase the reliability of programming.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by.

Claims (9)

A plurality of driving force adjusting unit for adjusting the driving force of the breakdown voltage;
A plurality of reference antifuses receiving respective breakdown voltages determined by the plurality of driving force adjusting units; And
A plurality of reference sensing unit for sensing the breakdown of the plurality of reference anti-fuse
Anti-fuse test circuit comprising a.
The method of claim 1,
The plurality of driving force adjusting unit
Each containing one or more different size clamp PMOS transistors
Antifuse test circuit.
The method of claim 2,
The larger the clamp PMOS transistor is, the larger the driving force of the breakdown voltage is.
Antifuse test circuit. Anti-fuse drive unit;
An anti-fuse test circuit for determining an insulation breakdown condition applied to the anti-fuse driver; And
A programming controller which drives the anti-fuse driver by using a test result of the anti-fuse test circuit
.
The method of claim 4, wherein
The antifuse test circuit
A plurality of driving force adjusting unit for adjusting the driving force of the breakdown voltage;
A plurality of reference antifuses receiving respective breakdown voltages driven by the plurality of driving force adjusting units; And
It includes a plurality of reference sensing unit for sensing whether the plurality of reference anti-fuse insulation breakdown
Semiconductor device.
6. The method of claim 5,
The plurality of driving force adjusting unit
Each containing one or more different size clamp PMOS transistors
Semiconductor device.
The method according to claim 6,
The larger the clamp PMOS transistor is, the larger the driving force of the breakdown voltage is.
Semiconductor device.
The method of claim 4, wherein
The anti-fuse drive unit
A plurality of breakdown setting units;
A plurality of anti-fuses connected to the plurality of breakdown setting units, respectively; And
It includes a plurality of anti-fuse sensing unit for sensing the insulation breakdown of each of the plurality of anti-fuse to activate the output signal of the insulating anti-fuse
Semiconductor device.

The method of claim 8,
The plurality of breakdown setting unit
Each comprising one or more different sized clamp PMOS transistors,
Driving the plurality of antifuse using some or all of the plurality of clamp PMOS transistors of different sizes with the driving force of the breakdown voltage determined by the antifuse test circuit.
Semiconductor device.
KR1020100099880A 2010-10-13 2010-10-13 Antifuse test circuit and semiconductor device including the same KR20120038237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100099880A KR20120038237A (en) 2010-10-13 2010-10-13 Antifuse test circuit and semiconductor device including the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100099880A KR20120038237A (en) 2010-10-13 2010-10-13 Antifuse test circuit and semiconductor device including the same

Publications (1)

Publication Number Publication Date
KR20120038237A true KR20120038237A (en) 2012-04-23

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