KR20120036431A

KR20120036431A - Reapter

Info

Publication number: KR20120036431A
Application number: KR1020100098096A
Authority: KR
Inventors: 이주현
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2010-10-08
Filing date: 2010-10-08
Publication date: 2012-04-18

Abstract

The repeater may include an enable signal delay unit configured to delay the enable signal in response to the test signal to generate a delay enable signal; And an address output unit configured to amplify an input address and output the output address in response to the delay enable signal.

Description

Repeater {REAPTER}

The present invention relates to a repeater.

The semiconductor memory device receives an address through a pad and performs an operation on a low address path and an operation on a column address path. In the operation of the low address path, a low address is generated from an address transmitted through a pad in synchronization with a low address strobe signal, and a word line connected to a memory cell is selected by the generated low address. Meanwhile, in the operation of the column address path, a column address is generated from an address transmitted through a pad in synchronization with a column address strobe signal, and data generated between the bit line and the input / output line is exchanged by the generated column address. Enable the output enable signal.

In a semiconductor memory device, in order to perform a read operation or a write operation, an operation regarding a low address path and an operation regarding a column address path should be performed. For this purpose, an address must be input through a pad. The address input through the pad is transmitted to the banks included in the semiconductor memory device. Since the signal level of the address is attenuated by the loading of the address transmission line, the address is amplified by the repeater provided in the address transmission line. Is sent.

1 is a view of a repeater according to the prior art.

As shown in FIG. 1, the repeater of the related art is driven by a read enable signal RD_EN input at a logic high level during a read operation to amplify the input address CA_IN and output it to the output address CA_OUT. .

However, in the repeater having such a configuration, when a PVT (Proess, Voltage, Temperature) characteristic change occurs in the transmission line to which the input address CA_IN is transmitted, the input address (RD_EN) is enabled in the section where the lead enable signal RD_EN is enabled. CA_IN) may not be delivered. That is, since there is no input margin between the read enable signal RD_EN and the input address CA_IN, an input operation CA_IN for a read operation is amplified and a malfunction occurs that is not output to the output address CA_OUT.

The present invention discloses a repeater capable of preventing a malfunction due to a change in the characteristics of an address line.

To this end, the present invention comprises an enable signal delay unit for generating a delay enable signal by delaying the enable signal in response to the test signal; And an address output unit configured to amplify an input address and output the output address in response to the delay enable signal.

1 is a view of a repeater according to the prior art.
2 is a block diagram showing the configuration of a repeater according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of an enable signal delay unit included in the repeater shown in FIG. 2.
FIG. 4 is a circuit diagram of an address output unit included in the repeater shown in FIG. 2.
FIG. 5 is a timing diagram for describing an operation of the repeater illustrated in FIG. 2.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

2 is a block diagram showing the configuration of a repeater according to an embodiment of the present invention.

As shown in FIG. 2, the repeater according to the present exemplary embodiment delays the enable signal EN by a predetermined period in response to the first and second test signals TM <1: 2>, and thus the delay enable signal. An enable signal delay unit 1 for generating (END) and an address output unit 2 for outputting the output address CA_OUT by amplifying the input address CA_IN in response to the delay enable signal END do.

As shown in FIG. 3, the enable signal delay unit 1 includes a first enable signal delay unit 11 and a second enable signal delay unit 12.

The first enable signal delay unit 11 is turned on in response to the first delay unit 110 for delaying the enable signal EN by a predetermined first delay period and the first test signal TM <1>. Transfer gate T11 for transmitting the enable signal EN and a transfer gate T12 for turning on in response to the first test signal TM <1> to transfer an output signal of the first delay unit 110. It includes.

The second enable signal delay unit 12 includes a second delay unit 120 for delaying an output signal of the first enable signal delay unit 11 by a predetermined second delay period, and a second test signal TM < 2>) is turned on in response to the first enable signal delay unit 11 and transfers the output signal of the transfer gate T13, and the second delay is turned on in response to the second test signal TM <2>. And a transfer gate T14 for transmitting the output signal of the 120.

The enable signal delay unit 1 having the above-described configuration converts the enable signal EN when the first test signal TM <1> and the second test signal TM <2> are at a logic low level. After inverting buffering through (IV13), the signal is output as a delay enable signal END. In addition, the enable signal delay unit 1 may enable the signal EN when the first test signal TM <1> is at a logic high level and the second test signal TM <2> is at a logic low level. Is delayed through the first delay unit 110, inverted buffered through the inverter IV13, and outputted as a delay enable signal END. In addition, the enable signal delay unit 1 may enable the signal EN when the first test signal TM <1> is at a logic low level and the second test signal TM <2> is at a logic high level. Is delayed through the second delay unit 120, inverted through the inverter IV13, and output as a delay enable signal END. In addition, when both the first test signal TM <1> and the second test signal TM <2> are at a logic high level, the enable signal EN may be set to the first delay unit 110 and the second delay unit. After the inversion buffering through the 120 and the inverter IV13, the signal is output as a delay enable signal END.

An address output section 2, as shown in FIG. 4, includes a precharge section 21, a drive signal generation section 22, and a drive section 23.

The precharge unit 21 is connected between the inverter IV21, the power supply voltage VDD, and the node nd21 to operate as a pull-up device for pulling up the node nd21 and the latch unit 210. The node nd21 is precharged to the logic high level in response to the precharge signal HSCTRL applied at the logic high level during the precharge operation.

The driving signal generator 22 generates a pull-up signal PU and a pull-down signal PD according to the level of the input address CA_IN in the section where the delay enable signal END is at a logic low level. That is, when the input address CA_IN is at the logic high level, the pull-up signal PU is enabled at the logic low level, and the pull-down signal PD is disabled at the logic low level. On the other hand, when the input address CA_IN is at a logic low level, the pull-down signal PD is disabled at a logic high level, and the pull-down signal PD is enabled at a logic high level.

The driver 23 receives a pull-up signal PU enabled at a logic low level and a PMOS transistor P22, which is a pull-up device that pulls up the output address CA_OUT to a logic high level, and is enabled at a logic high level. The NMOS transistor N22, which is a pull-down device that receives the pull-down signal PD and pulls down the output address CA_OUT to a logic low level, is included.

The operation of the repeater having such a configuration will be described below with reference to FIG. 5.

As in the first case (CASE 1), when the input address CA_IN is input in synchronization with the timing T3, the timing T6 and the timing T9, the repeater of the present embodiment has a first test signal TM <1> and a second test. Regardless of the level of the signal TM <2>, the input address CA_IN is amplified and output to the output address CA_OUT.

On the other hand, as in the second case (CASE2), the operation of the repeater in the case where the input address (CA_IN) is delayed for a predetermined period and transmitted by the change in the PVT characteristics of the transmission line to which the input address (CA_IN) is transmitted as follows. .

First, as in time T3, both the first test signal TM <1> and the second test signal TM <2> are applied at a logic low level, so that the enable signal EN is inverted and buffered, and thus the delay enable signal. If the signal is output as (END), the output signal CA_OUT is not output properly due to insufficient margin of the delay enable signal END and the input address CA_IN.

Next, as in the time point T6, when the first test signal TM <1> is at the logic high level and the second test signal TM <2> is at the logic low level, the enable signal EN is set to zero. Since the delay is delayed through the delay unit 110 and output as a delay enable signal END, the margin of the delay enable signal END and the input address CA_IN is secured.

Next, when the first test signal TM <1> and the second test signal TM <2> are at the logic high level, as in the time point T9, the enable signal EN is the first delay unit 110. And the second delay unit 120 is delayed and then inverted and output as a delay enable signal END, thereby ensuring a margin between the delay enable signal END and the input address CA_IN.

As described above, the repeater of the present exemplary embodiment is configured to delay delay signal END by the first test signal TM <1> and the second test signal TM <2> when the PVT characteristic change occurs. By checking whether the input address CA_IN is secured, malfunctions can be prevented.

1: enable signal delay unit 11: first enable signal delay unit
12: second enable signal delay unit 2: address output unit
21: precharge unit 22: drive signal generation unit
23: drive unit

Claims

An enable signal delay unit for delaying the enable signal in response to the test signal to generate a delay enable signal; And
And an address output unit configured to amplify an input address and output the output address in response to the delay enable signal.

The repeater of claim 1, wherein the enable signal delay unit outputs the enable signal in response to the test signal, or delays the enable signal by a predetermined period.

The method of claim 2, wherein the enable signal delay unit
A delay unit delaying the enable signal by the predetermined period;
A first transfer element transferring the enable signal in response to the test signal; And
And a second transfer device configured to transfer an output signal of the delay unit in response to the test signal.

The method of claim 1, wherein the address output unit
A driving signal generation unit receiving the input address and the delay enable signal and generating a pull-up signal and a pull-down signal; And
And a driving unit for driving the output address in response to the pull-up signal and the pull-down signal.

The repeater of claim 4, wherein the pull-up signal and the pull-down signal are selectively enabled according to the level of the input address in a section in which the delay enable signal is enabled.

The method of claim 4, wherein
And a precharge unit for driving an input node of the input address in response to a precharge signal.