KR20120027850A - Duty correcting circuit having a duty detector, delay-locked loop circuit having the duty correcting circuit and method of duty correction - Google Patents

Duty correcting circuit having a duty detector, delay-locked loop circuit having the duty correcting circuit and method of duty correction Download PDF

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Publication number
KR20120027850A
KR20120027850A KR1020100089654A KR20100089654A KR20120027850A KR 20120027850 A KR20120027850 A KR 20120027850A KR 1020100089654 A KR1020100089654 A KR 1020100089654A KR 20100089654 A KR20100089654 A KR 20100089654A KR 20120027850 A KR20120027850 A KR 20120027850A
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South Korea
Prior art keywords
clock signal
output clock
duty
signal
delay
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KR1020100089654A
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Korean (ko)
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김준배
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삼성전자주식회사
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Priority to KR1020100089654A priority Critical patent/KR20120027850A/en
Priority to US13/078,151 priority patent/US8542045B2/en
Publication of KR20120027850A publication Critical patent/KR20120027850A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

A duty correction circuit and a duty correction method including a digital duty detector are disclosed. The duty cycle correction circuit includes a duty cycle corrector and a duty detector. The duty cycle corrector generates an output clock signal by correcting a duty ratio of the input clock signal in response to the duty-up signal and the duty-down signal. The duty detector synchronizes the output clock signal to the inverted delayed output clock signal, detects the duty ratio of the output clock signal using the inverted delayed output clock signal, and generates a duty-up signal and a duty-down signal. Therefore, the duty cycle correction circuit can accurately detect the duty ratio of the output clock signal and correct the duty.

Description

DUTY CORRECTING CIRCUIT HAVING A DUTY DETECTOR, DELAY-LOCKED LOOP CIRCUIT HAVING THE DUTY CORRECTING CIRCUIT AND METHOD OF DUTY CORRECTION}

The present invention relates to a duty cycle correction circuit and a duty cycle correction method comprising a duty detector.

In a semiconductor device, in particular, a semiconductor memory device, a clock signal for operating logic circuits is used. In order to use a clock signal in an internal circuit that performs various functions, an internal clock signal synchronized with an external input clock signal and having a duty compensated in consideration of a clock transmission path is required.

It is an object of the present invention to provide a duty correction circuit comprising a digital duty detector with high precision.

Another object of the present invention is to provide a delay synchronization loop circuit including the duty correction circuit.

Another object of the present invention is to provide a duty correction method for detecting the duty of the output clock signal and correcting the duty in a digital manner with high precision.

In order to achieve the above object, a duty cycle correction circuit according to an embodiment of the present invention includes a duty cycle corrector and a duty detector.

The duty cycle corrector generates an output clock signal by correcting a duty ratio of the input clock signal in response to the duty-up signal and the duty-down signal. The duty detector generates a delayed output clock signal by delaying the output clock signal, inverts a phase of the delayed output clock signal to generate an inverted and delayed output clock signal, and applies the delayed output clock signal to the inverted delayed output clock signal. Locking an output clock signal, sampling the output clock signal using the inverted delayed output clock signal to generate sample data, and based on a logic state of the sample data, a duty ratio of the output clock signal. ratio) and generate the duty-up signal and the duty-down signal.

According to an embodiment of the present invention, the duty detector is configured to delay the output clock signal based on a logic state of first sample data sampling the output clock signal at a rising edge of the inverted delayed output clock signal. Adjust a time and detect a duty ratio of the output clock signal based on a logic state of second sample data sampling the output clock signal at a falling edge of the inverted delayed output clock signal. Can be.

According to an embodiment of the present invention, the duty detector may adjust the delay time of the output clock signal by using a delay line of a delay synchronization loop circuit.

According to an embodiment of the present invention, the duty detector may include a delay circuit, an inverter, a first flip-flop, a second flip-flop, and a control circuit.

The delay circuit delays the output clock signal in response to a delay-up signal and a delay-down signal to generate the delayed output clock signal. The inverter inverts the phase of the delayed output clock signal to generate the inverted delayed output clock signal. The first flip-flop samples the output clock signal in response to the falling edge of the inverted delayed output clock signal and generates first sample data. The second flip-flop samples the output clock signal in response to the rising edge of the inverted delayed output clock signal and generates second sample data. The control circuit generates the delay-up signal, the delay-down signal, the duty-up signal and the duty-down signal based on the logic states of the first and second sample data.

According to an embodiment of the present invention, the control circuit may include a delay control circuit and a duty control circuit.

The delay control circuit generates the delay-up signal, the delay-down signal, and the output enable signal based on the logic state of the second sample data. The duty control circuit generates the duty-up signal and the duty-down signal based on the logic state of the output enable signal and the first sample data.

According to an embodiment of the present invention, the duty detector generates a delay-up signal when the second sample data is in a logic low state to increase a delay time of the output clock signal, and the second sample data is logic high. In this state, a delay-down signal may be generated to reduce the delay time of the output clock signal.

According to an embodiment of the present invention, the duty detector generates a duty-up signal when the output enable signal is enabled and the first sample data is in a logic low state to increase the duty ratio of the output clock signal. When the output enable signal is enabled and the first sample data is in a logic high state, a duty-down signal may be generated to reduce the duty ratio of the output clock signal.

According to one embodiment of the invention, the delay circuit may be a delay line of a delay synchronization loop.

According to an embodiment of the present invention, the duty detector may include a delay circuit, a phase separator, a first flip-flop, a second flip-flop, and a control circuit.

The delay circuit delays the output clock signal in response to a delay-up signal and a delay-down signal to generate the delayed output clock signal. A phase separator separates the phase of the delayed output clock signal to generate the inverted delayed output clock signal having a phase opposite to the delayed output clock signal and the delayed output clock signal. The first flip-flop samples the output clock signal in response to the delayed output clock signal and generates first sample data. The second flip-flop samples the output clock signal in response to the inverted delayed output clock signal and generates second sample data. The control circuit generates the delay-up signal, the delay-down signal, the duty-up signal and the duty-down signal based on the logic states of the first and second sample data.

According to an embodiment of the present invention, the first flip-flop samples the output clock signal in response to the rising edge of the delayed output clock signal, and the second flip-flop is the rising edge of the inverted delayed output clock signal. In response, the output clock signal may be sampled.

According to an embodiment of the present invention, the duty cycle correction circuit generates a duty cycle correction code in response to the duty-up signal and the duty down signal and provides the duty cycle correction section to the duty cycle corrector. It may further include a code generator.

The delay locked loop circuit according to one embodiment of the present invention includes a duty cycle corrector, a delay circuit, a duty detector, a replica path, and a phase detector.

The duty cycle corrector generates an output clock signal by correcting a duty ratio of the input clock signal in response to the duty-up signal and the duty-down signal. The delay circuit delays the output clock signal to generate a delayed output clock signal. The duty detector generates an inverted and delayed output clock signal by inverting a phase of the delayed output clock signal, locks the output clock signal to the inverted delayed output clock signal, and inverts the delayed output clock signal. Sample the output clock signal using a signal to generate sample data, detect a duty ratio of the output clock signal based on a logic state of the sample data, and detect the duty-up signal and the duty-down signal. Generate a signal. After the duty ratio correction is completed, the replica path delays the delayed output clock signal to generate a feedback signal. After the duty ratio correction is completed, the phase detector detects phases of the input clock signal and the feedback signal to generate an up signal and a down signal, and provide the up signal and the down signal to the delay circuit.

According to an embodiment of the present invention, the delay circuit may be a delay line of the delay synchronization loop circuit.

According to one embodiment of the present invention, the delay lock loop circuit generates a duty correction code in response to the duty-up signal and the duty-down signal and provides the duty correction code to the duty cycle corrector. The apparatus may further include a correction code generator.

According to one embodiment of the present invention, the replica path has a delay corresponding to a transmission time from a point at which an internal clock signal, which is a delayed output clock signal after the duty ratio correction is generated, to a point at which the internal clock signal is to be used. You can have time.

A semiconductor device according to one embodiment of the present invention includes a delay synchronization loop circuit for generating an internal clock signal synchronized with an external clock signal and duty cycle corrected, and an internal circuit operating in response to the internal clock signal. The delay synchronization loop circuit corrects a duty ratio of a first internal clock signal corresponding to the external clock signal. The duty cycle correction circuit includes a duty cycle corrector and a duty detector. The duty cycle corrector generates an output clock signal by correcting a duty ratio of the first internal clock signal in response to the duty-up signal and the duty-down signal. The duty detector generates a delayed output clock signal by delaying the output clock signal, inverts a phase of the delayed output clock signal to generate an inverted and delayed output clock signal, and applies the delayed output clock signal to the inverted delayed output clock signal. Locking an output clock signal, sampling the output clock signal using the inverted delayed output clock signal to generate sample data, and based on a logic state of the sample data, a duty ratio of the output clock signal. ratio) and generate the duty-up signal and the duty-down signal.

A duty cycle correction method according to an embodiment of the present invention includes generating an output clock signal by correcting a duty ratio of an input clock signal in response to a duty-up signal and a duty-down signal, and delaying the output clock signal to delay the delay. Generating an output clock signal, inverting a phase of the delayed output clock signal to generate an inverted and delayed output clock signal, and locking the output clock signal to the inverted delayed output clock signal Sampling the output clock signal using the inverted delayed output clock signal to generate sample data; detecting a duty ratio of the output clock signal based on a logic state of the sample data; Generating a duty-up signal and the duty-down signal.

According to one embodiment of the present invention, the duty cycle correction method further includes a delay time of the output clock signal based on a logic state of sample data sampled at the rising edge of the inverted delayed output clock signal. Can be adjusted.

According to an embodiment of the present invention, the duty ratio of the output clock signal is determined based on a logic state of sample data sampled at the falling edge of the inverted delayed output clock signal. Can be detected.

The duty cycle correction circuit including the duty detector according to an embodiment of the present invention digitally adjusts the delay time of the sampling clock signal and detects the duty of the output clock signal based on the logic state of the sampled data. Therefore, the duty cycle correction circuit can accurately detect the duty ratio of the output clock signal and correct the duty ratio. Therefore, the semiconductor device including the duty cycle correction circuit consumes less power and has a smaller chip size.

1 is a block diagram illustrating a duty cycle correction circuit according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating one example of a duty detector included in the duty cycle correction circuit of FIG. 1.
3 to 5 are timing diagrams illustrating logic states of an output clock signal at a detection time according to a duty ratio when the output clock signal and the inverted delay output clock signal are locked.
6 is a truth table illustrating an operation of a control circuit included in the duty detector of FIG. 2.
7 to 12 are timing diagrams illustrating an operation of the duty detector of FIG. 2.
FIG. 13 is a block diagram illustrating an example of a delay circuit included in the duty detector of FIG. 2.
14 is a circuit diagram illustrating another example of a duty detector included in the duty cycle correction circuit of FIG. 1.
15 is a block diagram illustrating a duty cycle correction circuit according to another exemplary embodiment of the present invention.
16 is a block diagram illustrating one example of a delayed synchronization loop circuit including a duty cycle correction circuit according to embodiments of the present invention.
17 is a block diagram illustrating another example of a delayed synchronization loop circuit including a duty cycle correction circuit according to embodiments of the present invention.
18 is a block diagram illustrating an example of a semiconductor device including a delay synchronization loop circuit according to example embodiments of the inventive concepts.
19 is a flowchart illustrating a duty cycle correction method according to an embodiment of the present invention.
20 is a flowchart illustrating a method of generating a delayed output clock signal included in the duty cycle correction method of FIG. 19.
21 is a flowchart illustrating a method of detecting a duty ratio of an output clock signal included in the duty correction method of FIG. 19.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may exist in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a duty cycle correction circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the duty cycle correction circuit 100 includes a duty cycle corrector 110 and a duty detector 120.

The duty cycle corrector 110 corrects the duty ratio of the input clock signal in response to the duty-up signal DUP and the duty-down signal DDN to generate the output clock signal CLKOUT. The duty detector 120 delays the output clock signal CLKOUT to generate a delayed output clock signal, inverts the phase of the delayed output clock signal to generate an inverted and delayed output clock signal, and inverts the delay. Locking the output clock signal to an output clock signal, sampling the output clock signal CLKOUT using the inverted delayed output clock signal to generate sample data, and outputting the output clock based on a logic state of the sample data. The duty ratio of the signal CLKOUT is detected and a duty-up signal DUP and a duty-down signal DDN are generated.

The duty detector 120 adjusts the delay time of the output clock signal CLKOUT based on the logic state of the first sample data that sampled the output clock signal CLKOUT at the rising edge of the inverted delayed output clock signal. A duty ratio of the output clock signal CLKOUT may be detected based on a logic state of the second sample data sampled at the falling edge of the inverted delayed output clock signal. . The duty detector 120 may adjust the delay time of the output clock signal CLKOUT by using a delay line of the delay synchronization loop circuit.

FIG. 2 is a circuit diagram illustrating an example of the duty detector 120 included in the duty cycle correction circuit 100 of FIG. 1.

Referring to FIG. 2, the duty detector 120 may include a delay circuit 121, an inverter INV1, a first flip-flop 124, a second flip-flop 125, and a control circuit 126.

The delay circuit 121 delays the output clock signal CLKOUT in response to the delay-up signal DLYUP and the delay-down signal DLYDN to generate the delayed output clock signal CLKOUT_D. The inverter INV1 inverts the phase of the delayed output clock signal CLKOUT_D to generate the inverted delayed output clock signal CLKOUT_BD. The first flip-flop 124 samples the output clock signal CLKOUT in response to the falling edge of the inverted delayed output clock signal CLKOUT_BD and generates first sample data SA. The second flip-flop 125 samples the output clock signal CLKOUT in response to the rising edge of the inverted delayed output clock signal CLKOUT_BD and generates second sample data SB. The control circuit 126 may include a delay-up signal DLYUP, a delay-down signal DLYDN, and a duty-up signal DUP based on logic states of the first sample data SA and the second sample data SB. And a duty-down signal (DDN).

The control circuit 126 may include a duty control circuit 127 and a delay control circuit 128.

The delay control circuit 128 generates a delay-up signal DLYUP, a delay-down signal DLYDN, and an output enable signal ED_ALIGN based on the logic state of the second sample data SB. The duty control circuit 127 generates a duty-up signal DUP and a duty-down signal DDN based on the logic state of the output enable signal ED_ALIGN and the first sample data SA.

The duty detector 120 generates a delay-up signal DLYUP when the second sample data SB is in a logic low state to increase the delay time of the output clock signal CLKOUT, and the second sample data SB is logic. In the high state, the delay-down signal DLYDN may be generated to reduce the delay time of the output clock signal CLKOUT.

In addition, when the output enable signal ED_ALIGN is enabled and the first sample data SA is in a logic low state, the duty detector 120 generates a duty-up signal DUP to generate a duty ratio of the output clock signal CLKOUT. When the output enable signal ED_ALIGN is enabled and the first sample data SA is logic high, the duty-down signal DDN may be generated to reduce the duty ratio of the output clock signal CLKOUT. have.

In FIG. 2, the delay circuit 121 may be a delay line of a delay synchronization loop circuit.

3 to 5 are timing diagrams showing logic states of the output clock signal CLKOUT at the detection time according to the duty ratio when the output clock signal CLKOUT and the inverted delay output clock signal are locked.

FIG. 3 shows the logic of the output clock signal CLKOUT at the detection point DP when the output clock signal CLKOUT and the inverted delay output clock signal CLKOUT_BD are locked when the duty ratio is 60:40. Indicates the state. 4 shows the logic of the output clock signal CLKOUT at the detection point DP when the output clock signal CLKOUT and the inverted delayed output clock signal CLKOUT_BD are locked when the duty ratio is 40:60. Indicates the state. FIG. 5 shows the logic of the output clock signal CLKOUT at the detection point DP when the output clock signal CLKOUT and the inverted delay output clock signal CLKOUT_BD are locked when the duty ratio is 50:50. Indicates the state.

Referring to the timing diagram of FIG. 3, when the output clock signal CLKOUT and the inverted delay output clock signal CLKOUT_BD are locked, the output clock signal CLKOUT at the detection time DP is in a logic high state. Has Referring to the timing diagram of FIG. 4, when the output clock signal CLKOUT and the inverted delay output clock signal CLKOUT_BD are locked, the output clock signal CLKOUT at the detection point DP is in a logic low state. Has Referring to the timing diagram of FIG. 5, when the output clock signal CLKOUT and the inverted delay output clock signal CLKOUT_BD are synchronized with each other and the duty ratio approaches 50:50, the output clock signal at the detection time DP is detected. (CLKOUT) alternates between a logic high state and a logic low state. In this state, it can be seen that the duty cycle correction by the duty cycle correction circuit 100 is completed.

6 is a truth table illustrating an operation of a control circuit included in the duty detector of FIG. 2.

Referring to FIG. 6, when the second sample data SB is in a logic low state, the duty detector 120 generates a delay-up signal DLYUP to increase the delay time of the output clock signal CLKOUT. When the second sample data SB is in the logic high (1) state, the delay-down signal DLYDN may be generated to reduce the delay time of the output clock signal CLKOUT. In addition, when the output enable signal ED_ALIGN is enabled and the first sample data SA is in a logic low (0) state, the duty detector 120 generates a duty-up signal DUP to output the output clock signal CLKOUT. When the duty cycle of the output enable signal ED_ALIGN is enabled and the first sample data SA is logic high (1), the duty-down signal DDN is generated to generate the duty cycle of the output clock signal CLKOUT. The duty ratio can be reduced.

7 to 12 are timing diagrams illustrating an operation of the duty detector of FIG. 2. 7 through 12 illustrate waveforms of the output clock signal CLKOUT, the delayed output clock signal CLKOUT_D, and the inverted delayed output clock signal CLKOUT_BD.

7 to 9 are timing diagrams illustrating an operation of the duty detector of FIG. 2 when a high state section of the output clock signal CLKOUT is greater than a low state section. 10 to 12 are timing diagrams illustrating an operation of the duty detector of FIG. 2 when the high state section of the output clock signal CLKOUT is smaller than the low state section.

Referring to FIG. 7, the rising edges of the output clock signal CLKOUT and the inverted delayed output clock signal CLKOUT_BD are not locked. The output clock signal CLKOUT detected at the rising edge of the inverted delayed output clock signal CLKOUT_BD has a logic low state SB = 0. Accordingly, the duty detector 120 may increase the delay time of the output clock signal CLKOUT by generating the delay-up signal DLYUP.

Referring to FIG. 8, the rising edges of the output clock signal CLKOUT and the inverted delay output clock signal CLKOUT_BD are not synchronized. The output clock signal CLKOUT detected at the rising edge of the inversion delay output clock signal CLKOUT_BD has a logic high state (SB = 1). Therefore, the duty detector 120 may generate the delay-down signal DLYDN to reduce the delay time of the output clock signal CLKOUT (DELAY DOWN).

Referring to FIG. 9, the rising edges of the output clock signal CLKOUT and the inverted delayed output clock signal CLKOUT_BD are locked. The output clock signal CLKOUT detected at the falling edge of the inverted delayed output clock signal CLKOUT_BD has a logic high state SA = 1. Accordingly, the duty detector 120 may generate a duty-down signal DDN to reduce the duty ratio of the output clock signal CLKOUT (DUTY DOWN).

Referring to FIG. 10, the rising edges of the output clock signal CLKOUT and the inverted delayed output clock signal CLKOUT_BD are not locked. The output clock signal CLKOUT detected at the rising edge of the inverted delayed output clock signal CLKOUT_BD has a logic low state SB = 0. Accordingly, the duty detector 120 may increase the delay time of the output clock signal CLKOUT by generating the delay-up signal DLYUP.

Referring to FIG. 11, the rising edges of the output clock signal CLKOUT and the inverted delay output clock signal CLKOUT_BD are not synchronized. The output clock signal CLKOUT detected at the rising edge of the inversion delay output clock signal CLKOUT_BD has a logic high state (SB = 1). Therefore, the duty detector 120 may generate the delay-down signal DLYDN to reduce the delay time of the output clock signal CLKOUT (DELAY DOWN).

Referring to FIG. 12, the rising edges of the output clock signal CLKOUT and the inverted delayed output clock signal CLKOUT_BD are locked. The output clock signal CLKOUT detected at the falling edge of the inverted delayed output clock signal CLKOUT_BD has a logic low state SA = 0. Therefore, the duty detector 120 may generate a duty-up signal DUP to increase the duty ratio of the output clock signal CLKOUT.

FIG. 13 is a block diagram illustrating an example of the delay circuit 121 included in the duty detector 120 of FIG. 2.

Referring to FIG. 13, the delay circuit 121 includes a delay enabling circuit 123, a delay circuit composed of delays D1 to D5, multiplexers MUX1 and MUX2, and an interpolator. (122) may be included.

The delay enable circuit 123 generates delay control signals based on the delay-up signal DLYUP and the delay-down signal DLYDN. Each of the delayers D1 to D5 constituting the delay circuit is activated in response to the delay control signals, and delays the output clock signal CLKOUT by the delay amount D of the delayers D1 to D5. For example, D1 delays the output clock signal CLKOUT by the delay amount D, and D3 delays the output signal of the delay D2 by the delay amount D. The first multiplexer MUX1 selects and outputs signals of input terminals of odd-numbered delayers among the delayers D1 to D5, and the second multiplexer MUX2 selects even-numbered delayers among the delayers D1 to D5. Selects and outputs the signals at their inputs. The interpolator 122 detects a value between the output signal of the first multiplexer MUX1 and the output signal of the second multiplexer MUX2 and outputs the internal clock signal ICLK. For example, the interpolator 122 performs interpolation on the signal of the input terminal of D1 and the signal of the input terminal of D2, and outputs the output clock signal CLKOUT corresponding to 1/2 of the delay amount D of the delay unit. The internal clock signal ICLK is generated by delaying time.

FIG. 14 is a circuit diagram illustrating another example of the duty detector 120 included in the duty cycle correction circuit 100 of FIG. 1.

Referring to FIG. 14, the duty detector 120a may include a delay circuit 121, a phase separator PS1, a first flip-flop 124a, a second flip-flop 125, and a control circuit 126. .

The delay circuit 121 delays the output clock signal CLKOUT in response to the delay-up signal DLYUP and the delay-down signal DLYDN to generate the delayed output clock signal CLKOUT_D. The phase separator PS1 separates the phase of the delayed output clock signal CLKOUT_D to generate an inverted delayed output clock signal CLKOUT_BD having a phase opposite to the delayed output clock signal CLKOUT_D and the delayed output clock signal CLKOUT_D. . The first flip-flop 124a samples the output clock signal CLKOUT in response to the rising edge of the delayed output clock signal CLKOUT_D and generates first sample data SA. The second flip-flop 125 samples the output clock signal CLKOUT in response to the rising edge of the inverted delayed output clock signal CLKOUT_BD and generates second sample data SB. The control circuit 126 may include a delay-up signal DLYUP, a delay-down signal DLYDN, and a duty-up signal DUP based on logic states of the first sample data SA and the second sample data SB. And a duty-down signal (DDN).

The control circuit 126 may include a duty control circuit 127 and a delay control circuit 128.

The delay control circuit 128 generates a delay-up signal DLYUP, a delay-down signal DLYDN, and an output enable signal ED_ALIGN based on the logic state of the second sample data SB. The duty control circuit 127 generates a duty-up signal DUP and a duty-down signal DDN based on the logic state of the output enable signal ED_ALIGN and the first sample data SA.

The duty detector 120a of FIG. 14 uses the phase separator PS1 instead of the inverter INV1 included in the duty detector 120 of FIG. 2 to delay the clock signal CLKOUT_D and the delay output clock signal CLKOUT_D. Generates an inverted delayed output clock signal CLKOUT_BD having the opposite phase. In addition, the first flip-flop 124a samples the output clock signal CLKOUT in response to the rising edge of the delayed output clock signal CLKOUT_D and generates first sample data SA.

The operation of the duty detector 120a of FIG. 14 is similar to that of the duty detector 120 of FIG. 2. Therefore, the description of the operation of the duty detector 120a of FIG. 14 will be omitted.

15 is a block diagram illustrating a duty cycle correction circuit 200 according to another embodiment of the present invention.

Referring to FIG. 15, the duty cycle correction circuit 200 includes a duty cycle corrector 110, a duty detector 120, and a duty correction code generator 150.

The duty cycle correction unit 110 generates an output clock signal CLKOUT by correcting a duty ratio of the input clock signal CLKIN in response to the duty correction code CODE_DCC. The duty detector 120 delays the output clock signal CLKOUT to generate a delayed output clock signal, inverts the phase of the delayed output clock signal to generate an inverted and delayed output clock signal, and inverts the delay. Locking the output clock signal to an output clock signal, sampling the output clock signal CLKOUT using the inverted delayed output clock signal to generate sample data, and outputting the output clock based on a logic state of the sample data. The duty ratio of the signal CLKOUT is detected and a duty-up signal DUP and a duty-down signal DDN are generated. The duty cycle code generator 150 generates a duty cycle code CODE_DCC based on the duty-up signal DUP and the duty-down signal DDN.

Unlike the duty correction circuit 100 of FIG. 1, the duty cycle correction circuit 200 of FIG. 15 is based on the duty-up signal DUP and the duty-down signal DDN that are outputs of the duty detector 120. Generates the code CODE_DCC. The duty cycle correction unit 110 generates an output clock signal CLKOUT by correcting a duty ratio of the input clock signal CLKIN in response to the duty correction code CODE_DCC.

16 is a block diagram illustrating one example of a delayed synchronization loop circuit 300 including a duty cycle correction circuit according to embodiments of the present invention.

Referring to FIG. 16, the delay synchronization loop circuit 300 includes a duty cycle corrector 310, a delay circuit 321, a duty detector 320, a replica path 340, and a phase detector 350.

The duty cycle correction unit 310 generates an output clock signal CLKOUT by correcting the duty ratio of the input clock signal CLKIN in response to the duty-up signal DUP and the duty-down signal DDN. The delay circuit 321 delays the output clock signal CLKOUT to generate the delayed output clock signal CLKOUT_D. The duty detector 320 inverts the phase of the delayed output clock signal CLKOUT_D to generate an inverted and delayed output clock signal CLKOUT_BD, and outputs the output clock signal CLKOUT to the inverted delayed output clock signal CLKOUT_BD. Locks the signal, samples the output clock signal CLKOUT using the inverted delay output clock signal CLKOUT_BD to generate sample data, and outputs the duty of the output clock signal CLKOUT based on the logic state of the sample data. A duty ratio is detected and a duty-up signal (DUP) and a duty-down signal (DDN) are generated. After the duty ratio correction is completed, the replica path 340 delays the delayed output clock signal CLKOUT_D to generate the feedback signal FBCK. After the duty ratio correction is completed, the phase detector 350 detects a phase difference between the input clock signal CLKIN and the feedback signal FBCK to generate an up signal UP and a down signal DN, and generate an up signal UP. And a down signal DN to the delay circuit 321.

The delay circuit 321 included in the delay lock loop 300 of FIG. 16 may have a configuration of the delay lock loop 121 as shown in FIG. 13. Thus, the delay circuit 321 may include a delay line with interpolators D1, D2, D3, D4, and D5 and an interpolator 122.

The duty detector 320 may include an inverter INV1, a first flip-flop 324, a second flip-flop 325, and a control circuit 326.

The inverter INV1 inverts the phase of the delayed output clock signal CLKOUT_D to generate the inverted delayed output clock signal CLKOUT_BD. The first flip-flop 324 samples the output clock signal CLKOUT in response to the falling edge of the inverted delayed output clock signal CLKOUT_BD and generates first sample data SA. The second flip-flop 325 samples the output clock signal CLKOUT in response to the rising edge of the inverted delayed output clock signal CLKOUT_BD and generates second sample data SB. The control circuit 326 may include a delay-up signal DLYUP, a delay-down signal DLYDN, and a duty-up signal DUP based on logic states of the first sample data SA and the second sample data SB. And a duty-down signal (DDN).

The control circuit 326 may include a duty control circuit 327 and a delay control circuit 328. The delay control circuit 328 generates a delay-up signal DLYUP, a delay-down signal DLYDN, and an output enable signal ED_ALIGN based on the logic state of the second sample data SB. The duty control circuit 327 generates the duty-up signal DUP and the duty-down signal DDN based on the logic state of the output enable signal ED_ALIGN and the first sample data SA.

In the duty cycle correction mode, the delay circuit 321 adjusts the delay time of the output clock signal CLKOUT based on the delay-up signal DLYUP and the delay-down signal DLYDN, which are output signals of the duty detector 320, The duty cycle correction unit 310 generates an output clock signal CLKOUT by correcting the duty ratio of the input clock signal CLKIN in response to the duty-up signal DUP and the duty-down signal DDN. After the duty cycle correction is completed, in the normal mode, the delay circuit 321 adjusts the delay time of the output clock signal CLKOUT based on the up signal UP and the down signal DN, which are outputs of the phase detector 350. The delay synchronization loop circuit 300 detects a phase difference between the input clock signal CLKIN and the feedback signal FBCK and generates an internal clock signal ICLK synchronized with the input clock signal CLKIN.

17 is a block diagram illustrating another example of a delayed synchronization loop circuit 400 including a duty cycle correction circuit according to embodiments of the present invention.

Referring to FIG. 17, the delay lock loop circuit 400 may include a duty cycle corrector 410, a delay circuit 421, a duty detector 420, a replica path 440, a phase detector 450, and a duty correction code. Generator 460.

The delay lock loop 400 shown in FIG. 17 generates a duty compensation code CODE_DCC based on the duty-up signal DUP and the duty down signal DDN in the delay lock loop 300 of FIG. 16. The duty-correction code generator 460 is added to the circuit. The duty cycle corrector 410 generates an output clock signal CLKOUT by correcting a duty ratio of the input clock signal CLKIN in response to the duty correction code CODE_DCC.

18 is a block diagram illustrating an example of a semiconductor device including a delayed synchronization loop circuit 500 according to example embodiments.

Referring to FIG. 18, the semiconductor device 500 may include a delay synchronization loop circuit 510 and an internal circuit 520.

The delay synchronization loop circuit 510 includes a duty correction circuit and generates an internal clock signal ICLK synchronized with an external clock signal and subjected to duty cycle correction. The internal circuit 520 operates in response to the internal clock signal ICLK. The delayed synchronization loop circuit 510 may have a circuit configuration shown in FIG. 16 or 17.

Therefore, the duty cycle correction circuit including the duty detector according to the embodiment of the present invention digitally adjusts the delay time of the sampling clock signal and detects the duty of the output clock signal based on the logic state of the sampled data. The duty cycle correction circuit also locks the output clock signal CLKOUT using the inverted delayed output clock signal CLKOUT_BD to correct the duty ratio. Therefore, the duty cycle correction circuit according to the embodiment of the present invention can more accurately detect the duty of the output clock signal and generate an output clock signal having a duty ratio of 50:50.

19 is a flowchart illustrating a duty cycle correction method according to an embodiment of the present invention.

Referring to FIG. 19, a duty cycle correction method according to an embodiment of the present invention is as follows.

1) In response to the duty-up signal and the duty-down signal, the duty ratio of the input clock signal is corrected to generate an output clock signal (S1).

2) delay the output clock signal to generate a delayed output clock signal (S2).

3) Inverted and delayed output clock signals are generated by inverting the phase of the delayed output clock signal (S3).

4) The output clock signal is locked to the inverted delay output clock signal (S4).

5) The output clock signal is sampled using the inverted delay output clock signal to generate sample data (S5).

6) detects a duty ratio of the output clock signal based on the logic state of the sample data and generates the duty-up signal and the duty-down signal (S6).

20 is a flowchart illustrating a method of generating a delayed output clock signal included in the duty cycle correction method of FIG. 19. Referring to FIG. 20, a method of generating a delayed output clock signal according to an embodiment of the present invention is as follows.

1) The output clock signal is sampled at the rising edge of the inverted delayed output clock signal to generate first sample data (S21).

2) The delay time of the output clock signal is adjusted based on the logic state of the first sample data (S22).

21 is a flowchart illustrating a method of detecting a duty ratio of an output clock signal included in the duty correction method of FIG. 19. Referring to FIG. 21, a method of detecting a duty ratio of an output clock signal according to an embodiment of the present invention is as follows.

1) The output clock signal is sampled at the falling edge of the inverted delayed output clock signal to generate second sample data (S61).

2) The duty ratio of the output clock signal is detected based on the logic state of the second sample data (S62).

The duty cycle correction method according to the embodiment of the present invention performs the duty ratio correction according to the flowcharts shown in FIGS. 19 to 21. When the output clock signal CLKOUT and the inverted delay output clock signal CLKOUT_BD are locked and the duty ratio approaches 50:50, the output clock signal CLKOUT at the time of detection DP becomes the logic high state and the logic. Alternate between low states. As such, when the logic state of the output clock signal CLKOUT alternates between the logic high state and the logic low state, the duty cycle correction may be completed. In addition, the duty cycle correction time (eg, 200 cycles) may be determined in advance, the duty ratio correction may be repeatedly performed, and the duty cycle correction may be considered to be completed after the duty cycle correction time has passed.

The present invention is applicable to a semiconductor device including a clock generation circuit and a clock generation circuit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

100, 200: duty cycle correction circuit 110, 310, 410: duty cycle correction unit
120, 320, 420: duty detector 121, 321: delay circuit
122: interpolator 123: delay enable circuit
124, 125: flip-flops 126, 326, 426: control circuit
127, 327, 427: duty control circuit 128, 328, 428: delay control circuit
150: duty-correction code generator 300, 400, 510: delayed synchronization loop circuit
324, 325, 424, 425: flip-flop 340: replica path
350: phase detector 500: semiconductor device
520: internal circuit INV1: inverter
PS1: phase separator

Claims (10)

A duty cycle correction unit configured to generate an output clock signal by correcting a duty ratio of the input clock signal in response to the duty-up signal and the duty-down signal; And
Delaying the output clock signal to generate a delayed output clock signal, inverting the phase of the delayed output clock signal to generate an inverted and delayed output clock signal, and inverting the delayed output clock signal to the output clock signal And output the sample data by sampling the output clock signal using the inverted delayed output clock signal and adjusting the duty ratio of the output clock signal based on the logic state of the sample data. And a duty detector for detecting and generating the duty-up signal and the duty-down signal. The method of claim 1, wherein the duty detection unit
A delay time of the output clock signal is adjusted based on a logic state of the first sample data sampled at the rising edge of the inverted delayed output clock signal, and a falling edge of the inverted delayed output clock signal and a duty ratio of the output clock signal is detected based on a logic state of the second sample data sampling the output clock signal at the edge. The method of claim 1, wherein the duty detection unit
And a delay time of the output clock signal by using a delay line of a delay synchronization loop circuit. The method of claim 1, wherein the duty detection unit
A delay circuit configured to delay the output clock signal in response to a delay-up signal and a delay-down signal to generate the delayed output clock signal;
An inverter configured to invert a phase of the delayed output clock signal to generate the inverted delayed output clock signal;
A first flip-flop for sampling the output clock signal and generating first sample data in response to a falling edge of the inverted delayed output clock signal;
A second flip-flop for sampling the output clock signal and generating second sample data in response to a rising edge of the inverted delayed output clock signal;
And a control circuit for generating the delay-up signal, the delay-down signal, the duty-up signal, and the duty-down signal based on logic states of the first and second sample data. Duty compensation circuit. The method of claim 4, wherein the control circuit
A delay control circuit configured to generate the delay-up signal, the delay-down signal, and an output enable signal based on the logic state of the second sample data; And
And a duty control circuit for generating the duty-up signal and the duty-down signal based on the logic state of the output enable signal and the first sample data. The method of claim 4, wherein the duty detection unit
When the second sample data is in a logic low state, a delay-up signal is generated to increase a delay time of the output clock signal. When the second sample data is in a logic high state, a delay-down signal is generated to generate a delay-down signal. A duty cycle correction circuit, characterized in that to reduce delay time. The method of claim 4, wherein the duty detection unit
When the output enable signal is enabled and the first sample data is in a logic low state, a duty-up signal is generated to increase the duty ratio of the output clock signal, and the output enable signal is enabled and the first sample is generated. And a duty-down signal is generated when the data is in a logic high state to reduce the duty ratio of the output clock signal. The method of claim 4, wherein
And the delay circuit is a delay line of a delay synchronous loop circuit. The method of claim 1, wherein the duty detection unit
A delay circuit for delaying the output clock signal in response to a delay-up signal and a delay-down signal to generate the delayed output clock signal;
A phase separator for separating the phase of the delayed output clock signal to generate the inverted delayed output clock signal having a phase opposite to the delayed output clock signal and the delayed output clock signal;
A first flip-flop for sampling the output clock signal and generating first sample data in response to the delayed output clock signal;
A second flip-flop for sampling the output clock signal and generating second sample data in response to the inverted delay output clock signal;
And a control circuit for generating the delay-up signal, the delay-down signal, the duty-up signal, and the duty-down signal based on logic states of the first and second sample data. Duty compensation circuit. The method of claim 9,
The first flip-flop samples the output clock signal in response to the rising edge of the delayed output clock signal, and the second flip-flop samples the output clock signal in response to the rising edge of the inverted delayed output clock signal. Duty correction circuit, characterized in that.
KR1020100089654A 2010-06-07 2010-09-13 Duty correcting circuit having a duty detector, delay-locked loop circuit having the duty correcting circuit and method of duty correction KR20120027850A (en)

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US13/078,151 US8542045B2 (en) 2010-06-07 2011-04-01 Duty correcting circuit, delay-locked loop circuit and method of correcting duty

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101326117B1 (en) * 2013-06-25 2013-11-06 홍익대학교 산학협력단 A digital delay-locked loop using a phase-inversion algorithm and method for controlling the same
US10727826B2 (en) 2018-08-14 2020-07-28 Samsung Electronics Co., Ltd. Delay-locked loop circuit, semiconductor memory device, and methods of operating delay-locked loop circuit
CN117044108A (en) * 2021-03-25 2023-11-10 高通股份有限公司 Novel delay unit insensitive to PVT variation and generating quadrature clocks with equal rising/falling edges

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101326117B1 (en) * 2013-06-25 2013-11-06 홍익대학교 산학협력단 A digital delay-locked loop using a phase-inversion algorithm and method for controlling the same
US10727826B2 (en) 2018-08-14 2020-07-28 Samsung Electronics Co., Ltd. Delay-locked loop circuit, semiconductor memory device, and methods of operating delay-locked loop circuit
CN117044108A (en) * 2021-03-25 2023-11-10 高通股份有限公司 Novel delay unit insensitive to PVT variation and generating quadrature clocks with equal rising/falling edges

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