KR20120024387A - Semiconductor memory device and method of operationg the same - Google Patents

Abstract

In an embodiment, a semiconductor memory device may include an address controller configured to store defective column addresses and sequentially output the stored defective column addresses while a first control signal is activated; And a control logic for controlling data indicating a program path to be input to each of the main page buffers associated with the defective column addresses output from the address controller while the first control signal is activated.

Description

Semiconductor memory device and method of operation

The present invention relates to a semiconductor memory device and a method of operating the same.

An erase operation for erasing data stored in a memory cell of an electrically erasable and programmable nonvolatile semiconductor memory device and a program operation for storing data in the memory cell include FN tunneling and hot electron injection (FN). Hot electron injection is used.

In such a semiconductor memory device, when a memory cell connected to a bit line is defective, a repair is performed to replace it with a redundancy cell.

The repair operation is briefly described as follows.

First, an address of a defective cell detected by a test operation of a semiconductor memory device is stored in a storage device such as cam cells.

When power is input to the semiconductor memory device, the address of the defective cell stored in the storage device is loaded into the control logic.

The control unit determines whether the address input together with the operation command is the address of the defective cell, and controls the redundancy cell to be selected when the address of the defective cell is input.

Since such a repair operation is performed in a semiconductor memory device, a redundancy data input operation for inputting redundancy data into a page buffer connected to a bit line corresponding to each column address is necessary before programming data.

In the redundancy data input operation, the controller causes the data of "1", for example, to be stored in the page buffer connected to the bit line corresponding to the address of the defective cell, and the data of "0" in the remaining page buffer.

By such redundancy data input operation, unnecessary verification operation at the time of program verification operation can be avoided.

In general, the redundancy data input operation checks all column addresses in order to determine whether the address is a defective cell. That is, the operation time is long because all column addresses are checked and data is input to all page buffers.

According to an exemplary embodiment of the present invention, when performing redundancy data input, only the main page buffer connected to the bit line corresponding to the failed column address and the redundancy page buffer connected to the redundancy bit line corresponding to the redundant column address corresponding to the failed column address are used. Provided are a semiconductor memory device capable of selectively inputting redundancy data and a method of operating the same.

In a semiconductor memory device according to an embodiment of the present invention,

An address control unit for storing defective column addresses and sequentially outputting the stored defective column addresses while a first control signal is activated; And a control logic for controlling data indicating a program path to be input to each of the main page buffers associated with the defective column addresses output from the address controller while the first control signal is activated.

A semiconductor memory device according to another embodiment of the present invention,

Main page buffers respectively connected to the main column and connected to the data line in response to each of the plurality of first selection signals; Redundancy page buffers connected to a redundancy column and connected to the data lines in response to each of the plurality of second selection signals, and storing data representing program execution in response to each of the plurality of second control signals; An address controller which stores defective column addresses and sequentially outputs the defective column addresses while a first control signal is activated; While the first control signal is active, data indicating a program path is input through the data line, a main page buffer associated with a defective column address output from the address control unit, and a redundancy column replacing the defective column address. A control logic to output a page buffer selection signal for selecting a redundancy page buffer associated with the address; And enabling one of the plurality of first selection signals to select a main page buffer corresponding to the page buffer selection signal output from the control logic while the first control signal is activated, and selecting a redundancy page buffer. And a page buffer control circuit for enabling one of the plurality of second control signals.

The address control unit may include an address decoding unit for generating a decoded signal each time an external address is input while the first control signal is activated; And an address storage unit including a plurality of registers for storing the defective column addresses, respectively, and outputting a defective column address stored in a register selected according to the decoding signal.

The page buffer control circuit may include: a main page buffer selection circuit configured to output the first selection signal in response to the redundancy enable signal, the first control signal, and the page buffer selection signal; And a redundancy page buffer control circuit for outputting the second selection signal and the second control signal in response to the page buffer selection signal, the redundancy enable signal, and the first control signal.

The main page buffer control circuit is configured to perform a NAND combination of the redundancy enable signal and the inverted first control signal, a NAND gate, an output signal of the NAND gate, and the page buffer selection signal to perform the first selection. And a first AND gate for outputting a signal.

The redundancy page buffer control circuit may include: a second AND gate configured to AND-combine the page buffer selection signal and the redundancy enable signal; A third AND gate outputting the second control signal by AND combining the output signal of the second AND gate and the first control signal; And a fourth AND gate outputting the second selection signal by AND combining the output signal of the second AND gate and the signal inverting the first control signal.

The control logic may store '0' in the latches of the entire main page buffers and store '1' in the latches of the entire redundancy page buffers before activating the first control signal. .

The address control unit may further include an address latch circuit for temporarily storing a defective column address output from the address storage units and providing the defective column address to the mux.

In another embodiment, a method of operating a semiconductor memory device is provided.

Before starting the redundancy data input, inputting '0' into the latches of the main page buffers connected to the main column and inputting '1' into the latches of the redundancy page buffers connected to the redundancy column; Sequentially selecting a main page buffer associated with the defective column address for redundancy data input; And changing the data of the selected main page buffer to '1' and changing the data of the redundancy page buffer connected to the redundancy column line corresponding to the defective column address to '0'.

Selecting a main page buffer associated with the defective column address in order, the method comprising: sequentially selecting a storage unit in which the defective column addresses are stored each time an external address is input; Outputting a defective column address stored in the selected storage unit; And selecting a main page buffer associated with the output defective column address.

The semiconductor memory device and an operating method thereof according to an embodiment of the present invention can reduce redundancy data input time by inputting data by selecting only a failed main page buffer and a redundancy page buffer using a repaired column address.

1 shows a semiconductor memory device for explaining the present invention.
2 illustrates a logic group of FIG. 1.
3 illustrates the first storage unit of FIG. 2.
4A illustrates the main page buffer of FIG. 1.
4B illustrates the redundancy page buffer of FIG. 1.
5 illustrates the page buffer control circuit of FIG. 1.
6 is a flowchart illustrating a redundancy data input operation according to an embodiment of the present invention.
FIG. 7 is a timing diagram of control signals for explaining the redundancy data input operation of FIG. 6.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 shows a semiconductor memory device for explaining the present invention.

Referring to FIG. 1, the semiconductor memory device 100 may include a memory cell array 110, a page buffer group 120, an X decoder 130, a voltage supply circuit 140, an input / output circuit 150, and a page buffer control circuit. 160 and logic group 170.

The memory cell array 110 includes a plurality of memory blocks BK. Some of the memory blocks are used as cam blocks CBK for storing option information, repair column address information, and the like. The cam block CBK has the same structure as other memory blocks.

Each memory block BK includes a main cell unit 111 and a redundancy cell unit 112. The main cell unit 111 and the redundancy cell unit 112 include a plurality of cell strings CS. The cell strings CS of the main cell unit 111 and the redundancy cell unit 112 have the same structure.

In FIG. 1, only one of the cell strings CS of the main cell unit 111 is described in detail.

The cell string CS includes zeroth through thirty-first memory cells C0 through C31 connected in series between a drain select transistor DST and a source select transistor SST.

A drain select line DSL is connected to a gate of the drain select transistor DST, and a bit line is connected to a drain of the drain select transistor DST. The bit lines are divided into an even bit line BLe and an odd bit line BLO.

A source select line SSL is connected to the gate of the source select transistor SST, and a source of the source select transistor SST is commonly connected to the common source line SL.

The gates of the 0th to 31st memory cells C0 to C31 are connected to the 0th to 31st word lines WL0 to WL31, respectively.

The cell string CS of the redundancy cell unit 112 is replaced in place of the cell string in which the fail has occurred among the cell strings CS of the main cell unit 111, and is connected to the cell string of the main cell unit 111 in which the fail has occurred. The column address of the bit line is stored as a repair column address.

The repair column address is stored in the cam block CBK of the memory cell array 110 or by using a separate circuit (not shown) such as a fuse.

When the semiconductor memory device 100 starts to operate at an initial stage, the repair column address stored in the cam block CBK is loaded and stored in the storage means included in the logic group 170. It is used for operation.

The page buffer group 120 includes a main page buffer group 121 and a redundancy page buffer group 122. The main page buffer group 121 includes a plurality of main page buffers (MPBs), and the redundancy page buffer group 122 includes a plurality of redundancy page buffers (RPBs).

Each main page buffer MPB is connected to an even bit line BLe and an odd bit line BLo of the main cell unit 111, and each redundancy page buffer RPB is an even bit of the redundancy cell unit 112. It is connected to the line BLe and the odd bit line BLO pair.

The main page buffer MPB and the redundancy page buffer RPB store data for programming in the selected memory cell or read and store data stored in the selected memory cell.

The X decoder 130 includes a plurality of block selection circuits 131. Each block selection circuit 131 is connected to one memory block BK.

The block select circuit 131 according to the control signal provided from the logic group 170, the drain select line DSL, the source select line SSL, and the 0 th to 31 rd word lines of the memory block BK connected thereto. The WL0 to WL31 and the global drain select line GDSL of the voltage supply circuit 140, the global source select line GSSL, and the global word lines GWL0 to GWL31 are connected.

In response to a control signal from the logic group 170, the voltage supply circuit 140 may operate, for example, a program voltage Vpgm, a read voltage Vread, a pass voltage Vpass, an erase voltage Verase, or the like. Create

The operating voltage generated by the voltage supply circuit 140 is supplied to the global drain select line GDSL, the global source select line GSSL, and the global word lines GWL0 to GWL31 or the well of the memory block.

The input / output circuit 150 provides a data transfer path between the page buffer group 120 and the data input pad (not shown) in response to the control signal of the logic group 170. The page buffer control circuit 160 generates a control signal input to the main page buffer group 121 and the redundancy page buffer group 122 when a redundancy data input operation is performed.

The logic group 170 generates control signals for controlling the page buffer group 120, the X decoder 130, the voltage supply circuit 140, the input / output circuit 150, and the page buffer control circuit 160.

The logic group 170 also includes an address control unit (not shown) for address control and storage means (not shown) for temporarily storing the repaired column address. The logic group 170 uses a repair column address to connect the main page buffer MPB connected to the bit line corresponding to the failed column address and the redundancy connected to the bit line corresponding to the redundancy column address replacing the failed column address. The page buffer group 120 and the page buffer control circuit 160 are controlled to input redundancy data only to the page buffer RPB.

As described above, the semiconductor memory device replaces a bit line to which a defective cell string is connected with a redundancy bit line, and replaces a column address corresponding to a bit line to which a failed cell string is connected to a redundancy column.

The semiconductor memory device 100 performs a program in units of pages and performs program verification. The data state of the page buffers in which the result of the program verification is stored is checked to determine whether the program is passed.

In this case, since the program verification data is not normally stored in the main page buffer MPB connected to the failed column, the program operation cannot be completed normally. Therefore, before the program, the data corresponding to the program path is input to the main page buffer (MPB) connected to the failed column so that the main page buffer (MPB) is excluded from the program verification. The operation of inputting data representing a program path into the main page buffer MPB connected to the failed column is called a redundant data input operation.

In general, for redundancy data input, it is determined whether the first column to the last column of the main cell unit 111 are repaired in sequence, and the main page buffer MPB connected to the repaired column receives data that can be determined as a program pass. The process of saving was done. Therefore, it took a long time to check all the columns.

According to an embodiment of the present invention, only the main page buffer MPB connected to a failed column is input to input data determined as a program pass.

To this end, the logic group 170 of FIG. 1 is configured as follows.

2 illustrates a logic group of FIG. 1.

Referring to FIG. 2, the logic group 170 includes a control logic 171 and an address controller 172. The logic group 170 includes more logic for a program, a read operation, and the like, but FIG. 2 shows only a part for describing an embodiment of the present invention.

The control logic 171 outputs control signals for performing an operation of the semiconductor memory device 100 including a program, a read operation or a redundancy data input.

In response to the redundancy data input enable signal Red_input_en, the address controller 172 outputs the external address AX <13: 2> as it is in the normal operation mode, and the previously stored repair in the redundancy data input operation mode. Output addresses in order. The external address AX <13: 2> is output from a separate logic (not shown) for address control of the logic group 170 and is input to the address control unit 172.

The repair address is stored in the cam block CBK, and is read from the cam block CBK and stored in the initial operation of the semiconductor memory device 100.

To this end, the address controller 172 includes a Y redundancy decoder 173, a storage unit 174, an address latch unit 175, and a mux 176. The storage unit 174 includes first to nth (n is a natural number greater than 1) storage units 174a. The n repair addresses are stored in the first through nth storage units 174a, respectively.

Since the first to nth storages 174a all have the same circuit configuration, they are indicated by one reference numeral.

The Y redundancy decoder 173 operates in response to the redundancy data input enable signal Red_input_en. The Y redundancy decoder 173, when an external address AX <13: 2> is input, first and second Y passes for sequentially enabling the first to nth storage units 174a of the storage unit 174. Signal (YPASS_REDADD <A: i>, YPASS_REDADD <B: j>,

)

The Y redundancy decoder 173 counts from 1 to n, and according to the counting order, the first pass signals YPASS_REDADD <A: 1> to YPASS_REDADD <A: n> and the second pass signal YPASS_REDADD <B: 1> through YPASS_REDADD <B: n>).

Among the repair addresses stored in the storage unit 174, the repair address stored in the k-th storage unit 174a selected by the Y redundancy decoder 173 is output as the cam latch address AX_CAM_Pre <13: 2>.

The address latch unit 175 temporarily stores the cam latch address AX_CAM_Pre <13: 2> and outputs it as a cam address AX_CAM <13: 2> in response to a control signal from the control logic 171. The cam address AX_CAM <13: 2> is one of the repair addresses stored in the cam block.

The external address AX <13: 2> input to the Y redundancy decoder 173 is also input to the mux 176.

The mux 176 selects one of the external address AX <13: 2> or the cam address AX_CAM <13: 2> according to the redundancy data input enable signal Red_input_en from the control logic 171. Output as an address.

The control logic 171 controls a redundancy data input operation of inputting data representing a pass result into a main page buffer MPB connected to a column selected by an internal address.

The control logic 171 inputs data representing the program pass result to the main page buffer MPB connected to the column selected by the internal address output from the mux 176.

On the other hand, the first to n-th storage unit 174a is configured as follows.

3 illustrates the first storage unit of FIG. 2.

The first to nth storage parts 174a of FIG. 2 all have the same circuit. Therefore, in FIG. 3, the first storage unit 174a is representatively shown.

Referring to FIG. 3, the first storage unit 174a includes the first PMOS transistor P1, the first through fourteenth NMOS transistors N1 through N14, the first inverter IN1, the AND gate AND, The address latch circuit portion 174b is included.

The first PMOS transistor P1 and the first and second NMOS transistors N1 and N2 are connected in series between a power supply voltage input terminal and a ground node. The gate of the first PMOS transistor P1 is connected to the ground node. Therefore, the first PMOS transistor P1 is always kept turned on.

The first pass signal YPASS_REDADD <1> is input to the gate of the first NMOS transistor N1. The second pass signal YPASS_REDADD <1> is input to the gate of the second NMOS transistor N2.

The node K1, which is a connection point between the first PMOS transistor P1 and the first NMOS transistor N1, is connected to an input terminal of the first inverter IN1. The first inverter IN1 is connected between the node K1 and the input terminal of the AND gate AND.

One of the two input signals input to the AND gate AND is an output signal of the first inverter IN1, and the other is a redundancy check signal REDCHKEN.

The output of the AND gate AND is input to the node K2.

The address latch circuit 174b stores the repair address in response to the control signal of the control logic 171. In an embodiment of the present invention, the repair address is an address of a failed column. The column address consists of 12 bits. That is, the repair address is composed of 12 bits of address bits. In addition, the address latch circuit 174b includes twelve latch circuits (not shown) capable of storing address bits one bit at a time.

Each of the address bits stored in the twelve latch circuits (not shown) is output to the cam latch address AX_CAM_Pre <13: 2> through the third to fourteenth NMOS transistors N3 to N14.

The third to fourteenth NMOS transistors N3 to N14 are connected to a latch circuit (not shown) which stores address bits in the address latch circuit 174b, respectively, and are turned on in response to the output of the AND gate AND.

The cam latch address AX_CAM_Pre <13: 2> is stored in the address latch unit 175 for each address bit. Therefore, the address latch unit 175 also includes latch circuits (not shown) for storing 12 cam latch address bits.

The address latch unit 175 outputs the stored cam latch address AX_CAM_Pre <13: 2> as the cam address AX_CAM <13: 2>. The mux 176 selects one of the cam address AX_CAM <13: 2> and the external address AX <13: 2> according to the redundancy data input enable signal Red_input_en, thereby selecting the internal address AX_int <13: 2>).

The control logic 171 inputs data representing the program path only to the main page buffer MPB selected according to the internal address AX_int <13: 2>.

To this end, when the redundancy data input operation is performed, operations of the main page buffer group 121 and the redundancy page buffer group 122 should be controlled separately. That is, the page buffer control circuit 160 separately inputs control signals input to the main page buffer group 121 and the redundancy page buffer group 122.

The main page buffer MPB and the redundancy page buffer RPB of the semiconductor memory device 100 according to the embodiment are as follows.

4A illustrates the main page buffer of FIG. 1, and FIG. 4B illustrates the redundancy page buffer of FIG. 1.

The circuits of the main page buffer MPB and the redundancy page buffer RPB of FIGS. 4A and 4B include the first main page buffer MPB and the redundancy page buffer group 122 of the main page buffer group 121 of FIG. 1. The first redundancy page buffer (RPB) is representatively shown, and only parts necessary for describing an embodiment of the present invention are shown.

Referring to FIG. 4A, the main page buffer MPB includes the second PMOS transistor P2, the fifteenth to twentieth NMOS transistors N15 to N20, and the second and third inverters IN2 and IN3. The second PMOS transistor P2 is connected between the power supply voltage input terminal and the first sensing node SO1 and precharges the first sensing node SO1 in response to the precharge signal PRECH.

The first sensing node SO1 is connected to the selected bit line BLe or BLo. The fifteenth NMOS transistor N15 is connected between the first sensing node SO1 and the node QC. The transmission signal TRAN is input to the gate of the fifteenth NMOS transistor N15.

The second and third inverters IN2 and IN3 are connected by a latch circuit between the node QC and the node QC_N.

The sixteenth NMOS transistor N16 is connected between the node QC and the node K3, and the seventeenth NMOS transistor N17 is connected between the node QC_N and the node K3.

The main reset control signal CRST is input to the gate of the sixteenth NMOS transistor N16, and the main set control signal CSET is input to the gate of the seventeenth NMOS transistor N17.

An eighteenth NMOS transistor N18 is connected between the node K3 and a ground node, and a gate of the eighteenth NMOS transistor N18 is connected to the first sensing node SO1.

The nineteenth NMOS transistor N19 is connected between the node QC and the first data line BITOUTb, and the twentieth NMOS transistor N20 is connected between the node QC_N and the second data line BITOUT. do.

The main first page buffer select signal PBSEL_PB <1> is connected to gates of the 19th NMOS transistor N19 and the 20th NMOS transistor N20. Since the main page buffer MPB of FIG. 4A is the first main page buffer MPB of the main page buffer group 121, the first page buffer selection signal PBSEL_PB <1> is input. The other main page buffers MPB are input with respective page buffer selection signals. For example, the k th page buffer selection signal PBSEL_PB <k> is input to the k th main page buffer MPB.

Meanwhile, referring to the redundancy page buffer RPB with reference to FIG. 4B, the redundancy page buffer RPB includes the third PMOS transistor P3, the twenty-first through twenty-seventh NMOS transistors N21 through N27, and the fourth and fifth Inverters IN4 and IN5 are included.

The third PMOS transistor P3 is connected between the power supply voltage input terminal and the second sensing node SO2 and precharges the second sensing node SO2 in response to the precharge signal PRECH.

The second sensing node SO2 is connected to the bit line BLe or BLo selected by the redundancy cell unit 112.

The twenty-first NMOS transistor N21 is connected between the second sensing node SO2 and the node RED_QC, and a transmission signal TRAN is input to a gate of the twenty-first NMOS transistor N21.

The fourth and fifth inverters IN4 and IN5 are connected by a latch circuit between the node RED_QC and the node RED_QC_N.

The twenty-second NMOS transistor N22 is connected between the node RED_QC and the node K4, and the twenty-third NMOS transistor N23 is connected between the node RED_QC_N and the node K4.

The redundancy reset signal RED_CRST is input to the gate of the twenty-second NMOS transistor N22, and the redundancy set signal RED_CSET is input to the gate of the twenty-third NMOS transistor N23.

The 24 th NMOS transistor N24 is connected between the node K4 and the ground node, and the gate of the 24 th NMOS transistor N24 is connected to the second sensing node SO2.

The 25 th NMOS transistor N25 is connected between the node RED_QC and the first data line BITOUTb, and the 26 th NMOS transistor N26 is connected between the node REC_QC_N and the second data line BITOUT. do.

The first redundancy page buffer selection signal PBSEL_RED_PB <1> is input to the gates of the 25th and 26th NMOS transistors N25 and N26.

The 27th NMOS transistor N27 is connected between the node RED_QC_N and the ground node, and the first redundancy input enable signal REDIN_EN <1> is input to the gate of the 27th NMOS transistor N27.

Since the redundancy page buffer RPB of FIG. 4B is the first redundancy page buffer RPB of the redundancy page buffer group 122 of FIG. 1, the first redundancy page buffer selection signal PBSEL_RED_PB <1> and the first redundancy input in The enable signal REDIN_EN <1> is input.

The other redundancy page buffers (RPBs) are input with respective redundancy page buffer selection signals and redundancy input enable signals.

In the main page buffer MPB and the redundancy page buffer RPB of FIGS. 4A and 4B, the precharge signal PRECH and the transmission signal TRAN are simultaneously connected to the main page buffer MPB and the redundancy page buffer RPB. Common signal to be input.

The main reset signal CRST, the redundancy reset signal RED_CRST, the main set signal CSET, and the redundancy set signal RED_CSET are separately input to the main page buffer MPB and the redundancy page buffer RPB.

When the control logic 171 starts the redundancy data input operation, the node QC_N of the main page buffer MPB is set to '0', and the node RED_QC_N of the redundancy page buffer RPB is set to '1'.

Therefore, for this purpose, the main reset signal CRST, the main set signal CSET, the redundancy reset signal RED_CRST and the redundancy set signal RED_CSET are separately output as described above.

In addition, the page buffer control circuit 160 is required to control the operation of the main page buffer MPB and the redundancy page buffer RPB.

5 illustrates the page buffer control circuit of FIG. 1.

In FIG. 5, the control signals for controlling the main page buffer MPB of FIG. 4A and the redundancy page buffer RPB of FIG. 4B are output from the page buffer control circuit 160.

Referring to FIG. 5, the page buffer control circuit 160 includes a main page buffer controller 161 and a redundancy page buffer controller 162.

The main page buffer controller 161 includes a first NAND gate NA1, a first AND gate AN1, and a sixth inverter IN6.

The redundancy page buffer controller 162 includes second to fourth AND gates AN2 to AN4 and a seventh inverter IN7.

The sixth inverter IN6 inverts and outputs the redundancy data input enable signal Red_input_en from the control logic 171.

The output of the sixth inverter IN6 is input to the first NAND gate NA1. The redundancy enable signal RED_EN is input to the other input terminal of the first NAND gate NA1.

The output of the first NAND gate NA1 is input to the first AND gate AN1. The first page buffer select signal PBSEL <1> is input to the other input terminal of the first AND gate AN1.

The output of the first AND gate AN1 becomes the first main page buffer selection signal PBSEL_PB <1>.

The first page buffer selection signal PBSEL <1> and the redundancy enable signal RED_EN are input to the second AND gate AN2 of the redundancy page buffer control circuit 162.

The output of the second AND gate AN2 becomes the redundancy select signal PBSEL_RED.

The redundancy select signal PBSEL_RED is input to the third and fourth AND gates AN3 and AN4.

The redundancy data input enable signal Red_input_en is input to the other input terminal of the third AND gate AN3.

The seventh inverter IN7 inverts and outputs the redundancy data input enable signal Red_input_en. The output of the seventh inverter IN7 is input to the fourth and gate AN4.

The output of the third AND gate AN3 becomes the first redundancy input enable signal REDIN_EN <1>. The output of the fourth AND gate AN4 becomes the first redundancy page buffer selection signal PBSEL_RED_PB <1>.

The page buffer control circuit 160 selects one of the main page buffer MPB and the redundancy page buffer RPB. The redundancy data input operation is performed by the control signal from the control logic 171.

6 is a flowchart illustrating a redundancy data input operation according to an exemplary embodiment of the present invention, and FIG. 7 is a timing diagram of control signals for explaining the redundancy data input operation of FIG. 6.

6 and 7 will be described with reference to FIGS. 1 to 5.

6 and 7, when the redundancy data input operation is started (S601), the control logic 171 enables the redundancy data input enable signal Red_input_en. The node QC_N of the main page buffer MPB is made '0' and the node RED_QC_N of the redundancy page buffer RPB is made '1' (S603).

To this end, a low level precharge signal PRECH is input to the page buffer group 120. The precharge control signal PRECH is output from the control logic 171.

In response to the precharge control signal PRECH, the first and second sensing nodes SO1 and SO2 of the main page buffer MPB and the redundancy page buffer RPB are respectively precharged to a high level.

When the first and second sensing nodes SO1 and SO2 become high, respectively, the eighteenth NMOS transistor N18 of the main page buffer MPB and the twenty-fourth NMOS transistor N24 of the redundancy page buffer RPB are connected to each other. It is turned on. Accordingly, the nodes K3 and K4 are connected to the ground node.

When the main set signal CSET is input to the high level in the main page buffer MPB while the node K3 is connected to the ground node, the 17th NMOS transistor N17 is turned on and the node QC_N is connected to the ground node. Connected. That is, the node QC_N becomes '0'.

When the redundancy set signal RED_CRST is input at the high level to the redundancy page buffer RPB while the node K4 is connected to the ground node, the 22nd NMOS transistor N22 is turned on and the node RED_QC is grounded. Is connected to the node. Therefore, the node RED_QC_N becomes '1'.

If the nodes QC_N and RED_QC_N of the main page buffer MPB and the redundancy page buffer RPB are set differently as described above, the control logic 171 causes the Y redundancy decoder 173 to start address counting (S605). .

During the redundancy data input operation, the Y redundancy decoder 173 stores the storage unit 174 in the first to nth storage units of the storage unit 174 in accordance with the timing at which the external address AX <13: 2> is input. The first and second pass signals YPASS_REDADD <A: i> and YPASS_REDADD <B: j> for selecting one of 174a are decoded.

That is, during the redundancy data input operation, the Y redundancy decoder 173 performs address counting to sequentially select the first to nth storage units 174a according to the timing at which the external address is input, regardless of the external address. The first and second pass signals YPASS_REDADD <A: i> and YPASS_REDADD <B: j> are thus output.

If n repair addresses are stored, the Y redundancy decoder 173 performs address counting from '1' to 'n', and accordingly the first and second pass signals YPASS_REDADD <A: i> and YPASS_REDADD <B: j>).

The repair address stored in one of the first to nth storage units 174a of the storage unit 174 is stored as the cam latch address by the first and second pass signals YPASS_REDADD <A: i> and YPASS_REDADD <B: j>. Output as (AX_CAM_Pre <13: 2>).

In FIG. 6, when the Y redundancy decoder 173 starts address counting according to the external address input timing (S605), the first and second pass signals YPASS_REDADD <A: 1> and YPASS_REDADD <B: 1> Is output.

Accordingly, the first storage unit 174a of FIG. 2 is selected.

If the repair address stored in the first storage unit 174a is the address of the first column of the main cell unit 111, the first main page buffer MPB and the first main page buffer are controlled by the control signals of the control logic 171. Redundancy data is input to the nodes QC_N and RED_QC_N in the first redundancy page buffer RPB used in place of the first main page buffer MPB.

To this end, the control logic 171 inputs the redundancy enable signal RED_EN, the first page buffer select signal PBSEL <1>, and the redundancy select signal PBSEL_RED to the page buffer control circuit 160 at a high level. do. The first page buffer selection signal PBSEL <1> is determined according to the repair address stored in the first storage unit 174a. If the repair address stored in the first storage unit 174a was the address of the tenth column, the tenth page buffer selection signal PBSEL <10> is output.

The first NAND gate NA1 of the page buffer control circuit 160 NAND combines the high level redundancy enable signal RED_EN and the low level inverted redundancy data input signal Red_input_en. At this time, the output of the first NAND gate NA1 is at a high level. The first AND gate AN1 combines the output of the high level first NAND gate NA1 with the high level first page buffer selection signal PBSEL <1>.

The output of the first AND gate AN1 becomes the first main page buffer selection signal PBSEL_PB <1>. Therefore, the first page buffer selection signal PBSEL_PB <1> becomes high level.

When the first main page buffer selection signal PBSEL_PB <1> becomes high, the nineteenth and twentieth NMOS transistors N19 and N20 of the main page buffer MPB of FIG. 4A are turned on.

At this time, when '0' is input to the first data line BITOUTb and '1' is input to the second data line BITOUT, the node QC_N of the main page buffer MPB is changed to '1'.

When the node QC_N becomes '1', it is determined that the bit line BLe or BLo, that is, the column line, connected to the corresponding main page buffer MPB is the program pass during the program verification.

On the other hand, the second AND gate AN2 combines and combines the high level first page buffer selection signal PBSEL <1> with the redundancy enable signal RED_IN. The output of the second AND gate AN2 is at a high level. Therefore, the redundancy select signal PBSEL_RED is at a high level.

Since the redundancy data input enable signal Red_input_en is at a high level, the third and gate AN3 outputs the first redundancy input enable signal REDIN_EN <1> at a high level, and the fourth and gate AN4. Outputs a low level first redundancy page buffer selection signal PBSEL_RED_PB <1>.

Accordingly, the 25th and 26th NMOS transistors N25 and N26 of the redundancy page buffer RPB of FIG. 4B are turned off. Therefore, data of the first and second data lines BITOUTb and BITOUT are not input to the redundancy page buffer RPB.

In addition, since the first redundancy input enable signal REDIN_EN <1> is at a high level, the 27th NMOS transistor N27 is turned on. Therefore, the node RED_QC_N becomes '0'.

According to the above operation, the node QC_N of the main page buffer MPB connected to the failed column is inputted with '1', and the node of the redundancy page buffer RPB connected to the redundancy column replacing the failed column. (RED_QC_N) becomes '0'.

The Y redundancy decoder 173 continues counting the address according to the external address input timing until the address of the nth storage unit 174a is outputted, and thereby the first and second pass signals YPASS_REDADD <A: i> and YPASS_REDADD. Outputs <B: j>). The repair addresses stored in the storage unit 174 are sequentially output in accordance with the first and second pass signals YPASS_REDADD <A: i> and YPASS_REDADD <B: j>.

Finally, the mux selects the cam address AX_CAM <13: 2> according to the redundancy data input enable signal Red_input_en, and outputs the internal address. Therefore, the redundancy data is input only to the main page buffer MPB connected to the failed column and the redundancy page buffer RPB connected to the redundancy column instead of the failed column.

As a result, the redundancy data input time is reduced compared to the method of performing redundancy data input to all page buffers.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

160: page buffer control circuit
161: main page buffer control unit
162: redundancy page buffer control
170: logic group
171: control logic
172: address control unit

Claims (14)

An address control unit for storing defective column addresses and sequentially outputting the stored defective column addresses while a first control signal is activated; And
And a control logic for controlling data indicating a program path to be input to each of the main page buffers associated with respective defective column addresses output from the address controller while the first control signal is activated. The method of claim 1,
The address control unit,
An address decoding unit for generating a decoded signal each time an external address is input while the first control signal is activated; And
And a plurality of registers for storing the defective column addresses, respectively, and an address storage unit for outputting a defective column address stored in a register selected according to the decoding signal. The method of claim 2,
And a mux for outputting one of the external address and the defective column address according to the first control signal. The method of claim 1,
The control logic is,
While the first data indicating the program path is input to the latch of the main page buffer associated with the defective column address, the second data indicating program execution is input to the redundancy page buffer associated with the redundancy address to replace the defective column address. And a semiconductor memory device. Main page buffers respectively connected to the main column and connected to the data line in response to each of the plurality of first selection signals;
Redundancy page buffers connected to a redundancy column and connected to the data lines in response to each of the plurality of second selection signals, and storing data representing program execution in response to each of the plurality of second control signals;
An address controller which stores defective column addresses and sequentially outputs the defective column addresses while a first control signal is activated;
While the first control signal is active, data indicating a program path is input through the data line, a main page buffer associated with a defective column address output from the address control unit, and a redundancy column replacing the defective column address. A control logic to output a page buffer selection signal for selecting a redundancy page buffer associated with the address; And
Enabling one of the plurality of first selection signals to select a main page buffer corresponding to a page buffer selection signal output from the control logic while the first control signal is activated, and selecting a redundancy page buffer And a page buffer control circuit for enabling one of the plurality of second control signals. 6. The method of claim 5,
The address control unit,
An address decoding unit for generating a decoded signal each time an external address is input while the first control signal is activated; And
And a plurality of registers for storing the defective column addresses, respectively, and an address storage unit for outputting a defective column address stored in a register selected according to the decoding signal. The method of claim 6,
The address control unit,
And a mux for outputting one of the external address and the defective column address according to the first control signal. 6. The method of claim 5,
The page buffer control circuit,
A main page buffer selection circuit for outputting the first selection signal corresponding to the page buffer selection signal in response to the redundancy enable signal, the first control signal and the page buffer selection signal; And
A redundancy page buffer control circuit configured to output the second selection signal or the second control signal corresponding to the page buffer selection signal in response to the page buffer selection signal, the redundancy enable signal and the first control signal; A semiconductor memory device comprising. The method of claim 8,
The main page buffer control circuit,
A NAND gate NAND combining the redundancy enable signal and the inverted second control signal;
And a first AND gate outputting the first selection signal corresponding to the page buffer selection signal by AND combining the output signal of the NAND gate and the page buffer selection signal. The method of claim 9,
The redundancy page buffer control circuit,
A second AND gate for AND combining the page buffer selection signal and the redundancy enable signal;
A third AND gate outputting the second control signal corresponding to the page buffer selection signal by AND combining the output signal of the second AND gate and the first control signal; And
And a fourth AND gate outputting the second selection signal corresponding to the page buffer selection signal by AND combining the output signal of the second AND gate and the signal inverting the first control signal. 6. The method of claim 5,
The control logic is,
And "0" is stored in the latches of all the main page buffers and "1" is stored in the latches of all the redundancy page buffers before activating the first control signal. The method of claim 6,
The address control unit,
And an address latch circuit for temporarily storing a defective column address output from the address storage unit and providing the defective column address to the mux. Before starting the redundancy data input, inputting '0' into the latches of the main page buffers connected to the main column and inputting '1' into the latches of the redundancy page buffers connected to the redundancy column;
Sequentially selecting a main page buffer associated with the defective column address for redundancy data input; And
Changing the data of the selected main page buffer to '1' and changing the data of the redundancy page buffer connected to the redundancy column line corresponding to the defective column address to '0'. . The method of claim 13,
In sequentially selecting the main page buffers associated with the defective column address,
Selecting a storage unit in which the defective column addresses are stored each time an external address is input;
Outputting a defective column address stored in the selected storage unit; And
Selecting a main page buffer associated with the output defective column address.

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