KR20120019965A

KR20120019965A - Fuse circuit

Info

Publication number: KR20120019965A
Application number: KR1020100083610A
Authority: KR
Inventors: 최원준
Original assignee: 주식회사 하이닉스반도체
Priority date: 2010-08-27
Filing date: 2010-08-27
Publication date: 2012-03-07

Abstract

The fuse circuit generates a pull-down signal and a pull-up signal that are sequentially enabled in response to the test mode signal, and generates a fuse screen signal by delaying the test mode signal by a predetermined period, and the fuse screen signal. And an output fuse signal generator configured to generate an output fuse signal in which the level transition is determined in response to the enable period.

Description

Fuse Circuit {FUSE CIRCUIT}

The present invention relates to a fuse circuit capable of detecting a fuse having an abnormal resistance value.

Semiconductor integrated circuit products use optional processing to change their mode. Conventional option treatments include bonding options, metal options, or fuse options.

In particular, the fuse option is widely used to replace an abnormal memory cell generated during a manufacturing process of a semiconductor memory device with a normal memory cell and to change a design of a semiconductor memory chip. The fuse option is implemented by cutting a fuse by irradiating a laser beam or by applying excessive current. A circuit having at least one fuse for the fuse option is called a fuse circuit.

On the other hand, a fuse included in the fuse circuit has an abnormal resistance value due to a defect generated in the manufacturing process, cutting of adjacent fuses or moisture introduced during the HAST (High Accelerated Stress Test) abnormal resistance value of the fuse included in the fuse circuit. Can have If a fuse included in the fuse circuit has an abnormal resistance value, a malfunction of the fuse circuit may be caused. Accordingly, there is a need for a method of detecting a fuse that causes a malfunction of the fuse circuit by screening the resistance value of the fuse included in the fuse circuit.

The present invention discloses a fuse circuit capable of detecting a fuse having an abnormal resistance value.

To this end, the present invention generates a pull-down signal and a pull-up signal that is sequentially enabled in response to the test mode signal, and a signal generation unit for generating a fuse screen signal by delaying the test mode signal by a predetermined interval, and the fuse screen Provided is a fuse circuit including an output fuse signal generator for generating an output fuse signal in which a level transition is determined in response to an enable period of a signal.

1 is a block diagram showing the configuration of a fuse circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a signal generation unit included in the fuse circuit shown in FIG. 1.
3 is a circuit diagram of an output fuse signal generation unit included in the fuse circuit of FIG. 1.
4 and 5 are timing diagrams for explaining the operation of the fuse circuit shown in FIG.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1 is a block diagram showing the configuration of a fuse circuit according to an embodiment of the present invention.

As shown in Fig. 1, the fuse circuit of this embodiment includes a signal generator 1 and an output fuse signal generator 2.

As illustrated in FIG. 2, the signal generator 1 includes a test mode signal processor 10, a first logic unit 11, an inverter IV10, and a second logic unit 13. The test mode signal processor 10 receives the inversion delay unit 100 that inverts the test mode signal TM and the output signal of the test mode signal TM and the inversion delay unit 100 and performs an AND operation. The third logic unit 101 is included. The first logic unit 11 receives the reset signal RSTB and the output signal of the test mode signal processor 10 to perform a logical sum operation. The inverter IV10 generates a fuse screen signal FS by inverting the output signal of the inversion delay unit 100. The second logic unit 13 receives the output signal of the inversion delay unit 100 and the reset pulse RSTP to perform an AND operation. Here, the reset signal RSTB is a signal that is enabled from a logic high level to a logic low level after a predetermined interval elapses after the power up period ends, and the reset pulse RSTP is input after a predetermined interval elapses after the power up period ends. It includes a pulse that becomes.

The signal generation unit 1 having the above configuration generates a pull-down signal PD enabled at the logic high level while the reset signal RSTB is disabled at the logic high level, and a pulse of the reset pulse RSTP is generated. Generates a pull-up signal PU that is enabled at a logic low level in the input period. In addition, the signal generator 1 may be turned on during the delay period of the inversion delay unit 100 when the test mode signal TM is enabled at the logic high level while the reset signal RSTB is enabled at the logic low level. Generates a pulldown signal PD that is enabled. In addition, the signal generation unit 1 may be configured as much as the enable period of the test mode signal TM from the time when the delay period of the inversion delay unit 100 elapses after the test mode signal TM is enabled at the logic high level. Generates a pull-up signal PU that is enabled at a logic low level during the interval. In addition, the signal generation unit 1 generates the fuse screen signal FS by inverting the test mode signal TM by the delay period of the inversion delay unit 100.

As shown in FIG. 3, the output fuse signal generator 2 includes a driver 20, a fuse detector 21, and an output unit 22. The driving unit 20 includes a PMOS transistor P20 that is turned on in response to the pull-up signal PU between the power supply voltage VDD and the node nd20, and a fuse F20 connected between the node nd20 and the node nd21. PMOS transistor P21 turned on in response to pull-up signal PU between node nd21 and node nd22, and in response to pull-down signal PD between node nd22 and ground voltage VSS. The fuse detecting unit 21 includes an NMOS transistor N21 that is turned on in response to the fuse screen signal FS between the node nd22 and the ground voltage VSS. The output unit 22 is connected to the output fuse signal F_OUT between the inverter IV20 and the power supply voltage VDD and the node nd22 to invert and buffer the signal of the node nd22 to output the output fuse signal F_OUT. And a PMOS transistor P22 that is turned on in response to the output fuse signal F_OUT between the node nd22 and the ground voltage VSS.

The output fuse signal generator 2 configured as described above drives the node nd22 to a logic low level after the power-up period ends, and the fuse screen in a section in which the test mode signal TM is enabled at a logic high level. In response to the signal FS and the pull-up signal PU, an output fuse signal F_OUT in which level transition is determined is generated.

Looking at the operation of the fuse circuit of the present embodiment described above, on the assumption that the fuse (F20) is cut as follows. 4 and 5, the enable period of the test mode signal TM is divided into a case of X and a case of Y, as follows.

As shown in FIG. 4, the reset signal RSTB transitions to a logic low level at a time t10 after the power-up period ends and the predetermined period elapses, and a pulse of the reset pulse RSTP is input. Accordingly, the pull-down signal PD is disabled at a logic low level, and the pull-up signal PU is enabled at a logic low level in a period t10 to t11 where a pulse of the reset pulse RSTP is input. Since the fuse F20 is cut, the node nd22 maintains the logic low level and the output fuse signal F_OUT maintains the logic high level by the logic high level enabled pull-down signal PD before t10. do.

Thereafter, when the test mode signal TM in which the enable section is set to X is input at time t12, the logic low level is enabled from time t13 at which the delay period of the inversion delay unit 100 has elapsed to time t15 at which the X section has elapsed. A pull-up signal PU and a fuse screen signal FS enabled at a logic high level.

At this time, the PMOS transistors P20 and P21 and the NMOS transistor N21 are simultaneously turned on by the pull-up signal PU enabled at the logic low level and the fuse screen signal FS enabled at the logic high level. The level of nd22 gradually rises. Since the enable section of the test mode signal TM is sufficiently secured as X, the level of the node nd22 rises to a logic high level, and the output fuse signal F_OUT transitions to a logic low level. When the output fuse signal F_OUT is output at a logic low level, the fuse F20 is recognized as not cut.

On the other hand, as shown in FIG. 5, when the enable period of the test mode signal TM is set to Y, the level of the node nd22 does not rise to the logic high level, so the output fuse signal F_OUT changes the logic high level. Keep it. Therefore, the fuse F20 is recognized as being cut.

As described above, the fuse circuit of the present exemplary embodiment may determine whether the output fuse signal F_OUT is level shifted by adjusting the enable period of the test mode signal TM. The level transition time of the output fuse signal F_OUT according to the enable period of the test mode signal TM is determined by the resistance value of the fuse. Therefore, a fuse having an abnormal resistance value can be detected on the basis of the information on the enable section of the test mode signal TM that shifts the level of the output fuse signal F_OUT in a fuse circuit having a fuse having a normal resistance value. have.

1: signal generator 10: test mode signal processor
100: reverse delay unit 2: output fuse signal generation unit
20: drive unit 21: fuse detection unit
22: output unit

Claims

A signal generation unit generating a pull-down signal and a pull-up signal which are sequentially enabled in response to the test mode signal, and generating a fuse screen signal by delaying the test mode signal by a predetermined period; And
And an output fuse signal generation unit configured to generate an output fuse signal in which a level transition is determined in response to an enable period of the fuse screen signal.

The fuse circuit of claim 1, wherein the signal generation unit generates the enabled pull-down signal when the reset signal is disabled, and generates the pull-up signal enabled in a section in which a pulse of the reset pulse is input.

3. The fuse circuit of claim 2, wherein the reset signal is a signal that is enabled after the power-up period ends, and the reset pulse includes a pulse input after the power-up period ends.

The fuse circuit of claim 3, wherein the signal generation unit generates the pull-down signal that is enabled during the predetermined period when the test mode signal is enabled while the reset signal is enabled.

5. The fuse of claim 4, wherein the signal generation unit generates the pull-up signal that is enabled for an interval equal to the enable interval of the test mode signal from the time when the predetermined interval elapses after the test mode signal is enabled. Circuit.

The method of claim 1, wherein the output fuse signal generation unit
A driving unit driving a first node in response to the pull-up signal and the pull-down signal;
A fuse detector configured to pull down the first node in response to the fuse screen signal; And
And an output unit configured to generate the output fuse signal by buffering the first node and to drive the first node in response to the output fuse signal.

The method of claim 6, wherein the driving unit
A first pull-up element connected between a power supply voltage and a second node and turned on in response to the pull-up signal;
A fuse connected between the second node and a third node;
A second pull-up element connected between the third node and the first node and turned on in response to the pull-up signal; And
And a first pull-down device connected between the first node and a ground voltage and turned on in response to the pull-down signal.

The fuse circuit of claim 7, wherein the fuse detector comprises a second pull-down element turned on in response to a fuse screen signal.